1. Theory
- Definition: A plasma asher removes photoresist and other organics by oxidising them in an oxygen plasma to CO and HO (MIT; NIST).
- Radicals, not ions: Barrel ashers shield the wafers so only radicals and neutrals reach them, giving an isotropic, selective etch (MIT; LSI Logic).
- Temperature dependence: Pure O ashing has an activation energy of 0.52 eV; hydrogen or water lowers it to about 0.4 eV and CF to about 0.1 eV, at the cost of etching oxide (Levenson and Waleh).
- Ion damage: Energetic ions can drive metals from the resist into underlying layers, which is why downstream ashing dominates (Levenson and Waleh).
2. Working Principle
- Barrel asher: Wafers on racks inside a perforated aluminium cage in a quartz vessel at about 1 Torr oxygen (LSI Logic).
- Microwave batch asher: 2.45 GHz, up to 1000 W, 0.6 mbar, 25 wafers (NIST).
- Single-wafer asher: 2.45 GHz microwave with a heated platen at 100 to 300 C and rates up to 3 m/min (NUS).
- Endpoint: Optical, from the plasma emission (NUS; Optical Emission Spectroscopy Endpoint (OES) page).
3. Applications
- Resist strip: After etch or implant (NIST; Levenson and Waleh).
- Descum: Short, gentle removal of residues in developed openings (NIST; Berkeley).
- Surface cleaning: Organic removal before further processing (NIST; my reading: complements the wet organic clean of the RCA Wet Bench page).
Ashing Chemistry and Rate
| Name | Formula | Related Formulae | Variables/Constants |
|---|---|---|---|
| Ashing reaction | |||
| Activation energies | |||
| Tool rates |
Barrel and Batch Ashers
| Name | Formula | Related Formulae | Variables/Constants |
|---|---|---|---|
| Barrel geometry | |||
| End-wafer effect | |||
| Microwave batch asher |
Downstream Ashing and Risks
| Name | Formula | Related Formulae | Variables/Constants |
|---|---|---|---|
| Downstream ashing | |||
| Fluorine and moisture risks | |||
| Endpoint |
Important Questions
Ques: How does a barrel asher remove photoresist without damaging the wafer?
By letting only radicals reach the wafers. MIT describes the barrel reactor as a chemical-only etcher whose shield keeps ion bombardment off the wafers, so the etch is isotropic and selective, with the resist removed as polymer + O CO + HO. LSI Logic’s patent describes the shield: a perforated aluminium cylinder, about 1/8 inch thick, inside the quartz vessel, filled with oxygen at about 1 . Ions striking the metal are grounded and neutralised, while radicals and neutral molecules pass through holes of 1/8 to 3/8 inch. Open cage ends let ions in, raising etch rate and damage on the end wafers. MIT notes poor edge-to-centre uniformity and use mainly for resist removal. Reference: MIT 6.152J Micro/Nano Processing Technology, lecture 17 ‘Etching’ (2005): barrel reactors with a shield keeping ions off the wafers, isotropic and selective chemical etching, poor edge-to-centre uniformity, used mostly for resist removal, polymer + O2 -> CO2 + H2O, macro-loading when too many wafers consume etchant, RIE at 10 to 100 mTorr, high-density plasmas at 1 to 10 mTorr (fetch-tool summary); T. G. Mallon (LSI Logic), ‘Faraday cage for barrel-style plasma etchers’, US Patent 5,362,353 (1994): perforated aluminium cylinder about 1/8 inch thick inside the quartz vessel, wafers on racks perpendicular to the axis, ions striking the metal grounded and neutralized while radicals and neutrals pass the perforations, open ends letting ions in and raising etch rate and damage on end wafers, vessel pumped to about 1 torr and filled with oxygen, holes 1/8 to 3/8 inch on 1/8 to 1/2 inch centres, example 1/4 inch on 3/8 inch (fetch-tool summary).
Ques: How do gas additives change the ashing rate?
By lowering the activation energy. Levenson and Waleh cite prior work: pure O has 0.52 , and adding N leaves it unchanged while raising the rate only from 0.1 to 0.2 at 160 . Adding 5 to 10 per cent H or water lowers it to about 0.4 and, with N, gives about 0.5 . O with CF drops it to about 0.1 and exceeds 1.5 , but etches silicon oxide. From 160 to 200 , the rate therefore rises 3.25 times at 0.52 but only 1.25 times at 0.1 (computed). A low activation energy allows lower process temperatures, as the patent notes. Reference: E. O. Levenson and A. Waleh (Anon, Inc.), ‘Process for ashing organic materials from substrates’, US Patent 6,231,775 (2001), background citing prior art: energetic ions driving heavy and alkali metals from resist into underlying layers, O2/CF4 raising ash rate but etching silicon oxide, oxygen ions forming water in spin-on glass and raising its dielectric constant, lower activation energy making the rate less temperature sensitive, pure O2 0.52 eV, O2 + N2 same activation energy with rate rising from 0.1 to 0.2 um/min at 160 C, 5 to 10 per cent H2 or H2O lowering it to about 0.4 eV, O2 + N2 + H2 or H2O about 0.5 um/min at 160 C, O2 + CF4 about 0.1 eV and above 1.5 um/min but etching the substrate, practical target above 0.5 um/min, downstream ashing the most widely used, hardened crust from high-dose implants and popping, substrate held from room temperature to 200 C (fetch-tool summary).
Ques: Why has downstream ashing replaced direct-plasma stripping?
To avoid ion damage and charging. Levenson and Waleh state that energetic ions can push heavy and alkali metals from resist impurities into underlying layers, shortening minority-carrier lifetime. Oxygen ions can also form water in spin-on glass, raising its dielectric constant and causing via poisoning. They describe downstream ashing as the most widely used method. The barrel shield of LSI Logic and MIT achieves part of this, but with poor uniformity and an end-wafer effect. In my reading, a downstream asher keeps the radical-only chemistry while treating one wafer at a time. The Samco PC-300 at NUS achieves 2 to 5 per cent within-wafer uniformity with optical endpoint, as on the Optical Emission Spectroscopy Endpoint (OES) page. Reference: E. O. Levenson and A. Waleh (Anon, Inc.), ‘Process for ashing organic materials from substrates’, US Patent 6,231,775 (2001), background citing prior art: energetic ions driving heavy and alkali metals from resist into underlying layers, O2/CF4 raising ash rate but etching silicon oxide, oxygen ions forming water in spin-on glass and raising its dielectric constant, lower activation energy making the rate less temperature sensitive, pure O2 0.52 eV, O2 + N2 same activation energy with rate rising from 0.1 to 0.2 um/min at 160 C, 5 to 10 per cent H2 or H2O lowering it to about 0.4 eV, O2 + N2 + H2 or H2O about 0.5 um/min at 160 C, O2 + CF4 about 0.1 eV and above 1.5 um/min but etching the substrate, practical target above 0.5 um/min, downstream ashing the most widely used, hardened crust from high-dose implants and popping, substrate held from room temperature to 200 C (fetch-tool summary); T. G. Mallon (LSI Logic), ‘Faraday cage for barrel-style plasma etchers’, US Patent 5,362,353 (1994): perforated aluminium cylinder about 1/8 inch thick inside the quartz vessel, wafers on racks perpendicular to the axis, ions striking the metal grounded and neutralized while radicals and neutrals pass the perforations, open ends letting ions in and raising etch rate and damage on end wafers, vessel pumped to about 1 torr and filled with oxygen, holes 1/8 to 3/8 inch on 1/8 to 1/2 inch centres, example 1/4 inch on 3/8 inch (fetch-tool summary); MIT 6.152J Micro/Nano Processing Technology, lecture 17 ‘Etching’ (2005): barrel reactors with a shield keeping ions off the wafers, isotropic and selective chemical etching, poor edge-to-centre uniformity, used mostly for resist removal, polymer + O2 -> CO2 + H2O, macro-loading when too many wafers consume etchant, RIE at 10 to 100 mTorr, high-density plasmas at 1 to 10 mTorr (fetch-tool summary); National University of Singapore E6 Nanofab, ‘Plasma asher (Samco PC-300)’ page: 2.45 GHz microwave, 1000 W, operating range listed as 0.5 to 5 mTorr, O2 1000 to 2000 sccm and N2 100 to 500 sccm, 200 mm wafers, ash rate up to 3 um/min or more, platen 100 to 300 C, uniformity 2 to 5 per cent within wafer and 2 to 4 per cent wafer to wafer, optical endpoint from plasma intensity (fetch-tool summary); Optical Emission Spectroscopy Endpoint (OES) page of this vault.
Ques: What pressure do ashers run at, and which value is more likely?
Roughly 0.5 to 1 ; the mTorr listing is unlikely. LSI Logic pumps its barrel vessel to about 1 of oxygen, and NIST’s PVA TePla 300 recipes run at 0.6 , which is 0.45 (computed). NUS lists its Samco PC-300 operating range as 0.5 to 5 , with oxygen flows of 1000 to 2000 . MIT places RIE at 10 to 100 and high-density plasmas at 1 to 10 , so a radical asher at a few mTorr would be unusual. Very high flows at mTorr pressure would also need very large pumps (my reading). The 0.45 to 1 figures are therefore more likely correct, and the NUS listing probably uses the wrong unit (my reading). Reference: T. G. Mallon (LSI Logic), ‘Faraday cage for barrel-style plasma etchers’, US Patent 5,362,353 (1994): perforated aluminium cylinder about 1/8 inch thick inside the quartz vessel, wafers on racks perpendicular to the axis, ions striking the metal grounded and neutralized while radicals and neutrals pass the perforations, open ends letting ions in and raising etch rate and damage on end wafers, vessel pumped to about 1 torr and filled with oxygen, holes 1/8 to 3/8 inch on 1/8 to 1/2 inch centres, example 1/4 inch on 3/8 inch (fetch-tool summary); NIST CNST NanoFab, ‘PVA TePla 300 Asher’ tool document: 2.45 GHz microwave plasma, 0 to 1000 W, 0.6 mbar working pressure in reference recipes, O2, Ar, N2 and CF4, 600 sccm O2 strip recipe, N2 then N2 + O2 at 200 sccm each with Faraday cage for descum, up to 25 wafers of up to 200 mm per batch, resist stripping, surface cleaning and descum (fetch-tool summary); National University of Singapore E6 Nanofab, ‘Plasma asher (Samco PC-300)’ page: 2.45 GHz microwave, 1000 W, operating range listed as 0.5 to 5 mTorr, O2 1000 to 2000 sccm and N2 100 to 500 sccm, 200 mm wafers, ash rate up to 3 um/min or more, platen 100 to 300 C, uniformity 2 to 5 per cent within wafer and 2 to 4 per cent wafer to wafer, optical endpoint from plasma intensity (fetch-tool summary); MIT 6.152J Micro/Nano Processing Technology, lecture 17 ‘Etching’ (2005): barrel reactors with a shield keeping ions off the wafers, isotropic and selective chemical etching, poor edge-to-centre uniformity, used mostly for resist removal, polymer + O2 -> CO2 + H2O, macro-loading when too many wafers consume etchant, RIE at 10 to 100 mTorr, high-density plasmas at 1 to 10 mTorr (fetch-tool summary).
Ques: What is descum, and how gentle is it?
A short, low-power ash that clears resist residue from developed openings. NIST’s PVA TePla 300 descum recipe uses nitrogen, then nitrogen and oxygen at 200 each, with the Faraday cage in place for every step, against 600 oxygen for a full strip. Berkeley’s Technics-c O descum at 50 removes unbaked resist at 330 . A 20 residue therefore clears in about 36 s (computed). At 400 , four wafers ashed 23 per cent slower than one (Berkeley), the macro-loading MIT describes. In my reading, descum time must be set for the actual load, or small features may stay scummed or lose linewidth. Reference: NIST CNST NanoFab, ‘PVA TePla 300 Asher’ tool document: 2.45 GHz microwave plasma, 0 to 1000 W, 0.6 mbar working pressure in reference recipes, O2, Ar, N2 and CF4, 600 sccm O2 strip recipe, N2 then N2 + O2 at 200 sccm each with Faraday cage for descum, up to 25 wafers of up to 200 mm per batch, resist stripping, surface cleaning and descum (fetch-tool summary); Marvell NanoLab (UC Berkeley) lab manual chapter 1.9 ‘VLSI etchants’: Technics-c O2 descum at 50 W and 51.1 sccm etching unbaked resist at 330 angstrom/min, at 400 W four wafers ashed 23 per cent slower than one (fetch-tool summary); MIT 6.152J Micro/Nano Processing Technology, lecture 17 ‘Etching’ (2005): barrel reactors with a shield keeping ions off the wafers, isotropic and selective chemical etching, poor edge-to-centre uniformity, used mostly for resist removal, polymer + O2 -> CO2 + H2O, macro-loading when too many wafers consume etchant, RIE at 10 to 100 mTorr, high-density plasmas at 1 to 10 mTorr (fetch-tool summary).
Ques: What goes wrong when ashing implanted or fluorinated resist?
Crusting, popping and substrate attack. Levenson and Waleh describe a hardened crust on resist after high-dose implants, which can pop during ashing and complicate later cleaning, and list sidewall polymers, via veils and metal fences as further residues. Adding CF speeds ashing above 1.5 but etches silicon oxide, so fluorine additions trade rate against selectivity. Oxygen ions can create water in spin-on glass. The patent’s own aim is low-temperature removal of the crust. In my reading, implanted resist is ashed at low temperature first, then fully, and any remaining inorganic residue is removed in a wet clean such as the sulfuric-peroxide step on the RCA Wet Bench page. Reference: E. O. Levenson and A. Waleh (Anon, Inc.), ‘Process for ashing organic materials from substrates’, US Patent 6,231,775 (2001), background citing prior art: energetic ions driving heavy and alkali metals from resist into underlying layers, O2/CF4 raising ash rate but etching silicon oxide, oxygen ions forming water in spin-on glass and raising its dielectric constant, lower activation energy making the rate less temperature sensitive, pure O2 0.52 eV, O2 + N2 same activation energy with rate rising from 0.1 to 0.2 um/min at 160 C, 5 to 10 per cent H2 or H2O lowering it to about 0.4 eV, O2 + N2 + H2 or H2O about 0.5 um/min at 160 C, O2 + CF4 about 0.1 eV and above 1.5 um/min but etching the substrate, practical target above 0.5 um/min, downstream ashing the most widely used, hardened crust from high-dose implants and popping, substrate held from room temperature to 200 C (fetch-tool summary); RCA Wet Bench page of this vault.
References
- E. O. Levenson and A. Waleh, “Process for ashing organic materials from substrates,” US Patent 6,231,775, Anon, Inc., 2001. Available: https://patents.google.com/patent/US6231775
- T. G. Mallon, “Faraday cage for barrel-style plasma etchers,” US Patent 5,362,353, LSI Logic, 1994. Available: https://patents.google.com/patent/US5362353
- MIT 6.152J Micro/Nano Processing Technology, “Lecture 17: etching,” MIT OpenCourseWare, 2005. Available: https://ocw.mit.edu/courses/6-152j-micro-nano-processing-technology-fall-2005/59b9f31d836355a3380aa156925508bc_lecture17.pdf
- NIST CNST NanoFab, “PVA TePla 300 asher,” tool document (web archive). Available: https://webarchive.library.unt.edu/web/20130214220525/http:/www.cnst.nist.gov/nanofab/pdf/PVA_Tepla_300_Asher.pdf
- National University of Singapore E6 Nanofab, “Plasma asher (Samco PC-300).” Available: https://cde.nus.edu.sg/e6nanofab/plasma-asher/
- Marvell NanoLab, UC Berkeley, “Chapter 1.9: VLSI etchants,” lab manual. Available: https://nanolab.berkeley.edu/labmanual/chap1/1.09vslietch.pdf
- RCA Wet Bench page of this vault.
- Optical Emission Spectroscopy Endpoint (OES) page of this vault.
Related pages in this vault: Wet Etch Bench, RCA Wet Bench, Optical Emission Spectroscopy Endpoint (OES), Photoresist and Process Window, Parallel-Plate Reactive Ion Etcher (RIE).