1. Theory

  • Definition: Resolution enhancement techniques push single-exposure imaging toward = 0.25, and multiple patterning goes below it by splitting or multiplying the pitch, reaching below 0.2 (ECE 695 L11).
  • Phase-shift masks: A 180 degree phase step between neighbouring openings makes their fields cancel in between; attenuated masks transmit a few to 20 per cent with a 180 degree shift (ECE 695 L10).
  • Proximity correction: Rule-based OPC applies table corrections, while model-based OPC and ILT optimize the mask with an imaging model against edge placement error and process-variation band (Chen et al.).
  • Source-mask optimization: The illumination pupil and the mask are optimized together to widen the process window (SMO preprint).
  • Pitch division: LELE splits a layout onto two masks; SADP and SAQP form lines from spacers, so pitch is halved or quartered and adjacent lines are self-aligned (ECE 695 L11; Abercrombie; More and Hegde).

2. Working Principle

  • Mask: Alternating PSMs are etched about 172 into quartz; attenuated PSMs use a MoSi absorber (ECE 695 L10).
  • OPC flow: Edges are biased, assist features added and fragments moved until the simulated contour matches the target (ECE 695 L10; Chen et al.).
  • LELE: Pattern and etch the first mask into a hard mask, then pattern and etch the second; overlay sets the spaces between the two sets (ECE 695 L11).
  • SADP and SAQP: Print mandrels, deposit a conformal spacer, etch it back, remove the mandrel, repeat for SAQP, and use a block or trim mask (Abercrombie; Ban et al.; More and Hegde).

3. Applications

  • Logic metal and fins: Spacer patterning with block masks for 1-D gratings (Ban et al.; Abercrombie).
  • DRAM active areas: SAQP at 22 to 26 pitch (More and Hegde).
  • Low-k1 critical layers: SMO and ILT for contacts and 2-D shapes (SMO preprint; Chen et al.).
  • Metrology demands: Pitch walk, overlay and CD must be measured per population (SPIE 10587 abstract; Overlay Metrology Tool page).

Phase-Shift Masks and Illumination

NameFormulaRelated FormulaeVariables/Constants
Alternating phase-shift mask

Attenuated phase-shift mask
Off-axis dipole example

Computational Lithography

NameFormulaRelated FormulaeVariables/Constants
Optical proximity correction
Process variation band
Source-mask optimization


Multiple Patterning

NameFormulaRelated FormulaeVariables/Constants
Litho-etch-litho-etch
Self-aligned double patterning

SAQP pitch walk

Important Questions

Ques: How does an alternating phase-shift mask improve resolution, and at what cost?

By making neighbouring fields cancel. ECE 695 L10 explains that a 180 degree phase step between adjacent openings causes destructive interference in the gap, and gives the quartz etch depth as = 172 at 193 , which recomputes to 172.3 (computed). The same lecture puts alternating PSM fabrication at about 10 times the cost of a binary mask. Attenuated PSMs are cheaper, using a MoSi absorber with a 180 degree shift, but the lecture quotes 6 to 20 per cent transmission on one slide and 5 to 15 per cent on another; the overlap, 6 to 15 per cent, is the safer range to assume (my reading). Chromeless phase lithography uses fully transparent features with only phase steps. Reference: ECE 695 Nanometer Scale Patterning and Processing, Lecture 10, ‘Optical Lithography - Resolution Enhancement Techniques’, Spring 2016, nanoHUB resource 24508: dipole example NA 1.2 with sigma 0.89/0.98, alternating PSM with 180 degree shift and fabrication cost 10x a binary mask, etch depth (lambda/2)/(1.56 - 1) = 172 nm, attenuated MoSi PSM 6 to 20 per cent transmission (5 to 15 per cent on another slide) with 180 degrees, chromeless phase lithography, OPC by biasing, scattering bars and sub-resolution squares, ILT mask data about 1000 GB, water NA limit 0.93 x 1.435 = 1.33 (fetch-tool summary).

Ques: What is the difference between rule-based OPC, model-based OPC and ILT?

How the correction is found. Chen et al. describe rule-based OPC as applying a pre-built correction table, fast but only locally correct; model-based OPC uses a physical imaging model and numerical optimization, either moving edge fragments or optimizing pixels, the latter being ILT. ILT produces free-form edges and assist features that improve fidelity but are hard to fracture into rectangular mask shots, and ECE 695 L10 notes ILT mask data of about 1000 . Chen et al. score masks by edge placement error and by the process variation band, the squared L2 norm between the extreme printed images, and report that their DiffOPC halves edge-based EPE at half ILT’s manufacturing cost. The PVB plays, in image space, the role of the dose-focus window (Photoresist and Process Window page; my reading). Reference: G. Chen, H. Yang, H. Ren, B. Yu and D. Z. Pan, ‘Differentiable Edge-based OPC’, arXiv:2408.08969: rule-based OPC from correction tables handling only local effects, model-based OPC split into edge-based and pixel-based (ILT), ILT free-form edges and SRAFs hard to manufacture, PVB as squared L2 norm between maximum and minimum printed images, EPE as resist-image distortion, DiffOPC halving EBOPC EPE at half ILT manufacturing cost (fetch-tool summary); ECE 695 Nanometer Scale Patterning and Processing, Lecture 10, ‘Optical Lithography - Resolution Enhancement Techniques’, Spring 2016, nanoHUB resource 24508: dipole example NA 1.2 with sigma 0.89/0.98, alternating PSM with 180 degree shift and fabrication cost 10x a binary mask, etch depth (lambda/2)/(1.56 - 1) = 172 nm, attenuated MoSi PSM 6 to 20 per cent transmission (5 to 15 per cent on another slide) with 180 degrees, chromeless phase lithography, OPC by biasing, scattering bars and sub-resolution squares, ILT mask data about 1000 GB, water NA limit 0.93 x 1.435 = 1.33 (fetch-tool summary); Photoresist and Process Window page of this vault.

Ques: What does source-mask optimization add beyond OPC?

It treats the illuminator as a variable too. The SMO preprint describes optimizing a pixelated source, 49 by 49 pixels or 2401 variables (computed), together with a pixelated mask including assist features, minimizing image-fidelity error plus a weighted process-window term. Its targets were CD within 5 per cent, exposure latitude of at least 18 per cent for 1-D and 13 per cent for 2-D features, and mask error factor below 2 and 4; over half the CD and EL values failed before optimization, and all met specification after three cycles. Freeform sources need thousands of variables, which programmable illuminators make possible (SMO preprint; High-NA DUV Immersion Scanner page). In the Hopkins picture, SMO changes both the TCCs and the mask orders (my reading). Reference: Preprints.org manuscript 202509.0754 on source-mask optimization (title and authors not shown in the fetched text): SMO used since the 22 nm node, freeform sources with thousands of variables, 49 x 49 pixel source, joint optimization with pixelated mask, SRAFs and MEF constraints, cost of image fidelity plus a weighted process-window term, specifications CD +/-5 per cent, EL at least 18 per cent (1D) and 13 per cent (2D), MEF below 2 (1D) and 4 (2D) met after three SMO cycles (fetch-tool summary); High-NA DUV Immersion Scanner page of this vault.

Ques: Why is SADP preferred over LELE, and is LELE overlay still a problem?

Because spacers align adjacent lines automatically. Abercrombie explains that LELE lines come from two masks that misalign, while SADP lines come from one spacer process; ECE 695 L11 adds that LELE halves throughput and needs two masks per layer. Ban et al. quote overlay below 3 for SADP but above 6 for LELE in 2011, whereas ASML now specifies 2.5 on-product overlay (High-NA DUV Immersion Scanner page). The 6 figure therefore reflects older scanners, and modern overlay makes LELE viable for some layers; but since a space between lines from different masks moves one-for-one with overlay, SADP remains the safer choice for tight gratings (my reading). SADP’s own weak point is spacer etch bias (Abercrombie). Reference: D. Abercrombie (Siemens EDA), ‘Self-Aligned Double Patterning, Part One’, Semiconductor Engineering, 15 May 2014: SID-type SADP with mandrel mask, spacer deposition and etch, mandrel removal, block mask, inherent alignment of adjacent lines against LELE misalignment, spacer etch bias as the main process challenge (fetch-tool summary); ECE 695 Nanometer Scale Patterning and Processing, Lecture 11, RETs continued, Spring 2016, nanoHUB resource 24318: LFLE and LELE flows, CD variation from overlay between the two masks, SADP with low-temperature oxide CVD and spacer etch giving accurate CD and relaxed second-mask overlay, pitch splitting, k1 practical limit 0.25 for single processing and below 0.2 with double processing, two masks per layer, throughput halved, immersion system above 50 million dollars (fetch-tool summary); Y. Ban, K. Lucas and D. Z. Pan, ‘Flexible 2D Layout Decomposition Framework for Spacer-Type Double Pattering Lithography’, DAC 2011: core and trim masks, single spacer width forming either wire width or space, SADP overlay below 3 nm against above 6 nm for LELE, spacer deposition the most critical control, no stitches, 22 nm cells with 34 nm width, space and spacer, 8 nm etch bias per edge, 50 nm core width, 5 nm trim overlay margin (fetch-tool summary); High-NA DUV Immersion Scanner page of this vault.

Ques: What is SAQP pitch walk and how sensitive is it?

Unequal spaces in a quadrupled grating. More and Hegde define it as the spread between three spaces: , and , with a 7.5 specification and spacer thicknesses of 28 and 20 , each plus or minus 1.3 . Starting from a balanced grating, a 1.3 thicker first spacer raises by 1.3 and lowers by 2.6 , a 3.9 pitch walk, 52 per cent of the specification (computed), because carries twice each spacer. They show that pitch walk combined with line-edge roughness causes line bridges. The SPIE 10587 abstract calls pitch walk part of the EPE budget and argues that dose and etch must be co-optimized to control it. Reference: S. K. More and R. Hegde (Semiverse Solutions, Lam Research), ‘Unraveling DRAM SAQP Process Complexity With Monte Carlo Virtual Fabrication’, Semiconductor Engineering, 16 April 2026: mandrel plus two spacer cycles giving four lines per mandrel, 60 nm print CD for 15 nm lines and trenches, pitch walk = max - min of alpha = T1, beta = mandrel CD - 2T2, gamma = mandrel pitch - mandrel CD - 2T1 - 2T2, 7.5 nm specification, spacer1 28 +/- 1.3 nm, spacer2 20 +/- 1.3 nm, LER with pitch walk causing line bridges, best Monte Carlo success 83.89 per cent (fetch-tool summary); ‘Co-optimization of exposure dose and etch process for SAQP pitch walk control’, Proc. SPIE 10587 (2018), ADS abstract (authors not shown): pitch walk as a repeating non-uniform grating of space and line CDs from different space populations, dose correction harder for SAQP than SADP, litho-etch co-optimization required, pitch walk part of the EPE budget, 32 nm pitch grating (fetch-tool summary).

Ques: How far does multiple patterning push k1, and what does it cost?

Below 0.2, at a price in steps and wafers. ECE 695 L11 states that the practical single-exposure limit is = 0.25 and that double processing brings it below 0.2. Splitting 76 mask pitches into a 38 grating gives a 19 half pitch, = 0.133 at NA 1.35 (computed). The same lecture lists the costs: two masks per critical layer, throughput halved, an extra etch, and immersion tools above 50 million dollars. Ban et al. note that SADP needs core and trim masks, a single spacer width and no stitching, with a 34 spacer and 8 etch bias per edge giving a 50 core (computed check). Each extra step adds CD and overlay populations to measure (Overlay Metrology Tool page; my reading). Reference: ECE 695 Nanometer Scale Patterning and Processing, Lecture 11, RETs continued, Spring 2016, nanoHUB resource 24318: LFLE and LELE flows, CD variation from overlay between the two masks, SADP with low-temperature oxide CVD and spacer etch giving accurate CD and relaxed second-mask overlay, pitch splitting, k1 practical limit 0.25 for single processing and below 0.2 with double processing, two masks per layer, throughput halved, immersion system above 50 million dollars (fetch-tool summary); Y. Ban, K. Lucas and D. Z. Pan, ‘Flexible 2D Layout Decomposition Framework for Spacer-Type Double Pattering Lithography’, DAC 2011: core and trim masks, single spacer width forming either wire width or space, SADP overlay below 3 nm against above 6 nm for LELE, spacer deposition the most critical control, no stitches, 22 nm cells with 34 nm width, space and spacer, 8 nm etch bias per edge, 50 nm core width, 5 nm trim overlay margin (fetch-tool summary); Overlay Metrology Tool page of this vault.

References

  1. ECE 695 Nanometer Scale Patterning and Processing, Lecture 10, “Optical Lithography - Resolution Enhancement Techniques (RETs) in Optical Projection Lithography,” Spring 2016, nanoHUB resource 24508. Available: https://nanohub.org/resources/24508/download/2016.02.01-ECE695Q-L10.pdf
  2. ECE 695 Nanometer Scale Patterning and Processing, Lecture 11, RETs continued, Spring 2016, nanoHUB resource 24318. Available: https://nanohub.org/resources/24318/download/2016.02.05-ECE695Q-L11.pdf
  3. D. Abercrombie, “Self-aligned double patterning, part one,” Semiconductor Engineering, 15 May 2014. Available: https://semiengineering.com/self-aligned-double-patterning-part-one/
  4. Y. Ban, K. Lucas and D. Z. Pan, “Flexible 2D layout decomposition framework for spacer-type double pattering lithography,” Proc. 48th Design Automation Conference, pp. 789-794, 2011. Available: https://www.cerc.utexas.edu/utda/publications/C117.pdf
  5. S. K. More and R. Hegde, “Unraveling DRAM SAQP process complexity with Monte Carlo virtual fabrication,” Semiconductor Engineering, 16 April 2026. Available: https://semiengineering.com/unraveling-dram-saqp-process-complexity-with-monte-carlo-virtual-fabrication/
  6. “Co-optimization of exposure dose and etch process for SAQP pitch walk control,” Proc. SPIE 10587, Optical Microlithography XXXI, 2018, ADS abstract. Available: https://ui.adsabs.harvard.edu/abs/2018SPIE10587E..04M/abstract
  7. G. Chen, H. Yang, H. Ren, B. Yu and D. Z. Pan, “Differentiable edge-based OPC,” arXiv:2408.08969. Available: https://arxiv.org/html/2408.08969v3
  8. Preprints.org manuscript 202509.0754, source-mask optimization study, version 1. Available: https://www.preprints.org/manuscript/202509.0754/v1
  9. High-NA DUV Immersion Scanner page of this vault.
  10. Photoresist and Process Window page of this vault.
  11. Overlay Metrology Tool page of this vault.

Related pages in this vault: High-NA DUV Immersion Scanner, Photoresist and Process Window, Overlay Metrology Tool, CD-SEM, Optical CD Scatterometer (OCD), Yield Models and Critical Area, Contact and Proximity Mask Aligner, EUV Scanner, Electron-Beam Lithography Writer.