1. Theory
- Definition: A backgrinding tool thins a finished wafer from the back, face down on a porous chuck under protective tape, with a rotating diamond cup wheel feeding axially into the rotating wafer (Liu et al.; Combs).
- Two-step grinding: A coarse wheel removes most of the excess and a fine wheel sets the final thickness and surface (Combs; DISCO).
- Damage: Grinding leaves a cracked layer about two to three times the peak roughness deep, which weakens the die (Ohta et al.).
- Stress relief: Dry polish, CMP or etching removes the damaged layer and restores strength (DISCO; Intel patent).
2. Working Principle
- Mount: Place the wafer device side down on protective tape and hold it by vacuum through the chuck (Strasbaugh patent).
- Grind: Coarse grind at up to a few micrometres per second, then fine grind with a #2000 or finer wheel (Intel patent; DISCO).
- Relieve: Remove about 2 to 25 by dry polish, CMP or isotropic etch (DISCO; Intel patent).
- Measure and dice: Check thickness and TTV, then dice, or use dicing before grinding (Liu et al.; DISCO).
3. Applications
- Thin memory dies: Memory chips below 100 , and 30 or less in some cases (DISCO).
- Advanced thinning: Wafers thinned from about 780 to below 10 with TTV below 1 (Liu et al.).
- Standard packages: About 0.76 mm sawn wafers ground to about 0.36 mm, and to about 0.20 mm for thin parts (Strasbaugh patent).
- Compound semiconductors: 100 mm GaAs wafers thinned to 250 (Combs).
Grinding Process
| Name | Formula | Related Formulae | Variables/Constants |
|---|---|---|---|
| Thinning plan | |||
| Grinding rate and time | |||
| Wheel contact geometry |
Damage and Stress Relief
| Name | Formula | Related Formulae | Variables/Constants |
|---|---|---|---|
| Subsurface damage from roughness | |||
| Stress-relief removal | |||
| Surface roughness after each step |
Strength and Flatness
| Name | Formula | Related Formulae | Variables/Constants |
|---|---|---|---|
| Three-point bending strength | |||
| Thickness variation from spindle tilt | |||
| Dicing order |
Important Questions
Ques: How is a wafer thinned from 720 to 150 micrometres?
In two grinding steps. Combs notes that a coarse wheel removes about 90 per cent of the excess and a finer wheel sets the final thickness, so going from 720 to 150 means about 513 coarse and 57 fine (computed). Intel’s patent grinds at 0.1 to 5.0 with the chuck at 200 to 300 , so 570 takes from about 2 minutes to 95 minutes depending on rate (computed). Finer grit leaves stronger dies: Combs reports 2000-grit dies needing about 50 per cent more stress to break than 1200-grit dies. A Strasbaugh patent gives typical post-grind thicknesses of about 0.36 mm and 0.20 mm for thin parts, and memory dies go below 100 and sometimes 30 or less (DISCO), where stress relief and dicing order become critical. Reference: E. G. Combs, ‘The back-end process: Step 3 - Wafer backgrinding’, Solid State Technology / Semiconductor Digest (about 2002) (fetch-tool summary); M. Dydyk, A. Urquiza, C. Singleton and T. McIntosh, ‘Wafer backside grinding with stress relief’, US patent 8,222,118 B2, Intel (filed December 2008) (fetch-tool summary); A. Strasbaugh and S. M. Kassir, ‘Method of backgrinding wafers while leaving backgrinding tape on a chuck’, US patent 7,059,942 B2, Strasbaugh (priority September 2000) (fetch-tool summary); DISCO Corporation, Sales Engineering Department, ‘Silicon wafer thinning, the singulation process, and die strength’, DISCO Technical Review TR16-03 (February 2016) (fetch-tool summary).
Ques: How much material must stress relief remove after grinding?
The sources differ. DISCO removes about 2 by CMP or dry polish after a #2000 wheel, while Intel’s patent removes 3 to 25 by isotropic etch after rough grinding with grits from 200 to 2000. Ohta et al. show that damage depth is about 2.3 times the peak roughness for silicon, about 1.6 to 2.0 at 10 grit and 5.6 to 7.4 at 20 grit (computed). The two figures are consistent once the last grinding step is considered: DISCO’s 2 follows a fine #2000 wheel, while Intel’s 3 to 25 follows rough grinding with grits as coarse as 200, and Ohta shows damage growing with grit size (my reading). For a fine-ground wafer, DISCO’s 2 is the more likely requirement. Intel reports 50 to 100 per cent strength recovery. Reference: DISCO Corporation, Sales Engineering Department, ‘Silicon wafer thinning, the singulation process, and die strength’, DISCO Technical Review TR16-03 (February 2016) (fetch-tool summary); M. Dydyk, A. Urquiza, C. Singleton and T. McIntosh, ‘Wafer backside grinding with stress relief’, US patent 8,222,118 B2, Intel (filed December 2008) (fetch-tool summary); T. Ohta, J. Yan, T. Kuriyagawa, S. Kodera and T. Nakasuji, ‘Prediction of subsurface damage depth of ground brittle materials by surface profiling’, Int. J. Machining and Machinability of Materials 2, 108 (2007) (fetch-tool summary).
Ques: How can subsurface damage be estimated without cross-sectioning?
From the surface roughness. Ohta et al. measured crack depth by small-tool and slanted polishing and fitted for silicon, about 2.3 times the peak roughness measured with a stylus, and 2.9 times for germanium; overall, crack depth was 2 to 3 times the roughness. The rule breaks down for the finest grits: slanted polishing gave about 10 times the roughness for 8 and 10 grits, against about 3 times for 20 and 149 . The ratio therefore depends on the method, and the small-tool result of about 2.3 is more likely reliable for routine estimates, since its repeatability was about 1 (my reading). A stylus profile is thus a quick inline damage check (my reading). Reference: T. Ohta, J. Yan, T. Kuriyagawa, S. Kodera and T. Nakasuji, ‘Prediction of subsurface damage depth of ground brittle materials by surface profiling’, Int. J. Machining and Machinability of Materials 2, 108 (2007) (fetch-tool summary).
Ques: How is die strength measured and why does thinning lower the breaking load?
By three-point bending to SEMI G86-0303: the die is simply supported, loaded by an indenter until it breaks, and the bending stress is (DISCO). The breaking load falls with the square of thickness, so for an assumed 1 N load, 4 span and 5 width, the stress is 480 at 50 but only 30 at 200 (computed). A thin die therefore breaks at a small load even if its material strength is unchanged. DISCO found that dies ground with a #2000 wheel were 2.3 times stronger when the saw marks ran at 90 degrees to the indenter than at 0 degrees. CMP or dry polish removed this direction dependence, and dicing before grinding helped only on dry-polished surfaces. Reference: DISCO Corporation, Sales Engineering Department, ‘Silicon wafer thinning, the singulation process, and die strength’, DISCO Technical Review TR16-03 (February 2016) (fetch-tool summary).
Ques: What controls total thickness variation in backgrinding?
Mainly the tilt between the wheel spindle and the chuck. Liu et al. model the ground surface as the wheel arc swept around the chuck axis, with contact half-angle , 30 degrees for an assumed 300 wafer and wheel (computed). A tilt of 0.018 degrees in one direction creates a 46.9 centre-to-edge difference, which matches = 47.1 (computed), while the other tilt direction mainly changes the shape by less than 1 . Since the target TTV is below 1 for wafers thinned from about 780 to below 10 , the spindle angle must be set to a few ten-thousandths of a degree (my reading). Reference: Y. Liu, H. Tao, D. Zhao and X. Lu, ‘An Investigation on the Total Thickness Variation Control and Optimization in the Wafer Backside Grinding Process’, Materials 15, 4230 (2022) (fetch-tool summary).
References
- E. G. Combs, “The back-end process: Step 3 - Wafer backgrinding,” Solid State Technology. Available: https://sst.semiconductor-digest.com/?p=36289
- M. Dydyk, A. Urquiza, C. Singleton and T. McIntosh, “Wafer backside grinding with stress relief,” US Patent 8,222,118 B2, Intel Corp., 2012. Available: https://patents.google.com/patent/US8222118
- DISCO Corporation, “Silicon wafer thinning, the singulation process, and die strength,” Technical Review TR16-03, 2016. Available: https://www-hq.disco.co.jp/eg/solution/technical_review/doc/TR16-03_Silicon%20wafer%20thinning,%20the%20singulation%20process,%20and%20die%20strength_20160610.pdf
- T. Ohta, J. Yan, T. Kuriyagawa, S. Kodera and T. Nakasuji, “Prediction of subsurface damage depth of ground brittle materials by surface profiling,” Int. J. Machining and Machinability of Materials, vol. 2, no. 1, pp. 108-124, 2007. Available: https://www.yan.mech.keio.ac.jp/wp-content/uploads/2024/09/10Prediction-of-subsurface-damage-depth-of-ground-brittle-materials-by-surface-profiling.pdf
- A. Strasbaugh and S. M. Kassir, “Method of backgrinding wafers while leaving backgrinding tape on a chuck,” US Patent 7,059,942 B2, Strasbaugh, 2006. Available: https://patents.google.com/patent/US7059942
- Y. Liu, H. Tao, D. Zhao and X. Lu, “An Investigation on the Total Thickness Variation Control and Optimization in the Wafer Backside Grinding Process,” Materials, vol. 15, 4230, 2022. Available: https://www.mdpi.com/1996-1944/15/12/4230/html
Related pages in this vault: CMP Polisher, Wafer Geometry Gauge, Stylus Profiler, Wafer Curvature Stress Gauge, Mechanical and Package Stress, Chip-to-Package Interconnects.