1. Theory

Definition: Chip-to-package interconnects carry signals and power between a die and its package, interposer or a stacked die: bond wires, solder (C4) bumps, copper pillars and microbumps, and bumpless Cu-Cu hybrid bonds, in order of falling pitch (LaPedus; Lau).
Pitch and density: The number of connections per area scales as $1/ p^{2}$ , from about 44 $m m^{- 2}$ at 150 $μ m$ pitch through 400 at 50 $μ m$ to 10,000 at 10 $μ m$ (computed; Lau).
Parasitics: A bond wire has about 0.5 to 1 $nH$ per mm, while a microbump has milliohms and femtofarads and an inductance small enough to neglect (RF Essentials; Ehrett et al.).
Energy: The energy per bit of a short vertical link scales with its capacitance, about 0.1 to 2 $fJ/bit$ for microbumps, and hybrid bonding gives about 3 times better energy efficiency than microbumps in AMD’s figures (Ehrett et al.; LaPedus).
Migration path: Below about 40 $μ m$ pitch the industry moves from solder microbumps to copper pillars and to hybrid bonding at 10 $μ m$ and below (LaPedus).

2. Working Principle

Bond wires: A thin gold or copper wire arcs from the die pad to the package lead, and its length and small radius give it a large self-inductance that dominates at GHz frequencies (RF Essentials).
Flip-chip bumps: Solder or copper-pillar bumps on the face of the die are reflowed or thermocompression-bonded to the substrate, giving short vertical paths and an area array of connections (LaPedus).
Hybrid bonding: Flat dielectric surfaces with slightly recessed Cu pads bond at room temperature, and an anneal expands the copper to close the recess and form Cu-Cu bonds without solder (Lau).
Signalling over short links: Because a microbump or hybrid bond is far shorter than a wavelength, it behaves as a small lumped capacitance that the driver charges each transition (Ehrett et al.; background knowledge).

3. Applications

Wire-bonded packages: Most packages, about 75 to 80 per cent by TechSearch’s count quoted by LaPedus, especially low-cost and low-pin-count parts (LaPedus).
Flip-chip processors and GPUs: Area-array C4 and copper-pillar bumps for high pin counts and power delivery; on the Power Delivery Networks page (LaPedus).
HBM and 2.5D integration: Microbumps at about 40 $μ m$ pitch for memory stacks and interposers (LaPedus; Ehrett et al.).
3D stacking: Hybrid bonding in image sensors, stacked SRAM cache and logic-on-logic such as Foveros Direct (Lau; LaPedus).

Bond Wires

Name	Formula	Related Formulae	Variables/Constants
Bond-wire inductance	$L \approx \frac{μ _{0} l}{2 π} [ln (\frac{2 l}{r}) - 1] \Rightarrow L [nH] \approx 0.2 l [ln (\frac{2 l}{r}) - 1] (l, r in mm)$	$X_{L} = 2 π f L, L \approx 0.5 to 1.0 nH/mm$	$L : se l f - in d u c t an ce o f a s t r ai g h t r o u n d w i r e$ $μ_{0} : p er m e abi l i t y o f f r ee s p a ce$ $l : l e n g t h$ $r : r a d i u s$ $X_{L} : r e a c t an ce a t f r e q u e n cy f; R F E sse n t ia l s : 0.5 t o 1.0 n H p er mm f or a s in g l e w i r e, ab o u t 0.7 nH f or 1 mm o f 25 μ m g o l d w i r e, ab o u t 63 Ω p er n H a t 10 GHz, t r an s mi ss i o n - l in e e f f ec t s ab o v e 20 GHz, an d a l e n g t h v a r ia t i o n o f pl u s or min u s 100 μ m s hi f t in g t h e ma t c h; t h e l o w - f r e q u e n cy f or m w i t h - 3/4 in s t e a d o f - 1 in c l u d es t h e in t er na l in d u c t an ce (ba c k g r o u n d k n o w l e d g e)$ $(co m p u t e d : 1 mm o f 25 μ m w i r e g i v es 0.82 nH w i t h - 1 an d 0.87 nH w i t h - 3/4, a g ain s t t h e q u o t e d 0.7 nH (see t h e Q / A); 0.7 nH i s 44 Ω a t 10 GHz)$
Parallel bond wires and ribbons	$L_{n} = \frac{L + ( n - 1 ) M}{n}$	$\frac{Δ L}{L} = 1 - \frac{L _{n}}{L}$	$L_{n} : in d u c t an ce o f n p a r a l l e l w i r es$ $L : s in g l e - w i r e in d u c t an ce$ $M : m u t u a l in d u c t an ce b e tw ee n w i r es (e q u a l m u t u a l co u pl in g a ss u m e d, ba c k g r o u n d k n o w l e d g e); R F E sse n t ia l s (1 mm) : s in g l e w i r e 0.7 nH, tw o w i r es 100 μ m a p a r t 0.4 nH, f o u r w i r es 0.25 nH an d a 250 μ m r ibb o n 0.3 nH, w i t h t h e t e x t q u o t in g ab o u t 60 p er ce n t r e d u c t i o n f or tw o w i r es$ $(co m p u t e d : t h e t ab l e g i v es r e d u c t i o n s o f 43, 64 an d 57 p er ce n t, so t h e 60 p er ce n t q u o t e d f or tw o w i r es d oes n o t ma t c h (see t h e Q / A); 0.4 nH f or tw o w i r es im pl i es M o f ab o u t 0.1 nH)$

Bumps and Microbumps

Name	Formula	Related Formulae	Variables/Constants
Bump pitch and interconnect density	$N_{A} = \frac{1}{p ^{2}} (square array)$	$\frac{N _{A, 1}}{N _{A, 2}} = (\frac{p _{2}}{p _{1}})^{2}$	$N_{A} : co nn ec t i o n s p er u ni t a r e a$ $p : p i t c h; L a P e d u s (2021) : f l i p - c hi p p i t c h es f r o m 300 t o 50 μ m w i t h main s t r e am co a r se p i t c h es o f 140 t o 150 μ m an d e m er g in g 110 t o 120 μ m, so l d er ba l l s o f 75 t o 200 μ m, t h e m os t a d v an ce d mi cr o b u m p s a t 40 μ m p i t c h w i t h ab o u t 25 μ m b u m p s an d 15 μ m s p a c in g (20 t o 25 μ m in t h e seco n d a r t i c l e), H B M s t a c k in g a t 40 μ m, I n t e l^{'} s 3 D C P U pl a t f or m a t 36 μ m, A mk or a t 35 μ m f r o m 2022, co pp er p i l l a r s a t 18 μ m p i t c h (9 μ m d iam e t er, 20 μ m h e i g h t) an d 10 μ m p i t c h (5 μ m, 10 μ m), ab o u t 200 an d 500 mi l l i o n b u m p s p er 300 mm w a f er a t 18 an d 10 μ m, an d mi cr o b u m p s v iab l e d o w n t o ab o u t 10 t o 20 μ m; L a u : 400 mi cr o b u m p s p er s q u a r e mm a t 50 μ m a g ain s t 10, 000 h y b r i d - b o n d p a d s p er s q u a r e mm a t 10 μ m f or I n t e l F o v er os D i r ec t$ $(co m p u t e d : 150, 50, 40, 10 an d 4 μ m p i t c h g i v e 44, 400, 625, 10, 000 an d 62, 500 m m^{- 2}, ma t c hin g L a u^{'} s 400 an d 10, 000)$
Resistance, capacitance and energy of a microbump	$R_{b} = \frac{ρ H}{π ( D /2 ) ^{2}}, E_{bi t} \approx α C_{b} V^{2}$	$1 μ W/Gbps = 1 fJ/bit$	$R_{b} : b u m p r es i s t an ce$ $ρ : b u m p r es i s t i v i t y$ $H : h e i g h t$ $D : d iam e t er$ $E_{bi t} : e n er g y p er bi t$ $α : a c t i v i t y an d s w in g f a c t or$ $C_{b} : b u m p c a p a c i t an ce$ $V : s i g na l s w in g (f or m s, ba c k g r o u n d k n o w l e d g e); E h r e tt e t a l . (or d er - o f - ma g ni t u d e es t ima t es) : b u m p s o f 5 μ m d iam e t er, 10 μ m h e i g h t an d 50 μ m p i t c h w i t h 40 mΩ, 0.4 fF an d 0.13 μ W/Gbps; 10 b y 10 μ m a t 20 μ m p i t c h w i t h 10 mΩ, 2 fF an d 0.64 μ W/Gbps; G e n 1 H B M - s t y l e 25 b y 35 μ m a t 55 μ m p i t c h w i t h 5.6 mΩ, 6.36 fF an d 2.04 μ W/Gbps; in d u c t an ce n e g l ec t e d; T S V s o f t e n 5 t o 10 t im es l o n g er t han mi cr o b u m p s, w i t h u p t o tw o or d er s o f ma g ni t u d e m or e d e l a y$ $(co m p u t e d : a l l t h r ee c a ses im pl y t h e s am e r es i s t i v i t y, 7.9 μ Ω cm, c l ose t o C u 3 S n (ba c k g r o u n d k n o w l e d g e f or t ha t v a l u e); a l l t h r ee g i v e ab o u t 0.32 fJ/bit p er fF, co n s i s t e n t w i t h \frac{1}{2} C V^{2} a t ab o u t 0.8 V; t h e e n er g i es a r e 0.13 t o 2.04 fJ/bit)$

Hybrid Bonding

Name	Formula	Related Formulae	Variables/Constants
Hybrid bonding	$N_{A} = \frac{1}{p ^{2}}, \frac{N _{A, H B}}{N _{A, μ b}} = (\frac{p _{μ b}}{p _{H B}})^{2}$	$bond at room temperature, then anneal at 150 to 300^{\circ} C$	$N_{A, H B}, N_{A, μ b} : d e n s i t y o f h y b r i d b o n d s an d mi cr o b u m p s$ $p_{H B}, p_{μ b} : t h e i r p i t c h es; L a u : h y b r i d b o n d in g d o w n t o 4 μ m p i t c h (D B I d e m o n s t r a t i o n w i t h 2 μ m p a d s), d i e l ec t r i c r o ug hn ess o f ab o u t 0.5 nm R M S or l ess an d C u r ecess o f ab o u t 3 nm, r oo m - t e m p er a t u r e co n t a c t f o l l o w e d b y ann e a l s a t 150 t o 300^{\circ} C (S o n y p r ocess a t 300^{\circ} C, 25 kN, 30 min, t h e n 60 min), S o n y^{'} s I M X 260 ima g e se n sor in hi g h - v o l u m e p r o d u c t i o n f r o m 2016, an d A M D^{'} s 3 D V - C a c h e p r o t o t y p e r ai s in g L 3 f r o m 32 t o 96 M B; L a P e d u s : h y b r i d b o n d in g a t 10 μ m an d b e l o w, A * S T A R a t 12 μ m, L e t i t o w a r d 5 μ m, pl a ce m e n t a cc u r a cy b e tt er t han 1 μ m t a r g e t e d, an d A M D q u o t in g 15 t im es t h e in t er co nn ec t d e n s i t y an d 3 t im es t h e e n er g y e f f i c i e n cy o f mi cr o b u m p s, w i t h o v er 2 T B / s f or V - C a c h e$ $(co m p u t e d : 36 μ m mi cr o b u m p s a g ain s t an a ss u m e d 9 μ m h y b r i d - b o n d p i t c h g i v e 16 t im es t h e d e n s i t y, c l ose t o A M D^{'} s 15 t im es)$

Important Questions

Ques: Is a 1 mm, 25 micrometre bond wire about 0.7 nH or about 0.8 nH?

RF Essentials quotes about 0.7 $nH$ , but its own practical formula, $0.2 l [ln (2 l / r) - 1]$ in nanohenries with lengths in millimetres, gives 0.82 $nH$ for 1 $mm$ and a 12.5 $μ m$ radius, and the low-frequency form with $- 3/4$ gives 0.87 $nH$ (computed). The formula assumes a straight, isolated wire far from any return path, while a real bond wire arcs over the die and package and has a nearby ground, whose return current lowers the loop inductance (background knowledge). The quoted 0.7 $nH$ therefore probably reflects a typical mounted wire, and 0.8 $nH$ the isolated straight-wire value (my reading). For design, the 0.7 $nH$ figure is the more realistic one, but the actual loop with its return path should be simulated. Either way, at 10 $GHz$ the wire adds about 44 to 52 $Ω$ of reactance (computed). Reference: RF Essentials, ‘Bond Wire Inductance’, RF glossary entry (fetch-tool summary).

Ques: Do two parallel bond wires cut the inductance by about 43 or about 60 per cent?

RF Essentials gives both: its table lists 0.7 $nH$ for one 1 $mm$ wire and 0.4 $nH$ for two wires 100 $μ m$ apart, a 43 per cent reduction (computed), while its text says about 60 per cent. Two wires with no mutual coupling would halve the inductance, a 50 per cent reduction, and mutual inductance between closely spaced wires always makes the reduction smaller than that (background knowledge), so a 60 per cent reduction for two wires is not physically possible with equal wires. The table value of 43 per cent is therefore the more likely one, implying a mutual inductance of about 0.1 $nH$ (computed). The text’s 60 per cent is close to the table’s 64 per cent for four wires and may refer to that case (my reading). A 250 $μ m$ ribbon gives 0.3 $nH$ , a 57 per cent reduction (computed). Reference: RF Essentials, ‘Bond Wire Inductance’, RF glossary entry (fetch-tool summary).

Ques: How much denser is hybrid bonding than microbumps?

Density scales with the inverse square of pitch, so it rises quickly as pitch falls. Lau gives 400 microbumps per square millimetre at 50 $μ m$ pitch against 10,000 hybrid-bond pads per square millimetre at the 10 $μ m$ pitch of Intel’s Foveros Direct, 25 times more, both following $1/ p^{2}$ exactly (computed). LaPedus quotes AMD’s figure of 15 times the interconnect density of microbumps for its 3D V-Cache, consistent with 36 $μ m$ bumps against an assumed 9 $μ m$ hybrid-bond pitch, which gives 16 times (computed). Hybrid bonding has been demonstrated at 4 $μ m$ with 2 $μ m$ pads, about 62,500 per square millimetre (computed), while microbumps are viable only down to about 10 to 20 $μ m$ according to LaPedus, because solder bridging and placement accuracy limit them. Reference: J. H. Lau, ‘State-of-the-Art and Outlooks of Chiplets Heterogeneous Integration and Hybrid Bonding’, Journal of Microelectronics and Electronic Packaging 18(4), 145-160 (2021) (fetch-tool summary); M. LaPedus, ‘Bumps vs. Hybrid Bonding for Advanced Packaging’, Semiconductor Engineering (23 June 2021) (fetch-tool summary).

Ques: How much energy does it take to send a bit through a microbump?

Very little, because a microbump is a tiny capacitor. Ehrett et al. estimate 0.13 $μ W/Gbps$ , that is 0.13 $fJ/bit$ , for a 5 $μ m$ wide, 10 $μ m$ tall bump of 0.4 $fF$ , rising to 0.64 and 2.04 $fJ/bit$ for 10 $μ m$ and HBM-style 25 by 35 $μ m$ bumps of 2 and 6.36 $fF$ . All three give about 0.32 $fJ/bit$ per femtofarad, consistent with $\frac{1}{2} C V^{2}$ at about 0.8 $V$ (computed). Their resistances, 40, 10 and 5.6 $mΩ$ , all imply about 7.9 $μ Ω cm$ for the bump metal (computed). The bump itself is therefore a negligible part of the link energy, which is dominated by the drivers, ESD protection and wiring on each die (background knowledge). Ehrett et al. note that TSVs are often 5 to 10 times longer than microbumps, with far larger delay and power. Reference: P. Ehrett, V. Goyal, O. Matthews, R. Das, T. Austin and V. Bertacco, ‘Analysis of Microbump Overheads for 2.5D Disintegrated Design’, University of Michigan Technical Report CSE-TR-002-17 (2017) (fetch-tool summary); Through-Silicon Vias as Passives page of this vault.

Ques: What makes hybrid bonding demanding to manufacture?

The surfaces must be almost perfectly flat and clean. Lau describes direct bond interconnect with a dielectric roughness of about 0.5 $nm$ RMS or less and copper pads recessed by about 3 $nm$ , bonded at room temperature and then annealed at 150 to 300 $^{\circ} C$ , so that the copper expands to close the recess and form the metal bond. Sony’s process, used in high volume since its IMX260 image sensor of 2016, anneals at 300 $^{\circ} C$ under 25 $kN$ for 30 minutes and again for 60 minutes. Chip-to-wafer bonding also needs high-accuracy placement: LaPedus cites Besi’s target of better than 1 $μ m$ , and Lau notes that slightly larger pads are used to tolerate placement errors. Particles and any warpage prevent the dielectric surfaces from bonding, so yield depends on cleanliness and wafer flatness (background knowledge). Reference: J. H. Lau, ‘State-of-the-Art and Outlooks of Chiplets Heterogeneous Integration and Hybrid Bonding’, Journal of Microelectronics and Electronic Packaging 18(4), 145-160 (2021) (fetch-tool summary); M. LaPedus, ‘Bumps vs. Hybrid Bonding for Advanced Packaging’, Semiconductor Engineering (23 June 2021) (fetch-tool summary).

Ques: Why do high-frequency and high-current chips avoid bond wires?

Because a bond wire’s inductance is large compared with what fast signals and power delivery can tolerate. At about 0.7 $nH$ per mm, a 1 $mm$ wire has about 44 $Ω$ of reactance at 10 $GHz$ (computed), comparable to a 50 $Ω$ line, and RF Essentials notes transmission-line effects above 20 $GHz$ and match shifts from length variations of plus or minus 100 $μ m$ . For power, a supply current change of 1 A per ns across 0.7 $nH$ would drop 0.7 $V$ (computed), far beyond the milliohm target impedances on the Power Delivery Networks page. Flip-chip bumps, spread over the whole die area at 40 to 150 $μ m$ pitch, provide many short paths in parallel, while about 75 to 80 per cent of packages still use wire bonding for its low cost (LaPedus). Reference: RF Essentials, ‘Bond Wire Inductance’, RF glossary entry (fetch-tool summary); M. LaPedus, ‘Bumps vs. Hybrid Bonding for Advanced Packaging’, Semiconductor Engineering (23 June 2021) (fetch-tool summary); Power Delivery Networks page of this vault.

Quartz 5

Explorer

Chip-to-Package Interconnects