1. Theory

  • Definition: A Bosch DRIE tool etches deep silicon structures by alternating an SF etch step with a CF passivation step in an ICP reactor (Alberta; Ayon et al.; Purdue).
  • Mechanism: Passivation coats all surfaces with a Teflon-like polymer; in the etch step, ions clear it from the floor and SF etches silicon isotropically, leaving the sidewalls protected (Alberta).
  • Scallops: Each isotropic step leaves a scallop; shorter etch steps make them smaller, down to 50 nm (Ayon et al.).
  • ARDE: Narrow features etch more slowly than wide ones, though gas flow can reduce the effect (Alberta; Ayon et al.).

2. Working Principle

  • Cycle: About 10 s CF and 15 s SF, 25 to 75 sccm each, at about 30 mTorr and 450 W ICP, removing 0.5 to 1 m per cycle (Alberta).
  • Bias: Below 100 V for passivation and above 100 V for etching (Alberta).
  • Rate: 0.5 to 2 m/min (Alberta) to above 4 m/min (Ayon et al.).
  • Masks: Resist for under 30 m, 0.6 m oxide for over 200 m, 0.2 m Cr for over 300 m (Alberta).

3. Applications

  • MEMS: Deep trenches, walls and through-wafer structures with aspect ratios of 20 to 60 (Alberta; Ayon et al.).
  • SOI devices: Etching to the buried oxide with footing control (Ayon et al.).
  • Alternative to KOH: Vertical walls in any orientation, unlike the 54.74 degree walls of the Wet Etch Bench page (my reading).

Bosch Cycle and Rate

NameFormulaRelated FormulaeVariables/Constants
Bosch cycle
Bias by step
Etch rate

Profile, Aspect Ratio and Mask

NameFormulaRelated FormulaeVariables/Constants
Scallops and profile
Aspect ratio achieved
Mask budget

ARDE, Loading and Buried Layers

NameFormulaRelated FormulaeVariables/Constants
ARDE (RIE lag)
Loading
Buried-layer effects

Important Questions

Ques: How does the Bosch process etch vertical walls with an isotropic chemistry?

By protecting the sidewalls between short etch steps. The Alberta primer describes a CF step of about 10 s that coats every surface with a Teflon-like polymer, and an SF step of about 15 s that first removes polymer from the trench floor, then etches silicon isotropically. Bias is kept well below 100 during deposition and above 100 during etching, so ions strip polymer only where they strike the floor (Alberta; my reading). Each cycle removes 0.5 to 1 , which is 1.2 to 2.4 (computed). Purdue confirms CF as the polymer source. Sidewalls end up scalloped at 85 to 92 degrees (Alberta), not the 54.74 degrees of KOH on the Wet Etch Bench page, and the reactor is an ICP as on the Inductively Coupled Plasma Etcher (ICP-RIE) page. Reference: University of Alberta NanoFab, ‘A deep silicon RIE primer: Bosch etching of deep structures in silicon’ (April 2009): C4F8 passivation of about 10 s depositing a Teflon-like polymer and SF6 etch of about 15 s removing bottom polymer then etching silicon isotropically, flows 25 to 75 sccm (typically 50), minimum pressure about 30 mTorr, ICP 450 W, bias well below 100 V during deposition and above 100 V during etch, 0.5 to 1 um per cycle, 0.5 to 2.0 um/min, resist enough below 30 um, 0.6 um thermal oxide for 200+ um, 0.2 um Cr for 300+ um, oxide eroded during C4F8 when ions present, scalloped sidewalls at 85 to 92 degrees, 100 um deep 5 um wide example, 2 um features etching much slower than 20 um ones as a fundamental effect handled only in mask design, bulls-eye non-uniformity above 20 to 30 per cent exposed silicon, pedestaling at buried layers from charging, cryo and black-silicon alternatives (fetch-tool summary); Purdue ECE 695Q, lectures 46 and 47 (nanoHUB, April 2016): C4F8 used for polymerization in deep RIE, Bosch process alternating passivation and etch, low pressure to reduce ion scattering and microloading (fetch-tool summary); Wet Etch Bench page of this vault; Inductively Coupled Plasma Etcher (ICP-RIE) page of this vault.

Ques: What etch rate does DRIE reach, and which figure is more likely?

Both are real; they describe different power levels. The Alberta primer gives 0.5 to 2.0 for its Oxford tool at 450 ICP, consistent with 0.5 to 1 per 25 s cycle (computed). Ayon et al. report above 4 , and an isotropic SF rate of up to 1380 , or 8.3 (computed), on a system with a 1000 coil and 300 electrode. They found that rate depends mainly on coil power, so the difference is expected from about twice the source power. The Alberta figure is more likely typical of a shared university tool, while the Ayon figure reflects a high-rate optimised process (my reading). Rate must always be quoted with coil power and open area (my reading). Reference: University of Alberta NanoFab, ‘A deep silicon RIE primer: Bosch etching of deep structures in silicon’ (April 2009): C4F8 passivation of about 10 s depositing a Teflon-like polymer and SF6 etch of about 15 s removing bottom polymer then etching silicon isotropically, flows 25 to 75 sccm (typically 50), minimum pressure about 30 mTorr, ICP 450 W, bias well below 100 V during deposition and above 100 V during etch, 0.5 to 1 um per cycle, 0.5 to 2.0 um/min, resist enough below 30 um, 0.6 um thermal oxide for 200+ um, 0.2 um Cr for 300+ um, oxide eroded during C4F8 when ions present, scalloped sidewalls at 85 to 92 degrees, 100 um deep 5 um wide example, 2 um features etching much slower than 20 um ones as a fundamental effect handled only in mask design, bulls-eye non-uniformity above 20 to 30 per cent exposed silicon, pedestaling at buried layers from charging, cryo and black-silicon alternatives (fetch-tool summary); A. A. Ayon, C. C. Lin, R. A. Braff, M. A. Schmidt, R. Bayt and H. H. Sawin (MIT), ‘Etching characteristics and profile control in a time multiplexed inductively coupled plasma etcher’, Solid-State Sensors, Actuators and Microsystems Workshop, Hilton Head (1998): 1000 W coil and 300 W electrode at 13.56 MHz, SF6 etch and C4F8 passivation, rate mainly set by coil power, more SF6 and electrode power helping, ARDE reduced by higher SF6 flow (140 sccm example) because fewer redepositing products form, 8.32 and 35.3 um trenches within 0.3 um depth and under 1 um variation, 4+ um/min and isotropic SF6 up to 1380 angstrom/s, more SF6 reducing anisotropy and roughening, 90 mTorr trip limit, shorter etch cycles reducing scallops to as low as 50 nm, under 4 per cent non-uniformity, low electrode power and higher pressure favouring resist selectivity, anisotropy rising with electrode power and first rising then falling with pressure, 12 um x 404 um and 1.85 um x 63.6 um trenches and a 0.8 um x 47.4 um wall, thicker passivation near buried oxide suppressing footing, SiF4 redeposition at low SF6 flow, diffusivity inverse to pressure (fetch-tool summary).

Ques: Is ARDE fundamental or controllable?

Partly both. The Alberta primer states that a 2 wide feature etches much slower than a 20 wide one, calls this a fundamental effect, and says it can only be handled in mask design. Ayon et al. found ARDE controllable: higher SF flow, 140 in their example, reduced it because fewer redepositing products form. Trenches of 8.32 and 35.3 then differed in depth by only 0.3 , with variation under 1 . In my reading, the two agree that narrow features lag. Ayon’s result shows that the lag can be made small over moderate widths with enough etchant flow. Alberta’s statement is more likely right for the smallest features, below Ayon’s 8 range. Reference: University of Alberta NanoFab, ‘A deep silicon RIE primer: Bosch etching of deep structures in silicon’ (April 2009): C4F8 passivation of about 10 s depositing a Teflon-like polymer and SF6 etch of about 15 s removing bottom polymer then etching silicon isotropically, flows 25 to 75 sccm (typically 50), minimum pressure about 30 mTorr, ICP 450 W, bias well below 100 V during deposition and above 100 V during etch, 0.5 to 1 um per cycle, 0.5 to 2.0 um/min, resist enough below 30 um, 0.6 um thermal oxide for 200+ um, 0.2 um Cr for 300+ um, oxide eroded during C4F8 when ions present, scalloped sidewalls at 85 to 92 degrees, 100 um deep 5 um wide example, 2 um features etching much slower than 20 um ones as a fundamental effect handled only in mask design, bulls-eye non-uniformity above 20 to 30 per cent exposed silicon, pedestaling at buried layers from charging, cryo and black-silicon alternatives (fetch-tool summary); A. A. Ayon, C. C. Lin, R. A. Braff, M. A. Schmidt, R. Bayt and H. H. Sawin (MIT), ‘Etching characteristics and profile control in a time multiplexed inductively coupled plasma etcher’, Solid-State Sensors, Actuators and Microsystems Workshop, Hilton Head (1998): 1000 W coil and 300 W electrode at 13.56 MHz, SF6 etch and C4F8 passivation, rate mainly set by coil power, more SF6 and electrode power helping, ARDE reduced by higher SF6 flow (140 sccm example) because fewer redepositing products form, 8.32 and 35.3 um trenches within 0.3 um depth and under 1 um variation, 4+ um/min and isotropic SF6 up to 1380 angstrom/s, more SF6 reducing anisotropy and roughening, 90 mTorr trip limit, shorter etch cycles reducing scallops to as low as 50 nm, under 4 per cent non-uniformity, low electrode power and higher pressure favouring resist selectivity, anisotropy rising with electrode power and first rising then falling with pressure, 12 um x 404 um and 1.85 um x 63.6 um trenches and a 0.8 um x 47.4 um wall, thicker passivation near buried oxide suppressing footing, SiF4 redeposition at low SF6 flow, diffusivity inverse to pressure (fetch-tool summary).

Ques: What sets the scallop size and sidewall profile?

The length of each etch step and the balance of etch and passivation. Ayon et al. report that shorter etch cycles reduce scalloping, to as little as 50 peak to valley, and that raising SF flow from 85 to 125 reduces anisotropy and roughens the surface. They also found that anisotropy rises with electrode power and, with pressure, first rises then falls as ion energy drops and ion angles spread, with a 90 trip limit. The Alberta primer gives sidewall angles of 85 to 92 degrees. In my reading, each scallop is the footprint of one isotropic SF step, so scallop depth scales with the per-cycle depth of 0.5 to 1 (Alberta). Reference: A. A. Ayon, C. C. Lin, R. A. Braff, M. A. Schmidt, R. Bayt and H. H. Sawin (MIT), ‘Etching characteristics and profile control in a time multiplexed inductively coupled plasma etcher’, Solid-State Sensors, Actuators and Microsystems Workshop, Hilton Head (1998): 1000 W coil and 300 W electrode at 13.56 MHz, SF6 etch and C4F8 passivation, rate mainly set by coil power, more SF6 and electrode power helping, ARDE reduced by higher SF6 flow (140 sccm example) because fewer redepositing products form, 8.32 and 35.3 um trenches within 0.3 um depth and under 1 um variation, 4+ um/min and isotropic SF6 up to 1380 angstrom/s, more SF6 reducing anisotropy and roughening, 90 mTorr trip limit, shorter etch cycles reducing scallops to as low as 50 nm, under 4 per cent non-uniformity, low electrode power and higher pressure favouring resist selectivity, anisotropy rising with electrode power and first rising then falling with pressure, 12 um x 404 um and 1.85 um x 63.6 um trenches and a 0.8 um x 47.4 um wall, thicker passivation near buried oxide suppressing footing, SiF4 redeposition at low SF6 flow, diffusivity inverse to pressure (fetch-tool summary); University of Alberta NanoFab, ‘A deep silicon RIE primer: Bosch etching of deep structures in silicon’ (April 2009): C4F8 passivation of about 10 s depositing a Teflon-like polymer and SF6 etch of about 15 s removing bottom polymer then etching silicon isotropically, flows 25 to 75 sccm (typically 50), minimum pressure about 30 mTorr, ICP 450 W, bias well below 100 V during deposition and above 100 V during etch, 0.5 to 1 um per cycle, 0.5 to 2.0 um/min, resist enough below 30 um, 0.6 um thermal oxide for 200+ um, 0.2 um Cr for 300+ um, oxide eroded during C4F8 when ions present, scalloped sidewalls at 85 to 92 degrees, 100 um deep 5 um wide example, 2 um features etching much slower than 20 um ones as a fundamental effect handled only in mask design, bulls-eye non-uniformity above 20 to 30 per cent exposed silicon, pedestaling at buried layers from charging, cryo and black-silicon alternatives (fetch-tool summary).

Ques: How thick must the mask be for a deep etch?

Thin for hard masks, thick for resist. The Alberta primer states that photoresist suffices for etches below 30 , 0.6 of thermal oxide for 200 or more, and 0.2 of Cr for 300 or more. These imply selectivities above 333 for oxide and above 1500 for chromium (computed). Oxide is eroded mainly during the CF step when ions are present (Alberta). Ayon et al. add that low electrode power and higher pressure favour resist selectivity, and that low temperature reduces resist etch rate. Their demonstrated structures reach aspect ratios of about 34 for trenches and 59 for a 0.8 wall (computed). Such depths need a hard mask (my reading). Reference: University of Alberta NanoFab, ‘A deep silicon RIE primer: Bosch etching of deep structures in silicon’ (April 2009): C4F8 passivation of about 10 s depositing a Teflon-like polymer and SF6 etch of about 15 s removing bottom polymer then etching silicon isotropically, flows 25 to 75 sccm (typically 50), minimum pressure about 30 mTorr, ICP 450 W, bias well below 100 V during deposition and above 100 V during etch, 0.5 to 1 um per cycle, 0.5 to 2.0 um/min, resist enough below 30 um, 0.6 um thermal oxide for 200+ um, 0.2 um Cr for 300+ um, oxide eroded during C4F8 when ions present, scalloped sidewalls at 85 to 92 degrees, 100 um deep 5 um wide example, 2 um features etching much slower than 20 um ones as a fundamental effect handled only in mask design, bulls-eye non-uniformity above 20 to 30 per cent exposed silicon, pedestaling at buried layers from charging, cryo and black-silicon alternatives (fetch-tool summary); A. A. Ayon, C. C. Lin, R. A. Braff, M. A. Schmidt, R. Bayt and H. H. Sawin (MIT), ‘Etching characteristics and profile control in a time multiplexed inductively coupled plasma etcher’, Solid-State Sensors, Actuators and Microsystems Workshop, Hilton Head (1998): 1000 W coil and 300 W electrode at 13.56 MHz, SF6 etch and C4F8 passivation, rate mainly set by coil power, more SF6 and electrode power helping, ARDE reduced by higher SF6 flow (140 sccm example) because fewer redepositing products form, 8.32 and 35.3 um trenches within 0.3 um depth and under 1 um variation, 4+ um/min and isotropic SF6 up to 1380 angstrom/s, more SF6 reducing anisotropy and roughening, 90 mTorr trip limit, shorter etch cycles reducing scallops to as low as 50 nm, under 4 per cent non-uniformity, low electrode power and higher pressure favouring resist selectivity, anisotropy rising with electrode power and first rising then falling with pressure, 12 um x 404 um and 1.85 um x 63.6 um trenches and a 0.8 um x 47.4 um wall, thicker passivation near buried oxide suppressing footing, SiF4 redeposition at low SF6 flow, diffusivity inverse to pressure (fetch-tool summary).

Ques: What goes wrong at loading extremes and buried layers?

Bulls-eye non-uniformity and undercut at the buried oxide. The Alberta primer warns that when exposed silicon exceeds 20 to 30 per cent of the wafer, depth becomes non-uniform in a bulls-eye pattern. Ayon et al. achieved below 4 per cent non-uniformity on 64 trenches between the centre and 3 cm away. Purdue notes that low pressure reduces microloading. At a buried layer, Alberta describes pedestaling, an undercut at the oxide-silicon interface caused by charging. Ayon et al. suppress footing at SOI interfaces with thicker passivation near the oxide. In my reading, ions deflected by charge on the exposed oxide attack the base of the structure, which is why the final cycles are changed. Reference: University of Alberta NanoFab, ‘A deep silicon RIE primer: Bosch etching of deep structures in silicon’ (April 2009): C4F8 passivation of about 10 s depositing a Teflon-like polymer and SF6 etch of about 15 s removing bottom polymer then etching silicon isotropically, flows 25 to 75 sccm (typically 50), minimum pressure about 30 mTorr, ICP 450 W, bias well below 100 V during deposition and above 100 V during etch, 0.5 to 1 um per cycle, 0.5 to 2.0 um/min, resist enough below 30 um, 0.6 um thermal oxide for 200+ um, 0.2 um Cr for 300+ um, oxide eroded during C4F8 when ions present, scalloped sidewalls at 85 to 92 degrees, 100 um deep 5 um wide example, 2 um features etching much slower than 20 um ones as a fundamental effect handled only in mask design, bulls-eye non-uniformity above 20 to 30 per cent exposed silicon, pedestaling at buried layers from charging, cryo and black-silicon alternatives (fetch-tool summary); A. A. Ayon, C. C. Lin, R. A. Braff, M. A. Schmidt, R. Bayt and H. H. Sawin (MIT), ‘Etching characteristics and profile control in a time multiplexed inductively coupled plasma etcher’, Solid-State Sensors, Actuators and Microsystems Workshop, Hilton Head (1998): 1000 W coil and 300 W electrode at 13.56 MHz, SF6 etch and C4F8 passivation, rate mainly set by coil power, more SF6 and electrode power helping, ARDE reduced by higher SF6 flow (140 sccm example) because fewer redepositing products form, 8.32 and 35.3 um trenches within 0.3 um depth and under 1 um variation, 4+ um/min and isotropic SF6 up to 1380 angstrom/s, more SF6 reducing anisotropy and roughening, 90 mTorr trip limit, shorter etch cycles reducing scallops to as low as 50 nm, under 4 per cent non-uniformity, low electrode power and higher pressure favouring resist selectivity, anisotropy rising with electrode power and first rising then falling with pressure, 12 um x 404 um and 1.85 um x 63.6 um trenches and a 0.8 um x 47.4 um wall, thicker passivation near buried oxide suppressing footing, SiF4 redeposition at low SF6 flow, diffusivity inverse to pressure (fetch-tool summary); Purdue ECE 695Q, lectures 46 and 47 (nanoHUB, April 2016): C4F8 used for polymerization in deep RIE, Bosch process alternating passivation and etch, low pressure to reduce ion scattering and microloading (fetch-tool summary).

References

  1. University of Alberta NanoFab, “A deep silicon RIE primer: Bosch etching of deep structures in silicon,” April 2009. Available: https://www.nanofab.ualberta.ca/wp-content/uploads/2009/03/primer_deepsiliconrie.pdf
  2. A. A. Ayon, C. C. Lin, R. A. Braff, M. A. Schmidt, R. Bayt and H. H. Sawin, “Etching characteristics and profile control in a time multiplexed inductively coupled plasma etcher,” Solid-State Sensors, Actuators and Microsystems Workshop, Hilton Head, 1998, doi:10.31438/trf.hh1998.10. Available: https://transducer-research-foundation.org/technical_digests/HiltonHead_1998/hh1998_0041.pdf
  3. Purdue ECE 695Q, lectures 46 and 47, April 2016, nanoHUB. Available: https://nanohub.org/resources/25351/download/2016.04.22-ECE695Q-L47.pdf
  4. Inductively Coupled Plasma Etcher (ICP-RIE) page of this vault.
  5. Wet Etch Bench page of this vault.

Related pages in this vault: Inductively Coupled Plasma Etcher (ICP-RIE), Wet Etch Bench, Through-Silicon Vias as Passives, Stylus Profiler, Atomic Layer Etch (ALE) Tool.