Ovonic Threshold Switch (OTS)

1. Theory

• Definition: An ovonic threshold switch (OTS) is a two-terminal selector made of a thin amorphous chalcogenide layer that switches reversibly between a high-resistance off state and a conductive on state at a threshold voltage.
• No phase change: The material is chosen not to crystallize, so switching is purely electronic and repeatable, unlike the threshold switching of a PCM cell that leads to crystallization.
• Subthreshold conduction: Below threshold, current follows Poole-Frenkel-type field-assisted emission.
• Threshold voltage: Scales roughly linearly with layer thickness ($V_{th}\approx V_0+E_{th}t$), so it can be tuned by thickness.
• Mechanism debate: Electronic (field-induced filling or multiplication) and thermal models both exist; the empirical rows fit either.
• Selectivity: Very high, because the half-select voltage lies below threshold while the full select voltage lies above it.

2. Working Principle

• Off state: Below $V_{th}$ only a tiny leakage current flows, isolating half-selected cells in the $V/2$ scheme.
• Threshold switching: Above $V_{th}$, after a delay that shrinks exponentially with overdrive, the device snaps back to a low-resistance state.
• On state: The voltage stays near the holding voltage $V_{hold}$ plus $I{R}_{on}$ while current flows to the memory element.
• Turn-off: When current falls below the holding current, the device returns to the off state with no structural change.
• Snap-back spike: Charge on parallel parasitic capacitance, $C_{par}(V_{th}-V_{hold})$, discharges through the memory element and can disturb it.
• Array size: The number of cells per line is limited by the summed leakage of half-selected cells relative to the selectivity.

3. Applications

• Crosspoint memory selector: The access device in stacked crosspoint phase-change memory, valued for its symmetry, low leakage and back-end compatibility.
• 3D stackable memories (development): Selector for future crosspoint ReRAM and selector-only memory arrays.

Name	Formula	Related Formulae	Variables/Constants
Subthreshold conduction (Poole-Frenkel)	$J={\sigma }_{0}E\exp \left[-\frac{E_a-q\sqrt{qE/\left(\pi \epsilon \right)}}{k_{B}T}\right]$	$E_a\approx \frac{E_g}{2}$ $J\propto \exp \left(-\frac{E_a}{k_{B}T}\right)\left(lowfield\right)$	$\begin{array}{r}J:currentdensityoftheselectorbelow\\ thethresholdvoltage\end{array}$ ${\sigma }_0:conductivityprefactor$ $E:electricfieldinthechalcogenidelayer$ $\begin{array}{r}{E}_a:activationenergyoftheconductionat\\ lowfield\end{array}$ $q:elementarycharge$ $\begin{array}{r}\epsilon :high-frequency(optical)\\ permittivityofthechalcogenide\end{array}$ $k_B,T:Boltzmannconstantandtemperature$ $\begin{array}{r}{E}_g:bandgapoftheamorphouschalcogenide\\ (theFermilevelliesnearmid-gap,so{E}_a\\ isabouthalfofthegap)\end{array}$ $\begin{array}{r}(thecurrentissymmetricinvoltage,\\ J\left(-E\right)=-J\left(E\right))\end{array}$ $\begin{array}{r}(thePhaseChangeMemorypagefitsthe\\ samesubthresholdphysicswiththe\\ Ielminihopping(sinh)form;dataovera\\ limitedfieldrangecanbefittedby\\ either,andneitherispreferredhere)\end{array}$
Threshold voltage and thickness	$V_{th}\approx V_0+E_{th}t$	$E_{th}=\frac{V_{th}-V_0}{t}$	$\begin{array}{r}{V}_{th}:voltageatwhichtheselectorswitches\\ fromtheoffstatetotheonstate\\ (thresholdswitching)\end{array}$ $\begin{array}{r}{V}_0:offsetvoltageofthelinearfitof{V}_{th}\\ againstthickness(includingthevoltage\\ droppedattheelectrodeinterfaces)\end{array}$ $E_{th}:thresholdfield$ $t:thicknessofthechalcogenidelayer$ $\begin{array}{r}(anempiricallinearfit;somedatashow\\ asub-linearriseof{V}_{th}witht)\end{array}$
Delay time of threshold switching	$t_d\approx t_0\exp \left(-\frac{V-V_{th}}{V_d}\right)$	$V>V_{th}$	$\begin{array}{r}{t}_d:delaybetweenapplyingavoltageV\\ abovethethresholdandtheswitchingto\\ theonstate\end{array}$ $\begin{array}{r}{t}_0:delayatavoltageequaltothestatic\\ thresholdvoltage\end{array}$ $V:appliedvoltagepulseamplitude$ $V_{th}:staticthresholdvoltage$ $\begin{array}{r}{V}_d:characteristicvoltageofthe\\ exponentialdecreaseofthedelay(an\\ empiricalfitparameter)\end{array}$ $\begin{array}{r}(thedelayfallsrapidlywithoverdrive,\\ sothedynamicthresholdforashortpulse\\ isabovethestaticone{V}_{th};thelinear\\ exponentisanempiricalfit,and\\ field-inducednucleationmodelspredict\\ anexponentin1/Vor1/V^{2}instead)\end{array}$
On-state model and voltage division in a 1S1R cell	$V_{sel}=V_{hold}+R_{on}I$	$V_{mem}=V_{app}-V_{sel}-I{R}_s$ $I=\frac{V_{app}-V_{hold}}{R_{on}+R_s+R_{mem}}$	$V_{sel}:voltageacrosstheselectorintheonstate$ $\begin{array}{r}{V}_{hold}:holdingvoltage,thevoltage\\ extrapolatedtozerocurrentonthe\\ on-statebranch\end{array}$ $R_{on}:dynamicon-stateresistanceoftheselector$ $I:currentthroughthecell$ $\begin{array}{r}{V}_{mem}:voltageacrossthememoryelementin\\ serieswiththeselector\end{array}$ $\begin{array}{r}{V}_{app}:voltageappliedacrosstheselector\\ andmemoryelementtogether\end{array}$ $\begin{array}{r}{R}_s:seriesresistanceoftheelectrodes\\ andthelines\end{array}$ $\begin{array}{r}{R}_{mem}:resistanceofthememoryelementin\\ itsstoredstate(sothevoltageleftfor\\ thememoryelementis{V}_{app}-V_{hold}minusthe\\ dropacross{R}_{on}and{R}_s)\end{array}$ $\begin{array}{r}(linearizedon-statebranch;V_{hold}\\ dependsoncurrentandtemperature,and\\ R_{mem}istakenconstant,i.e.thememory\\ elementdoesnotswitch)\end{array}$
Snap-back and relaxation oscillation	$t_c=RC\ln \frac{V_s-V_{hold}}{V_s-V_{th}}$	$R>R_{NDR}$ $f\approx \frac{1}{t_c+t_d+t_{disch}}$	$\begin{array}{r}{t}_c:timeforthecapacitorinparallel\\ withtheselectortochargefrom{V}_{hold}to{V}_{th}\\ throughtheresistanceR\end{array}$ $R:seriesresistanceofthesource$ $\begin{array}{r}C:capacitanceinparallelwiththe\\ selector(thedeviceandtheparasitic\\ capacitance)\end{array}$ $V_s:sourcevoltage,largerthan{V}_{th}$ $V_{hold},V_{th}:holdingvoltageandthresholdvoltage$ $\begin{array}{r}{R}_{NDR}:magnitudeofthenegative\\ differentialresistance-dV/dIofthe\\ snap-backbranch.ForR>R_{NDR}theload\\ linecrossestheS-shapedcurveonlyon\\ thatbranch,andwiththeparallelCthis\\ pointisunstable,sothecircuit\\ oscillates;forR<R_{NDR}thecelllatches\\ intheonortheoffstate\end{array}$ $\begin{array}{r}f:frequencyoftherelaxationoscillation\\ (usedtomeasurethethresholdandholding\\ voltage)\end{array}$ $\begin{array}{r}{t}_d,t_{disch}:switchingdelayanddischarge\\ timeofthecapacitorineachcycle\end{array}$ $\begin{array}{r}(t_{c}assumesanopenselectorwhileit\\ isoffandaninstantaneousdischarge)\end{array}$
Charge and energy released at the snap-back	$Q_{spike}=C_{par}\left(V_{th}-V_{hold}\right)$	$E_{spike}=\frac{1}{2}{C}_{par}\left(V_{th}^2-V_{hold}^2\right)$	$\begin{array}{r}{Q}_{spike}:chargedeliveredthroughthecell\\ whentheselectorswitchesandthe\\ parasiticcapacitancedischarges\end{array}$ $\begin{array}{r}{C}_{par}:parasiticcapacitanceinparallel\\ withtheselector,fromthelineandthe\\ memoryelement\end{array}$ $V_{th},V_{hold}:thresholdvoltageandholdingvoltage$ $\begin{array}{r}{E}_{spike}:energyofthesamedischarge(it\\ mustbesmallcomparedwiththeenergy\\ thatwoulddisturbthestoredstateofthe\\ memoryelement)\end{array}$
Selectivity and leakage requirement	$S=\frac{I\left(V_{sel}\right)}{I\left(V_{sel}/2\right)}$	$N_{max}\approx 1+\frac{mS}{2}$ $m=\frac{I_{leak,total}}{I_{sel}}$	$\begin{array}{r}S:selectivity,theratioofthecurrent\\ atthefullselectionvoltagetothatat\\ halfthevoltage(V/2biasscheme)\end{array}$ $\begin{array}{r}I\left(V_{sel}\right):currentoftheselectedcellat\\ thereadvoltage\end{array}$ $I\left(V_{sel}/2\right):leakageofahalf-selectedcell$ $\begin{array}{r}{N}_{max}:numberofcellsononelineforwhich\\ thetotalleakageofthe2\left(N-1\right)\\ half-selectedcellsismtimesthesignal\\ oftheselectedcell:2(N-1)I(V_{sel}/2)=mI(V_{sel})\end{array}$ $\begin{array}{r}m:ratioofthetotalleakagecurrentto\\ theselectedcellcurrentthattheread\\ circuitcanaccept(forexample0.1)\end{array}$ $\begin{array}{r}(anestimatethattakesequalleakagein\\ allhalf-selectedcellsandignoresthe\\ lineresistance)\end{array}$

Important Questions

Ques: How does an ovonic threshold switch work, and how does it differ from the threshold switching of a phase-change cell?

An ovonic threshold switch (OTS) is a thin layer of an amorphous chalcogenide between two electrodes. Below the threshold voltage its current is small and follows Poole-Frenkel-type conduction. At $V_{th}$ it switches, within the delay time, to a state with a low resistance and an almost constant voltage $V_{hold}$ across it (snap-back). It returns to the high-resistance state when the current falls below the holding current, with no change of structure. In a phase-change cell, threshold switching of the amorphous phase happens as well, but the heat released afterwards crystallizes the material (set). An OTS material is chosen not to crystallize, with a high crystallization temperature (typically arsenic-containing Ge-Se or Si-Ge-As-Te based glasses), so that the switching is repeatable and electronic only. Reference: S.R. Ovshinsky, Phys. Rev. Lett. 21, 1450 (1968); D. Adler, H.K. Henisch and N. Mott, “The mechanism of threshold switching in amorphous alloys,” Rev. Mod. Phys. 50, 209 (1978).

Ques: What causes threshold switching?

The mechanism is still debated. Electronic models describe carrier multiplication or field-induced filling of the localized states at a high field, which makes the layer conductive without a large temperature rise, and the thermal models describe a runaway of the current by Joule heating. The data on the nanosecond scale and the exponential decrease of the delay time with the overdrive support an electronic or field-induced nucleation picture. The rows of this page (the Poole-Frenkel current, the linear $V_{th}(t)$ and the exponential delay) are empirical descriptions that fit either picture and do not select one. Reference: D. Adler, H.K. Henisch and N. Mott, Rev. Mod. Phys. 50, 209 (1978); A. Pirovano, A.L. Lacaita, A. Benvenuti, F. Pellizzer and R. Bez, “Electronic switching in phase-change memories,” IEEE Trans. Electron Devices 51, 452 (2004); D. Ielmini and Y. Zhang, J. Appl. Phys. 102, 054517 (2007).

Ques: What are selectivity and the V/2 scheme, and what limits the array size?

In a crosspoint array the selected cell gets the full voltage and the half-selected cells on the same lines get half of it. The selector must therefore pass a large current at $V_{sel}$ and a very small current at $V_{sel}/2$, so the selectivity $S=I(V_{sel})/I(V_{sel}/2)$ is the main figure of merit. There are $2(N-1)$ half-selected cells per selected cell, and their leakage adds to the signal of the read, so the number of cells per line is limited to about $mS/2$ in the selectivity row, where $m$ is the tolerable ratio of total leakage to signal. An OTS has very high selectivity because the half-selected voltage is below the threshold while the selected voltage is above it, with no bias dependence like that of a diode. Reference: G.W. Burr et al., “Access devices for 3D crosspoint memory,” J. Vac. Sci. Technol. B 32, 040802 (2014); D.C. Kau et al., “A stackable cross point phase change memory,” IEDM Tech. Dig. (2009), paper 27.1.

Ques: Why can the snap-back damage or disturb the memory element in series?

At switching, the charge stored on the parasitic capacitance in parallel with the selector, $Q_{spike}=C_{par}(V_{th}-V_{hold})$, flows through the cell in a very short time. If the memory element is a ReRAM or phase-change cell, this current can be above its switching current and disturb the state. This is reduced by keeping the capacitance low (the selector close to the memory element, with the line capacitance isolated), by limiting the overshoot with a series resistance (which also lowers the voltage left for the memory element after switching, see the on-state row, so the two must be balanced), and by choosing a small $V_{th}-V_{hold}$. The relaxation-oscillation row gives the relation between the capacitance, the series resistance and the oscillation frequency. Reference: G.W. Burr et al., J. Vac. Sci. Technol. B 32, 040802 (2014); D. Ielmini and Y. Zhang, J. Appl. Phys. 102, 054517 (2007).

Ques: How does an OTS compare with a diode or a transistor as an access device?

A transistor (1T1R) gives full control and a controllable compliance current but takes the area of a transistor and needs a single-crystal silicon channel, which cannot easily be stacked in the back end. A diode (1D1R) allows a high density and works for a unipolar element or a bipolar element with a selector with a symmetric characteristic, but its on-current density is limited by the series resistance and its forward-reverse behaviour is not symmetric. An OTS is symmetric in voltage, can be stacked in a back-end process at a low temperature, has a high on-current density and a very low leakage, and has a threshold that can be adjusted by the thickness; the cost is the snap-back (the spike), the delay time, and the stability of the threshold voltage with time, which is dealt with on the reliability pages. Reference: G.W. Burr et al., J. Vac. Sci. Technol. B 32, 040802 (2014); S.M. Sze and Kwok K. Ng, Physics of Semiconductor Devices, 3rd ed., Wiley, 2007.

Related pages in this vault: Mixed Ionic Electronic Conduction Selector (MIEC), Phase Change Memory (PCM), Diode-Type Selector (PN and Schottky), Resistive Random Access Memory (ReRAM, RRAM), Diode for Alternating Current (DIAC), Conductive AFM (C-AFM).