1. Theory
- Definition: Phase-change memory (PCM or PRAM) is a two-terminal cell in which a chalcogenide such as (GST) is switched by Joule heating between a crystalline (low-resistance) and an amorphous (high-resistance) phase.
- Two phases: The crystalline phase conducts well; the amorphous glass conducts by thermally activated hopping between localized states.
- Threshold switching: Above a threshold field the amorphous phase switches electronically to a conductive state (snap-back), allowing current to flow without a very high voltage.
- Nucleation vs growth: GST is nucleation-dominated; Sb-rich alloys (doped , AgInSbTe) are growth-dominated and crystallize faster in small cells.
- Resistance drift: The amorphous resistance rises as () through structural relaxation.
- Good scaling: Melt volume falls as and reset current roughly as , so programming current drops as the cell shrinks.
2. Working Principle
- Reset (amorphize): A short, high-current pulse melts a region above the heater, and the pulse ends fast enough to quench it into glass.
- Set (crystallize): A longer, lower pulse holds the amorphous region between the glass-transition and melting temperatures until it crystallizes.
- Set is slower: Crystallization by nucleation and growth takes tens of nanoseconds or more, while reset is limited only by the thermal time constant.
- Read: A small voltage below the threshold measures resistance without heating.
- Multi-level cells: Partial amorphous or crystalline fractions give intermediate resistances, but drift narrows the gaps between levels.
- Material engineering: Doping (N, C) raises crystallization temperature for retention and lowers reset current.
3. Applications
- Embedded memory in automotive microcontrollers: Embedded PCM at advanced FD-SOI nodes, valued for high-temperature data retention.
- Neuromorphic and in-memory computing (research): Analog PCM synaptic arrays.
- Historical role: Storage-class memory (3D XPoint-type products) between DRAM and NAND, since discontinued.
| Name | Formula | Related Formulae | Variables/Constants |
|---|---|---|---|
| Resistance of the set and reset states | |||
| Subthreshold hopping conduction in the amorphous phase | |||
| Threshold voltage | |||
| Joule heating hot-spot temperature | |||
| Energy to melt a volume | |||
| Quench condition for amorphization | |||
| Crystallization kinetics (Johnson-Mehl-Avrami) | |||
| Classical nucleation and crystal growth | |||
| Resistance drift of the amorphous phase | |||
| Partially crystallized cell (effective medium) |
Important Questions
Ques: How does a phase-change memory cell store a bit, and what do the set and reset pulses do?
A phase-change cell contains a chalcogenide such as GeSbTe (GST) which can be crystalline (low resistance) or amorphous (high resistance). In a reset, a short, high current pulse heats a region above the melting temperature (the hot-spot temperature row) and the pulse is cut off quickly enough for the melt to be quenched into the glass (the quench condition). In a set, a longer pulse of lower amplitude holds the amorphous region between the glass transition and the melting temperature, where crystallization is fastest, until the crystal front has grown over it (JMAK and growth rows). The state is read at a small voltage that causes no heating. Set is the slower operation and reset needs the larger current. Reference: H.-S.P. Wong et al., “Phase change memory,” Proc. IEEE 98, 2201 (2010); S. Raoux, W. Welnic and D. Ielmini, “Phase change materials and their application to nonvolatile memories,” Chem. Rev. 110, 240 (2010).
Ques: What is threshold switching, and why is it needed to set an amorphous cell?
The amorphous state has a very high resistance, so a voltage below passes too little current to heat the material for a set. Above the threshold field, the amorphous layer switches electronically to a conductive state, with a drop in voltage (snap-back) to the holding voltage , and the current can then be large at a moderate voltage. This lets the cell be set without a very high voltage. The switching is electronic: if the voltage is removed early, the cell returns to the amorphous state without crystallizing. The same kind of threshold switching is used in ovonic threshold selectors, which use a chalcogenide composition chosen so that it does not crystallize (covered on the Selector pages). Reference: S.R. Ovshinsky, “Reversible electrical switching phenomena in disordered structures,” Phys. Rev. Lett. 21, 1450 (1968); D. Ielmini and Y. Zhang, “Analytical model for subthreshold conduction and threshold switching in chalcogenide-based memory devices,” J. Appl. Phys. 102, 054517 (2007).
Ques: Why does a phase-change cell scale well?
The melted volume falls with the cube of the linear size of the heater contact, so the reset energy scales as in the melting-energy row. The reset current scales roughly with (not with the area), because the thermal resistance of a hot spot rises as (the hemispherical thermal resistance row), so the required power for a given temperature rise falls as the cell shrinks. The programming current therefore decreases with scaling, in contrast to charge-storage memory, in which the programming voltage does not scale. The limit is the size at which the amorphous region is too thin to hold its state, at which the thermal crosstalk between neighbouring cells becomes a problem. Reference: A. Pirovano et al., “Scaling analysis of phase-change memory technology,” IEDM Tech. Dig. (2003), paper 29.6; A.L. Lacaita and D.J. Wouters, “Phase-change memories,” Phys. Status Solidi A 205, 2281 (2008).
Ques: Why is the set operation slower than the reset operation?
Reset only needs the melt to be formed and quenched, and the pulse can be of the order of nanoseconds or tens of nanoseconds, limited by the thermal time constant. Set needs the amorphous region to crystallize, which is a thermally activated process with nucleation and growth (the JMAK and nucleation rows), and the time depends on the material and the temperature: tens of nanoseconds for fast growth-dominated alloys, and longer for slow ones. Crystallization is fastest at an intermediate temperature between the glass transition and the melting temperature, so the set pulse has to hold the cell in this range, which is why its amplitude is lower and its length longer. Reference: S. Raoux, W. Welnic and D. Ielmini, Chem. Rev. 110, 240 (2010); H.-S.P. Wong et al., Proc. IEEE 98, 2201 (2010).
Ques: What is resistance drift, and why does it matter for multi-level cells?
After a reset the resistance of the amorphous phase increases with time as , with of about 0.1, and the threshold voltage drifts as well. The crystalline phase shows almost no drift. The explanation usually given is structural relaxation of the glass, which widens the gap or reduces the density of the localized states. In a multi-level cell the intermediate levels have a higher amorphous fraction and move with time, so the separation between levels shrinks and a drift-tolerant read is needed. The retention against crystallization at high temperature is a separate topic and is covered on the reliability pages. Reference: D. Ielmini, A.L. Lacaita and D. Mantegazza, “Recovery and drift dynamics of resistance and threshold voltages in phase-change memories,” IEEE Trans. Electron Devices 54, 308 (2007); V.G. Karpov, Y.A. Kryukov, I.V. Karpov and M. Mitra, “Fundamental drift of parameters in chalcogenide phase change memory,” J. Appl. Phys. 102, 124503 (2007).
Ques: Which phase-change materials are used, and how do nucleation-dominated and growth-dominated alloys differ?
The most common alloy is GeSbTe on the GeTe-SbTe pseudo-binary line, which crystallizes in a metastable rock-salt-like phase at about 150 and melts at about 620 . GeSbTe is usually described as nucleation-dominated: crystals nucleate in many places within the amorphous region and grow slowly. Alloys rich in Sb, such as doped SbTe or AgInSbTe, are growth-dominated: few nuclei form and the crystal front moves fast from the boundary, which gives a shorter set time for a small cell. Doping (for example with N or C) is used to raise the crystallization temperature and to reduce the reset current. Reference: S. Raoux, W. Welnic and D. Ielmini, Chem. Rev. 110, 240 (2010); M. Wuttig and N. Yamada, “Phase-change materials for rewriteable data storage,” Nat. Mater. 6, 824 (2007).
Ques: How can the resistance of an intermediate level be estimated?
A partly crystallized cell is a mixture of two phases, and the effective medium row gives its conductivity from the crystalline fraction . The resistance falls slowly with until the crystalline regions connect (percolation), when it drops sharply, so the intermediate levels are obtained either by a controlled amorphous region in a reset-state cell or by partial crystallization from the amorphous state. The effective medium model gives a first estimate, but the real cell is not a uniform mixture and the amorphous region has a defined shape, which is why the cell-level resistance is also fitted with the geometry-based rows. Reference: D. Ielmini and Y. Zhang, J. Appl. Phys. 102, 054517 (2007); D.A.G. Bruggeman, Ann. Phys. 416, 636 (1935).
Related pages in this vault: Resistive Random Access Memory (ReRAM, RRAM), Ovonic Threshold Switch (OTS), Organic and Molecular Resistive Memory, Floating Gate Flash Memory (NOR and NAND), Floating Gate and Charge-Trap Flash Memory (NOR, NAND and 3D NAND), Mixed Ionic Electronic Conduction Selector (MIEC), Static and Dynamic Random Access Memory (SRAM and DRAM), Silicon on Insulator (SOI) MOSFET, Two-Dimensional Material Memristor (Atomristor and Memtransistor).