1. Theory
- Definition: Defect SPC charts the number of defects per wafer, die or area against limits so that excursions are found and acted on (NIST; Hall et al.).
- Poisson c-chart: For random defects the mean and variance are equal, giving limits (NIST).
- Clustering: Real particle counts are overdispersed, so Poisson limits are too tight and the c-chart signals when the process is in control (Kawamura et al.; Bogdanov et al.).
- Alternatives: Negative-binomial limits, transformations, probability limits, XmR charts or defect-limited yield charts (Kawamura et al.; NIST; Riley).
2. Working Principle
- Baseline: Count defects on a preliminary set of inspection units, estimate and the variance, and check the dispersion index (NIST; Bogdanov et al.).
- Limits: Use Poisson limits only when variance is close to the mean; otherwise use limits that include the clustering term (Kawamura et al.).
- Monitoring: Chart counts, killer-class counts or adders per layer, and apply run rules as on the Statistical Process Control (SPC) page (Hall et al.).
- Reaction: Out-of-control points start the loop of the Defect Inspection Workflow and Sampling Plans page (Hall et al.).
3. Applications
- Particle monitors: Bare-wafer particle counts per tool (Kawamura et al.).
- In-line defect charts: Counts per layer on product wafers (NIST; Hall et al.).
- Yield-weighted charts: Defect-limited yield instead of raw counts (Riley).
Poisson c-Chart
| Name | Formula | Related Formulae | Variables/Constants |
|---|---|---|---|
| c-chart | |||
| Poisson validity | |||
| Variance-stabilising transforms |
Clustered Counts
| Name | Formula | Related Formulae | Variables/Constants |
|---|---|---|---|
| Overdispersion | |||
| Negative-binomial limits | |||
| Chart choice |
Excursion Monitoring
| Name | Formula | Related Formulae | Variables/Constants |
|---|---|---|---|
| Excursion detection | |||
| Beyond counts | |||
| Cost of a chart |
Important Questions
Ques: How is a c-chart for wafer defects built?
From the average count per inspection unit, assuming Poisson statistics. NIST gives and , with no lower limit if it is negative, because a Poisson count has variance equal to its mean. Its example uses 25 wafers of 100 chips with 400 defects in total, so , UCL 28 and LCL 4. Wafer 24, with 31 defects, falls above the UCL. Under the Poisson assumption a count above 28 has probability 0.0022 at a mean of 16, an average run length of about 460 wafers (computed). If the mean is not known, NIST estimates it as from a preliminary sample of inspection units. Reference: NIST/SEMATECH e-Handbook of Statistical Methods, section 6.3.3.1 ‘Counts control charts’: Poisson p(x) = e^-c c^x/x! with mean and variance c, c-chart UCL = c + k sqrt(c), centre c, LCL = c - k sqrt(c) with k usually 3 and no LCL if negative, c estimated by c-bar from preliminary units, example of 25 wafers of 100 chips with counts 16, 14, 28, 16, 12, 20, 10, 12, 10, 17, 19, 17, 14, 16, 15, 13, 14, 16, 11, 20, 11, 19, 16, 31, 13 totalling 400, c-bar 16, UCL 28 and LCL 4, normal approximation adequate for mean at least 5 and no LCL below a mean of 9, for mean 10 the symmetric LCL 0.513 against P(0) = 0.000045 so a lower limit of 2 or 3 is suggested, transformations 2 sqrt(c), 2 sqrt(c + 3/8) and sqrt(c) + sqrt(c + 1) with limits y-bar plus or minus 3, probability limits as an alternative, 3-sigma limits generally not a good idea for highly skewed distributions (fetch-tool summary).
Ques: Why do Poisson charts give false alarms on real defect data?
Because defects cluster, so the variance exceeds the mean. Kawamura et al. state that particle counts per wafer do not follow the Poisson distribution assumed by the c-chart, so the process is often declared out of control when it is in control. Bogdanov et al. give the negative-binomial variance as larger than the mean, which can be written . With a mean of 16 and , the standard deviation is 12 instead of 4. The Poisson UCL of 28 would then be exceeded 13.9 per cent of the time, about one wafer in seven (computed, assuming , a value MIT gives as typical). Kawamura et al. propose negative-binomial limits with outlier removal. Reference: H. Kawamura, K. Nishina and M. Higashide, ‘Control charts for particles in the semiconductor manufacturing process’, Stochastics and Quality Control (formerly Economic Quality Control) 23(1), 95-107 (2008), abstract: particle counts per wafer do not follow the Poisson distribution assumed by the c-chart, so the process is often declared out of control when it is in control, counts assumed negative binomial with a chart procedure including outlier removal, shown by simulation, numerical analysis and real data (fetch-tool summary); Yu. I. Bogdanov, N. A. Bogdanova and A. V. Rudnev, ‘Multilevel clustering fault model for IC manufacture’, arXiv:physics/0310012: negative-binomial mean a/b and variance (a/b^2)(1 + b) exceeding the mean, moment estimate a = mu^2/(sigma^2 - mu) (fetch-tool summary); MIT OpenCourseWare 2.830J, Lecture 10 ‘Yield modeling’ (2008): cluster parameter to be determined empirically, typical 1.5 to 2 for memory and microprocessors (fetch-tool summary).
Ques: Is the NIST example itself Poisson?
Nearly. NIST’s 25 wafer counts have a mean of 16 and a sample variance of 25.25, a dispersion index of 1.58, which implies a cluster parameter of about 28 (computed). A Poisson process would give an index near 1. Bogdanov et al. note that clustering effectively vanishes for cluster parameters above about 4 or 5, so this data set is only mildly clustered. The single high wafer at 31 inflates the variance noticeably. In my reading, the example illustrates the method, but real particle data with near 1.5 to 2 (MIT) would break the Poisson limits badly. The dispersion index should therefore be checked before any c-chart is used. Reference: NIST/SEMATECH e-Handbook of Statistical Methods, section 6.3.3.1 ‘Counts control charts’: Poisson p(x) = e^-c c^x/x! with mean and variance c, c-chart UCL = c + k sqrt(c), centre c, LCL = c - k sqrt(c) with k usually 3 and no LCL if negative, c estimated by c-bar from preliminary units, example of 25 wafers of 100 chips with counts 16, 14, 28, 16, 12, 20, 10, 12, 10, 17, 19, 17, 14, 16, 15, 13, 14, 16, 11, 20, 11, 19, 16, 31, 13 totalling 400, c-bar 16, UCL 28 and LCL 4, normal approximation adequate for mean at least 5 and no LCL below a mean of 9, for mean 10 the symmetric LCL 0.513 against P(0) = 0.000045 so a lower limit of 2 or 3 is suggested, transformations 2 sqrt(c), 2 sqrt(c + 3/8) and sqrt(c) + sqrt(c + 1) with limits y-bar plus or minus 3, probability limits as an alternative, 3-sigma limits generally not a good idea for highly skewed distributions (fetch-tool summary); Yu. I. Bogdanov, N. A. Bogdanova and A. V. Rudnev, ‘Multilevel clustering fault model for IC manufacture’, arXiv:physics/0310012: negative-binomial mean a/b and variance (a/b^2)(1 + b) exceeding the mean, moment estimate a = mu^2/(sigma^2 - mu) (fetch-tool summary); MIT OpenCourseWare 2.830J, Lecture 10 ‘Yield modeling’ (2008): cluster parameter to be determined empirically, typical 1.5 to 2 for memory and microprocessors (fetch-tool summary).
Ques: Which chart should be used for defect counts, and which recommendation is more likely right?
A chart whose limits reflect the real variance. NIST presents the Poisson c-chart, with transformations or probability limits for skewed data, and warns that 3-sigma limits are generally poor for highly skewed distributions. Riley argues that c-charts rarely work for noisy defect data and should be avoided. He recommends XmR charts, using the median range when outliers are present, and calls defect-limited yield charts the best option. Kawamura et al. instead keep a count chart but use negative-binomial limits. The NIST c-chart is correct only for Poisson data. For clustered fab data, Riley’s empirical XmR approach or Kawamura’s negative-binomial limits are more likely to work (my reading). XmR and run rules are on the SPC page. Reference: NIST/SEMATECH e-Handbook of Statistical Methods, section 6.3.3.1 ‘Counts control charts’: Poisson p(x) = e^-c c^x/x! with mean and variance c, c-chart UCL = c + k sqrt(c), centre c, LCL = c - k sqrt(c) with k usually 3 and no LCL if negative, c estimated by c-bar from preliminary units, example of 25 wafers of 100 chips with counts 16, 14, 28, 16, 12, 20, 10, 12, 10, 17, 19, 17, 14, 16, 15, 13, 14, 16, 11, 20, 11, 19, 16, 31, 13 totalling 400, c-bar 16, UCL 28 and LCL 4, normal approximation adequate for mean at least 5 and no LCL below a mean of 9, for mean 10 the symmetric LCL 0.513 against P(0) = 0.000045 so a lower limit of 2 or 3 is suggested, transformations 2 sqrt(c), 2 sqrt(c + 3/8) and sqrt(c) + sqrt(c + 1) with limits y-bar plus or minus 3, probability limits as an alternative, 3-sigma limits generally not a good idea for highly skewed distributions (fetch-tool summary); S. L. Riley, ‘Control charts for semiconductor defect management’, slides (20 January 2009): c-chart limits based on the Poisson distribution, problems with outlier data, c-charts rarely working well for noisy data and best avoided, XmR charts recommended with median range for large range variation, defect-limited yield (DLY) charts as the best option because they smooth noise and ease limit setting, run charts as a fallback (fetch-tool summary); H. Kawamura, K. Nishina and M. Higashide, ‘Control charts for particles in the semiconductor manufacturing process’, Stochastics and Quality Control (formerly Economic Quality Control) 23(1), 95-107 (2008), abstract: particle counts per wafer do not follow the Poisson distribution assumed by the c-chart, so the process is often declared out of control when it is in control, counts assumed negative binomial with a chart procedure including outlier removal, shown by simulation, numerical analysis and real data (fetch-tool summary); Statistical Process Control (SPC) page of this vault.
Ques: What does widening the limits cost in excursion detection?
Sensitivity. Suppose an excursion doubles the mean from 16 to 32 defects per wafer. With Poisson limits, a single wafer exceeds the UCL of 28 with probability 0.73. If counts are truly negative binomial with , the correct UCL is 52. That cuts in-control false alarms to 1.3 per cent, but catches the doubled mean on one wafer with probability only 0.17 (all computed, assuming ). Hall et al.’s cost-of-risk model grows with the chart’s average run length, so slower detection means more material at risk. In my reading, the answer is to chart quieter quantities, such as killer-class counts or adders, rather than to accept wide limits on total counts. Reference: G. D. R. Hall, R. Young, M. Dunne and M. Muro (ON Semiconductor), ‘A quality-cost model of in-line inspections for excursion detection and reduction’ (file name indicates ASMC 2008): excursion limits on defect count, density, characteristics or spatial pattern, cost of risk proportional to excursion rate, cost, inspection interval and average run length, false-alarm cost excluded (fetch-tool summary); Yu. I. Bogdanov, N. A. Bogdanova and A. V. Rudnev, ‘Multilevel clustering fault model for IC manufacture’, arXiv:physics/0310012: negative-binomial mean a/b and variance (a/b^2)(1 + b) exceeding the mean, moment estimate a = mu^2/(sigma^2 - mu) (fetch-tool summary); Defect Inspection Workflow and Sampling Plans page of this vault.
Ques: What should be charted besides total defect count?
Classes, adders, patterns and yield impact. Hall et al. set excursion limits on defect count, density, characteristics or spatial pattern, after classification into fine bins. Riley prefers defect-limited yield, which weights defects by their effect and smooths noise. In my reading, charting killer-class counts or adders, the defects added by one step, removes the background that inflates total-count variance. That lets limits stay tight. Spatial-pattern limits use the signatures of the Wafer-Map Spatial Signature Analysis page. NIST’s variance-stabilising transforms, such as , put any of these counts on a scale where limits of plus or minus 3 apply. A count of 31 at mean 16 maps to 3.1 units above centre (computed). Reference: G. D. R. Hall, R. Young, M. Dunne and M. Muro (ON Semiconductor), ‘A quality-cost model of in-line inspections for excursion detection and reduction’ (file name indicates ASMC 2008): excursion limits on defect count, density, characteristics or spatial pattern, cost of risk proportional to excursion rate, cost, inspection interval and average run length, false-alarm cost excluded (fetch-tool summary); S. L. Riley, ‘Control charts for semiconductor defect management’, slides (20 January 2009): c-chart limits based on the Poisson distribution, problems with outlier data, c-charts rarely working well for noisy data and best avoided, XmR charts recommended with median range for large range variation, defect-limited yield (DLY) charts as the best option because they smooth noise and ease limit setting, run charts as a fallback (fetch-tool summary); NIST/SEMATECH e-Handbook of Statistical Methods, section 6.3.3.1 ‘Counts control charts’: Poisson p(x) = e^-c c^x/x! with mean and variance c, c-chart UCL = c + k sqrt(c), centre c, LCL = c - k sqrt(c) with k usually 3 and no LCL if negative, c estimated by c-bar from preliminary units, example of 25 wafers of 100 chips with counts 16, 14, 28, 16, 12, 20, 10, 12, 10, 17, 19, 17, 14, 16, 15, 13, 14, 16, 11, 20, 11, 19, 16, 31, 13 totalling 400, c-bar 16, UCL 28 and LCL 4, normal approximation adequate for mean at least 5 and no LCL below a mean of 9, for mean 10 the symmetric LCL 0.513 against P(0) = 0.000045 so a lower limit of 2 or 3 is suggested, transformations 2 sqrt(c), 2 sqrt(c + 3/8) and sqrt(c) + sqrt(c + 1) with limits y-bar plus or minus 3, probability limits as an alternative, 3-sigma limits generally not a good idea for highly skewed distributions (fetch-tool summary); Wafer-Map Spatial Signature Analysis page of this vault.
References
- NIST/SEMATECH, “Counts control charts,” e-Handbook of Statistical Methods, section 6.3.3.1. Available: https://itl.nist.gov/div898/handbook/pmc/section3/pmc331.htm
- H. Kawamura, K. Nishina and M. Higashide, “Control charts for particles in the semiconductor manufacturing process,” Stochastics and Quality Control, vol. 23, no. 1, pp. 95-107, 2008, doi:10.1515/EQC.2008.95 (abstract read). Available: https://ideas.repec.org/a/bpj/ecqcon/v23y2008i1p95-107n10.html
- S. L. Riley, “Control charts for semiconductor defect management,” slides, 2009. Available: https://www.slideshare.net/slideshow/control-charts-for-semiconductor-defect-management-3050323/3050323
- Yu. I. Bogdanov, N. A. Bogdanova and A. V. Rudnev, “Multilevel clustering fault model for IC manufacture,” arXiv:physics/0310012. Available: https://arxiv.org/pdf/physics/0310012
- MIT OpenCourseWare 2.830J, “Lecture 10: yield modeling,” Spring 2008. Available: https://www.ocw.mit.edu/courses/2-830j-control-of-manufacturing-processes-sma-6303-spring-2008/4aff1e21de13870355ef44dbe71f45c6_lecture10.pdf
- G. D. R. Hall, R. Young, M. Dunne and M. Muro, “A quality-cost model of in-line inspections for excursion detection and reduction,” ON Semiconductor (file name indicates ASMC 2008). Available: https://www.onsemi.com/site/pdf/Hall_Session8_ASMC_MS_2008.pdf
- Statistical Process Control (SPC) page of this vault.
- Defect Inspection Workflow and Sampling Plans page of this vault.
- Wafer-Map Spatial Signature Analysis page of this vault.
Related pages in this vault: Statistical Process Control (SPC), Defect Inspection Workflow and Sampling Plans, Wafer-Map Spatial Signature Analysis, Yield Models and Critical Area, Laser-Scattering Particle Inspection, Defect-to-Yield Correlation and Kill Ratio.