Wafer-Map Spatial Signature Analysis

1. Theory

• Definition: A spatial signature is a pattern of defects or failing die on a wafer map that is associated with a manufacturing problem, such as a handler scratch or CVD contamination (Tobin et al.).
• Random against clustered: Defects that land independently follow Poisson statistics; clustering makes the variance of defects per die exceed the mean, ${\sigma }^2=\mu +{\mu }^2/\alpha$ (Bogdanov et al.).
• Signature families: Global, curvilinear, amorphous and micro-structure in spatial signature analysis (SSA), or Center, Donut, Edge-Ring, Edge-Loc, Loc, Scratch, Random and Near-full in WM-811K (Tobin et al.; Kim and Kim).
• Repeaters: A reticle defect prints in every field, so it repeats at the same field position (Applied Materials Israel).

2. Working Principle

• Grouping: Defects within about 1 to 10 $\mu$m are grouped, then merged by directional dilation into objects described by area, elongation, compactness and proximity (Tobin et al.).
• Clustering test: Join-count statistics compare neighbouring bad and good die with a no-clustering reference; flagged wafers are smoothed and thresholded into cluster maps (Hansen et al.).
• Classification: Fuzzy kNN reached 94 per cent expected performance on 13 classes; polar-coordinate CNNs reach 91 to 94 per cent on WM-811K (Tobin et al.; Kim and Kim).
• Root cause: Wafers with similar maps are grouped and checked for shared processing history, then matched to a library of known patterns (Hansen et al.).

3. Applications

• Excursion triage: Naming the likely step from the signature (Tobin et al.; Defect Sources and Classification page).
• Edge yield: Correlating edge, front and back-side defects by angle (KLA and SK Hynix).
• Reticle qualification: Detecting repeaters by field averaging (Applied Materials Israel).
• Yield modelling: Measuring the cluster parameter for the Yield Models and Critical Area page (Bogdanov et al.).

Signatures and Maps

Name	Formula	Related Formulae	Variables/Constants
Signature classes	$\text{Global, Curvilinear, Amorphous, Micro-structure}$	$\text{Center, Donut, Edge-Ring, Edge-Loc, Loc, Scratch, Random, Near-full}$	$\begin{array}{r}Tobinetal.:SSAclasses;KimandKim:\\ WM-811Kpatterndefinitions,Edge-Loc,Loc\\ andScratchlabellingsubjective;Defect\\ SourcesandClassificationpage\end{array}$ $\begin{array}{r}(myreading:theSSAclassesdescribe\\ shape,theWM-811Kclassesposition)\end{array}$
Map resolution	$p=\frac{200\mathrm{mm}}{512}\approx 390\mu \mathrm{m}$	$N_{defects}=10^2\text{to}10^3\text{per map}$	$\begin{array}{r}Tobinetal.:512\times 512densityimage,1\\ to10\mu \mathrm{m}grouping,about0.01\mu \mathrm{m}perpixel\\ inreview\end{array}$ $(computed:200\mathrm{mm}/512=390.6\mu \mathrm{m})$
Sampling of maps	$f_{map}=0.1\text{to}0.2$	$f_{reviewed}=0.2\times 0.2=0.04$	$\begin{array}{r}Tobinetal.:about20percentofwafers\\ mappedand20percentofthosereviewed\\ manually\end{array}$ $\begin{array}{r}(computed:about4percentofwafersseen\\ byaperson,themotivationforautomatic\\ SSA)\end{array}$

Random against Clustered

Name	Formula	Related Formulae	Variables/Constants
Join-count test	$BB={\sum }_{\text{bad}}\frac{n_{bad,neigh}}{n_{neigh}},GG={\sum }_{\text{good}}\frac{n_{good,neigh}}{n_{neigh}}$	$BB,GG\gg \text{null}\Rightarrow \text{clustered}$	$\begin{array}{r}Hansenetal.:comparedwiththe\\ distributionforawaferwithoutspatial\\ clustering,thensmoothing,arc-sine\\ square-roottransformandthresholdingto\\ aclustermap\end{array}$ $\begin{array}{r}(myreading:theformulasrestatethe\\ paten{t}^{\prime }sverbaldefinitions;itgivesno\\ closedform)\end{array}$
Dispersion index	${\sigma }^2=\mu +\frac{{\mu }^2}{\alpha }$	$\frac{{\sigma }^2}{\mu }=1+\frac{\mu }{\alpha },\alpha =\frac{{\mu }^2}{{\sigma }^2-\mu }$	$\begin{array}{r}\mu ,{\sigma }^2:meanandvarianceofdefectsper\\ die;Bogdanovetal.:negative-binomial\\ momentsandestimates;YieldModelsand\\ CriticalAreapage\end{array}$ $\begin{array}{r}(computed:\mu =0.5with{\sigma }^2=0.75gives\alpha =\\ 1andindex1.5;Poissongivesindex1)\end{array}$
Cluster parameter	$\alpha =1.5\text{to}2\text{(memory, microprocessor)}$	$\alpha =0.3\text{to}7,\text{Poisson-like above}4\text{to}5$	$\begin{array}{r}MIT2.830J;Bogdanovetal.:64Myield\\ 0.0012(Poisson)against0.4924\\ (clustered)\end{array}$ $\begin{array}{r}(myreading:clusteringputsseveral\\ defectsonthesamedie,sparingothers)\end{array}$

From Signature to Process Step

Name	Formula	Related Formulae	Variables/Constants
Signature to step	$\text{curvilinear}\leftarrow \text{handling, spin coat};\text{micro-structure}\leftarrow \text{CMP}$	$\text{amorphous}\leftarrow \text{litho, etch};\text{global}\leftarrow \text{particles}$	$\begin{array}{r}Tobinetal.:wagon-wheelstreaksfrom\\ spincoating,insufficientetchclusters;\\ DefectSourcesandClassificationpage:\\ centreandedgeringfromdepositionor\\ RTA,ringfrometch\end{array}$ $\begin{array}{r}(myreading:asignaturenarrowsthe\\ searchtoastep;commonalitythennames\\ thetool)\end{array}$
Edge signatures	$\text{EBR line crossovers, bevel etch, CMP chipping, peeling}$	$\theta \text{-sector correlation front and back}$	$\begin{array}{r}KLAandSKHynix:photo,etch,deposition,\\ cleaningandCMPedgesources;Lam:\\ asymmetricdirectionaldefectsfrom\\ warpageandanisotropicdeposition\end{array}$ $\begin{array}{r}(myreading:anglearoundthewafer,not\\ onlyradius,carriesinformation)\end{array}$
Reticle repeaters	$\bar{G}(x,y)=\frac{1}{N_f}{\sum }_{k=1}^{N_f}{G}_k(x,y)$	$\Delta Y=\frac{1}{N_{die/field}}=25\%(4\text{dies})$	$G_k:gradeimageoffieldk$ $\begin{array}{r}{N}_f:fields;AppliedMaterialsIsrael:field\\ alignmentthenaveraging,thresholdfrom\\ false-alarmrate,maskdefectprintingon\\ everydieitcovers\end{array}$ $\begin{array}{r}(myreading:averagingNfieldslowers\\ randomnoiseroughlyas\sqrt{N_f}whilea\\ repeaterkeepsitssignal)\end{array}$

Important Questions

Ques: What is spatial signature analysis, and how is it automated?

It is recognising defect patterns that point to a process problem. Tobin et al. define a signature as a unique pattern associated with a manufacturing problem, such as a handler scratch or CVD contamination. Wafer maps exist for about 10 to 20 per cent of wafers, and about 20 per cent of those are reviewed manually, about 4 per cent of wafers (computed). Their method turns a 200 $\mathrm{mm}$ map into a 512 by 512 density image of about 390 $\mu \mathrm{m}$ pixels and groups defects within about 1 to 10 $\mu \mathrm{m}$. Directional dilation then merges them into objects scored by area, elongation, compactness and proximity. A fuzzy kNN classifier reached 94 per cent expected performance across 13 classes. Reference: K. W. Tobin, S. S. Gleason, T. P. Karnowski and H. Sari-Sarraf (Lockheed Martin Energy Research), ‘Automated defect spatial signature analysis for semiconductor manufacturing process’, US Patent 5,982,920 (1999): a spatial signature as a unique defect pattern associated with a manufacturing problem such as a handler scratch or CVD contamination, wafer maps generated for about 10 to 20 per cent of wafers with about 20 per cent of sampled data reviewed manually, maps of several hundred to several thousand defects, density image split into low- and high-density parts, nearest-neighbour grouping at about 1 to 10 um then directional dilation, fuzzy constraints on area, elongation, compactness and proximity, classes Global (unclustered single events, e.g. particle contamination), Curvilinear (curvilinear and radial clusters from spinning processes), Amorphous (tight clusters from lithography or etch) and Micro-structure (linear single-pixel events from CMP micro-scratching), 512 x 512 map of a 200 mm wafer at about 390 um per pixel (fetch-tool summary); K. W. Tobin, S. S. Gleason, T. P. Karnowski (ORNL), S. L. Cohen and F. Lakhani (SEMATECH), ‘Automatic classification of spatial signatures on semiconductor wafermaps’ (about 1997): Global (ring or random uniform particles), Curvilinear (scratches and streaks, wagon-wheel streaks from spin coating), Amorphous (tight clusters, e.g. insufficient etching) and Micro-structure (CMP), pairwise fuzzy kNN classifier with hold-one-out validation, 113 examples in 13 classes, overall expected performance 94 per cent with sets from 84 to 99 per cent, Medium/Uniform 89 to 100 and Ring 80 to 98 per cent after removing problem signatures (fetch-tool summary).

Ques: How do you test whether failing die are clustered rather than random?

By comparing neighbour statistics or the variance with a random reference. Hansen et al. use join counts: BB sums, over defective circuits, the share of defective neighbours, and GG does the same for good circuits. Values far outside the distribution for an unclustered wafer flag clustering. Their flagged wafers are smoothed, transformed by arc-sine square root, standardised and thresholded into a cluster map. Bogdanov et al. give the count view: for a negative binomial, variance exceeds the mean, ${\sigma }^2=\mu +{\mu }^2/\alpha$, so $\alpha ={\mu }^2/({\sigma }^2-\mu )$. A mean of 0.5 defects per die with variance 0.75 gives $\alpha =1$ and a dispersion index of 1.5, against 1 for Poisson (computed). Reference: J. D. Friedman, M. H. Hansen, J. R. Hoyer and V. N. Nair (AT&T Bell Laboratories), ‘Method for characterizing failed circuits on semiconductor wafers’, US Patent 5,240,866 (1993): join-count statistics BB (over defective circuits, share of defective neighbours) and GG (same for good circuits) compared with their distribution for a wafer without spatial clustering, flagged wafers smoothed by weighted neighbourhood counts, arc-sine square-root transform, standardisation under the no-clustering null, normal probability integral transform and thresholding to a binary cluster map, hierarchical clustering of wafers by the number of differing circuit positions, commonality checks on shared processing history and matching to a library of known patterns (fetch-tool summary); Yu. I. Bogdanov, N. A. Bogdanova and A. V. Rudnev (Moscow Institute of Electronic Engineering), ‘Multilevel clustering fault model for IC manufacture’, arXiv:physics/0310012: Poisson Y = exp(-lambda), Murphy, Seeds and negative binomial Y = (1 + lambda0/a)^(-a) with a the cluster parameter typically 0.3 to 7 and clustering vanishing above about 4 or 5, mean a/b and variance (a/b^2)(1 + b) exceeding the mean, moment estimates a = mu^2/(sigma^2 - mu) and b = mu/(sigma^2 - mu), correlation stronger for close regions, hierarchical models predicting higher yield than Poisson, e.g. 64M complexity at p = 1e-7 giving 0.0012 (Poisson) against 0.4924 (level 1) (fetch-tool summary).

Ques: Which process step does each signature point to?

Each family narrows the search to a step. Tobin et al. link global patterns to particle contamination, curvilinear streaks to spinning processes such as a wagon-wheel pattern from spin coating, amorphous clusters to lithography or insufficient etching, and micro-structure lines to CMP micro-scratching. The Defect Sources and Classification page adds centre and edge rings from deposition or RTA non-uniformity, rings from etch and linear scratches from handling. Lam’s Kim shows that asymmetric, direction-dependent defects can come from wafer warpage during anisotropic barrier deposition. In my reading, the signature identifies the step, and Hansen et al.’s commonality check on shared processing history then identifies the tool. Reference: K. W. Tobin, S. S. Gleason, T. P. Karnowski and H. Sari-Sarraf (Lockheed Martin Energy Research), ‘Automated defect spatial signature analysis for semiconductor manufacturing process’, US Patent 5,982,920 (1999): a spatial signature as a unique defect pattern associated with a manufacturing problem such as a handler scratch or CVD contamination, wafer maps generated for about 10 to 20 per cent of wafers with about 20 per cent of sampled data reviewed manually, maps of several hundred to several thousand defects, density image split into low- and high-density parts, nearest-neighbour grouping at about 1 to 10 um then directional dilation, fuzzy constraints on area, elongation, compactness and proximity, classes Global (unclustered single events, e.g. particle contamination), Curvilinear (curvilinear and radial clusters from spinning processes), Amorphous (tight clusters from lithography or etch) and Micro-structure (linear single-pixel events from CMP micro-scratching), 512 x 512 map of a 200 mm wafer at about 390 um per pixel (fetch-tool summary); K. W. Tobin, S. S. Gleason, T. P. Karnowski (ORNL), S. L. Cohen and F. Lakhani (SEMATECH), ‘Automatic classification of spatial signatures on semiconductor wafermaps’ (about 1997): Global (ring or random uniform particles), Curvilinear (scratches and streaks, wagon-wheel streaks from spin coating), Amorphous (tight clusters, e.g. insufficient etching) and Micro-structure (CMP), pairwise fuzzy kNN classifier with hold-one-out validation, 113 examples in 13 classes, overall expected performance 94 per cent with sets from 84 to 99 per cent, Medium/Uniform 89 to 100 and Ring 80 to 98 per cent after removing problem signatures (fetch-tool summary); Defect Sources and Classification page of this vault; J. Kim (Lam Research), ‘Techniques to identify and correct asymmetric wafer map defects caused by design and process errors’, Semiconductor Engineering (22 February 2024): biased deposition or etch creating structural defects in different radial directions, warpage tilting the wafer during anisotropic TaN/Ta deposition, line orientation deciding sensitivity, 49 simulated sites with resistance from 40 430 to 40 438 ohm/sq and the far y-axis edge out of specification (fetch-tool summary); J. D. Friedman, M. H. Hansen, J. R. Hoyer and V. N. Nair (AT&T Bell Laboratories), ‘Method for characterizing failed circuits on semiconductor wafers’, US Patent 5,240,866 (1993): join-count statistics BB (over defective circuits, share of defective neighbours) and GG (same for good circuits) compared with their distribution for a wafer without spatial clustering, flagged wafers smoothed by weighted neighbourhood counts, arc-sine square-root transform, standardisation under the no-clustering null, normal probability integral transform and thresholding to a binary cluster map, hierarchical clustering of wafers by the number of differing circuit positions, commonality checks on shared processing history and matching to a library of known patterns (fetch-tool summary).

Ques: How are reticle repeaters found?

By combining every field so that only the repeating defect survives. Applied Materials Israel describe repeating defects as appearing at multiple locations, normally from a defect on the mask that prints on each die it covers. Die-to-die comparison struggles because process and mechanical variation bury them in noise. Their method aligns the mask fields, averages a grade image over all fields, and thresholds the average at a level set by the desired false-alarm rate. Repeaters keep their signal while random defects average down. In my reading, the noise falls roughly as the square root of the number of fields. The cost is severe: in a four-die field, one reticle defect removes 25 per cent of yield (Applied Materials Israel). Reference: K. Pomeranz, E. Neistein, V. Balasubramanian, M. Amzaleg and E. Bassa (Applied Materials Israel), ‘Method of detecting repeating defects and system thereof’, US Patent 10,275,872: repeating defects distributed at multiple locations, normally from a mask or reticle defect printing on each die, weakened in die-to-die comparison by process and mechanical variation, grade images averaged over mask fields after field alignment so repeaters keep their signal and random defects are reduced, threshold from the desired false-alarm rate, a four-die field where one defect costs 25 per cent yield (fetch-tool summary).

Ques: Why do edge signatures need special attention?

Because many steps leave their marks there, and edge die are a growing share of output. Kim et al. (SK Hynix and KLA) note that edge yield matters more as fabs shrink edge exclusion. They list edge sources by step: photo (edge defocus, residues, edge bead removal traces), etch (bevel etch, roughness), deposition (centricity, abnormal coating), cleaning (particles, peeling) and CMP (bevel chipping, scratches, peeling). The root cause is very often at the crossover of edge bead removal lines from successive steps. Peeling clusters at the edge correlated with front and back-side particles in specific angular regions. In my reading, an edge-ring or edge-local map should be checked by angle as well as radius. Reference: T. Kim, J. Oh, H. Yoo (SK Hynix), D. Kim and T. Torelli (KLA-Tencor), ‘Criticality of wafer edge inspection and metrology data to all surface defectivity root cause and yield analysis’, ASMC 2016 (Semiconductor Engineering, 2018): edge yield mattering as edge exclusion shrinks, edge sources by step (photo: edge defocus, residues, EBR traces; etch: bevel etch, roughness; deposition: centricity, abnormal coating; cleaning: particles, peeling; CMP: bevel chipping, scratches, peeling), root cause often at crossovers of EBR lines from successive steps, edge peeling clusters correlated with front and back-side particles in specific theta regions, binning accuracy above 90 per cent (fetch-tool summary).

Ques: What fraction of WM-811K wafers is patterned, and which figure is right?

Both 3.1 and 14.8 per cent are right; they use different denominators. Kim and Kim state that 25 519 maps carry a defect pattern, 3.1 per cent, out of 811 457 maps. The Defect Sources and Classification page, from Bao et al., gives 14.8 per cent of the 172 950 labelled maps. Dividing 25 519 by 811 457 gives 3.14 per cent and by 172 950 gives 14.75 per cent (computed). The labelled-map figure is the more meaningful rate, since the 638 507 unlabelled maps were never classed (my reading). Kim and Kim also note that Edge-Loc, Loc and Scratch labels depend on engineers’ judgement, which limits classifier accuracy. Their polar-coordinate CNNs reached 91.3 to 94 per cent. Reference: M. H. Kim and T. S. Kim, ‘Development of a wafer defect pattern classifier using polar coordinate system transformed inputs and convolutional neural networks’, Electronics 13(7), 1360 (2024): patterned defects mainly from controllable process factors and random noise often from poor process-environment management, Center (middle), Donut (ring with few defects at centre and edge), Edge-Ring (along the edge), Edge-Loc, Loc and Scratch at varying locations with subjective labelling, WM-811K of 811 457 maps with 172 950 labelled and 25 519 (3.1 per cent) patterned, 1266 wafers of varying die size, polar 7 x 7 region counts with CNN at 91.3 per cent and a tree of binary CNNs at 94 per cent on 26 x 26 maps (fetch-tool summary); Defect Sources and Classification page of this vault.

Ques: What cluster parameter is typical, and which value is more likely?

About 1.5 to 2 for modern memory and logic. MIT’s 2.830J lecture gives typical values of 1.5 to 2 for memory and microprocessors and notes that large values approach Poisson yield and small values Seeds yield. Bogdanov et al. give a wider range of 0.3 to 7, with clustering effectively vanishing above about 4 or 5. The two agree: MIT’s range lies inside Bogdanov’s and refers to specific product classes. The 1.5 to 2 value is therefore more likely for a typical estimate, while the wider range covers other processes (my reading). Clustering matters greatly: at 64M complexity Bogdanov et al. compute yield of 0.0012 for Poisson against 0.4924 with clustering. Reference: MIT OpenCourseWare 2.830J Control of Manufacturing Processes, Lecture 10 ‘Yield modeling’ (2008): negative binomial from a gamma defect density, large alpha approaching Poisson and small alpha approaching Seeds, alpha to be determined empirically with typical memory and microprocessor values of 1.5 to 2 (fetch-tool summary); Yu. I. Bogdanov, N. A. Bogdanova and A. V. Rudnev (Moscow Institute of Electronic Engineering), ‘Multilevel clustering fault model for IC manufacture’, arXiv:physics/0310012: Poisson Y = exp(-lambda), Murphy, Seeds and negative binomial Y = (1 + lambda0/a)^(-a) with a the cluster parameter typically 0.3 to 7 and clustering vanishing above about 4 or 5, mean a/b and variance (a/b^2)(1 + b) exceeding the mean, moment estimates a = mu^2/(sigma^2 - mu) and b = mu/(sigma^2 - mu), correlation stronger for close regions, hierarchical models predicting higher yield than Poisson, e.g. 64M complexity at p = 1e-7 giving 0.0012 (Poisson) against 0.4924 (level 1) (fetch-tool summary); Yield Models and Critical Area page of this vault.

References

1. K. W. Tobin, S. S. Gleason, T. P. Karnowski and H. Sari-Sarraf, “Automated defect spatial signature analysis for semiconductor manufacturing process,” US Patent 5,982,920, 1999. Available: https://patents.google.com/patent/US5982920
2. K. W. Tobin, S. S. Gleason, T. P. Karnowski, S. L. Cohen and F. Lakhani, “Automatic classification of spatial signatures on semiconductor wafermaps,” ORNL and SEMATECH. Available: https://core.ac.uk/download/71171406.pdf
3. J. D. Friedman, M. H. Hansen, J. R. Hoyer and V. N. Nair, “Method for characterizing failed circuits on semiconductor wafers,” US Patent 5,240,866, AT&T Bell Laboratories, 1993. Available: https://uspto.report/patent/grant/5240866
4. Yu. I. Bogdanov, N. A. Bogdanova and A. V. Rudnev, “Multilevel clustering fault model for IC manufacture,” arXiv:physics/0310012. Available: https://arxiv.org/pdf/physics/0310012
5. MIT OpenCourseWare 2.830J, “Lecture 10: yield modeling,” Control of Manufacturing Processes, Spring 2008. Available: https://www.ocw.mit.edu/courses/2-830j-control-of-manufacturing-processes-sma-6303-spring-2008/4aff1e21de13870355ef44dbe71f45c6_lecture10.pdf
6. K. Pomeranz, E. Neistein, V. Balasubramanian, M. Amzaleg and E. Bassa, “Method of detecting repeating defects and system thereof,” US Patent 10,275,872, Applied Materials Israel. Available: https://patents.google.com/patent/US10275872
7. M. H. Kim and T. S. Kim, “Development of a wafer defect pattern classifier using polar coordinate system transformed inputs and convolutional neural networks,” Electronics, vol. 13, p. 1360, 2024, doi:10.3390/electronics13071360. Available: https://mdpi.com/2079-9292/13/7/1360
8. T. Kim, J. Oh, H. Yoo, D. Kim and T. Torelli, “Criticality of wafer edge inspection and metrology data to all surface defectivity root cause and yield analysis,” ASMC 2016, Semiconductor Engineering. Available: https://semiengineering.com/criticality-of-wafer-edge-inspection-and-metrology-data-to-all-surface-defectivity-root-cause-and-yield-analysis
9. J. Kim, “Techniques to identify and correct asymmetric wafer map defects caused by design and process errors,” Semiconductor Engineering, 22 February 2024. Available: https://semiengineering.com/techniques-to-identify-and-correct-asymmetric-wafer-map-defects-caused-by-design-and-process-errors
10. Defect Sources and Classification page of this vault.
11. Yield Models and Critical Area page of this vault.

Related pages in this vault: Defect Sources and Classification, Yield Models and Critical Area, Defect Detection Fundamentals, Patterned-Wafer Optical Inspection, CMP Polisher, Defect Inspection Workflow and Sampling Plans, Defect SPC and Excursion Monitoring, Automatic Defect Classification and Machine Learning, Defect Data Handling with Python and Perl.