1. Theory

Definition: A defect inspection plan decides which layers, lots and wafers to inspect, which detected defects to review and classify, and when results trigger action (Hall et al.; Bean).
Excursions: Low-frequency, high-impact events, with limits set on defect count, density, characteristics or spatial pattern (Hall et al.).
Material at risk: Lots processed since the last known-good inspection are at risk, so risk rises with the inspection interval (Hall et al.; Bean).
Detection chain: An excursion is caught only if the material is inspected, the defect is detected and its source is recognised (Bean).

2. Working Principle

Loop: Inspect, classify by ADC or review, bin, chart against limits; out-of-control lots are isolated, contained, root-caused, fixed and verified (Hall et al.).
Recipe: Care areas from design data focus sensitivity on critical regions and separate quiet from noisy regions (Teagle et al.).
Sampling: Skip-lot coverage such as 1 lot in 10, a fixed number of wafers per lot, and allocation across layers by risk (Bean; Hall et al.).
Review sampling: Review slots allocated to size bins in proportion to their predicted yield loss (Simmons).
Root cause: Similar wafer maps are grouped and checked for shared processing history (Hansen et al.; Wafer-Map Spatial Signature Analysis page).

3. Applications

Excursion monitoring: Layer-by-layer charts of defect counts and classes (Hall et al.).
Inspection capacity planning: Balancing wafers inspected against material at risk (Bean).
Yield learning: Defect Paretos by class and location in critical and non-critical lines (Teagle et al.).

Control Loop and Detection

Name	Formula	Related Formulae	Variables/Constants
Defect control loop	$inspect \to ADC/review \to bin \to SPC limit$	$OOC \to isolate, contain, root-cause, fix, verify$	$H a l l e t a l . : A D C f in e bin s s t or e d in a d e f ec t d a t aba se, e x c u r s i o n l imi t s o n co u n t, d e n s i t y, c ha r a c t er i s t i cs or s p a t ia l p a tt er n; B e an : c l a ss i f i e d r e v i e w s t r a c k s hi f t s b y d e f ec t t y p e$ $(m y r e a d in g : e v er y in s p ec t i o n r es u l t e n d s e i t h er in a c ha r t p o in t or in an a c t i o n)$
Detection chain	$P_{d e t ec t} = P_{in s p ec t e d} P_{see n} P_{r eco g ni se d}$	$monitor effective within 2 to 3 modules, ineffective near 10$	$B e an : t h e ma t er ia l m u s t b e in s p ec t e d, t h e d e f ec t d e t ec t e d an d i t s so u r ce r eco g ni se d; D e f ec t D e t ec t i o n F u n d am e n t a l s p a g e f or c a pt u r e r a t e$ $(m y r e a d in g : t h e p r o d u c t f or m r es t a t es B e a n^{'} s t h r ee r e q u i r e d e v e n t s)$
Root-cause commonality	$d (w_{1}, w_{2}) = \sum_{d i es} [s_{1} \neq = s_{2}]$	$shared history: batch bath, serial tool, chamber position$	$H an se n e t a l . : hi er a r c hi c a l c l u s t er in g o f w a f er ma p s b y d i f f er in g p os i t i o n s, co mm o na l i t y c h ec k s, l ib r a r y o f k n o w n p a tt er n s; W a f er - M a p S p a t ia l S i g na t u r e A na l y s i s p a g e$ $(m y r e a d in g : s i s t h e p a ss or f ai l s t a t e o f e a c h d i e)$

Lot, Wafer and Layer Sampling

Name	Formula	Related Formulae	Variables/Constants
Skip-lot coverage	$f_{l o t} = \frac{15}{150} = 0.1$	$P_{c a ug h t} = 1 - (1 - f_{l o t})^{k}$	$B e an : 15 t a g g e d l o t s o f 150 p er w ee k, a l l w a f er s o f t a g g e d l o t s in s p ec t e d, ab o u t 270 r i s in g t o 500 w a f er in s p ec t i o n s p er w ee k; T o bin e t a l . : ma p s f or 10 t o 20 p er ce n t o f w a f er s$ $(co m p u t e d, a ss u min g r an d o m t a g g in g : an e x c u r s i o n l a s t in g 5 l o t s i s c a ug h t w i t h 0.41 p r o babi l i t y, 20 l o t s w i t h 0.88)$
Cost of risk	$C_{R} = \frac{1}{2} \sum_{i} ⟨ A R L_{i} ⟩ C_{i} λ_{i} I_{i}$	$E [C] = \frac{C _{0}}{λ} + C_{1} (Δ) [I (A R L) - τ + γ + T]$	$λ_{i} : e x c u r s i o n r a t e$ $I_{i} : in s p ec t i o n in t er v a l$ $C_{i} : cos t p er e x c u r s i o n; H a l l e t a l . : ab o u t 10 p er ce n t hi g h f or l a r g e s hi f t s, f a l se a l a r m s an d f i x e d cos t s e x c l u d e d$ $(m y r e a d in g : r i s k g r o w s w i t h t h e in t er v a l b e tw ee n in s p ec t i o n s an d w i t h c ha r t s l ug g i s hn ess)$
Optimal allocation	$n_{i} = \frac{n _{t}}{n _{0}} \frac{λ _{i} ⟨ A R L _{i} ⟩ C _{i}}{\sum _{j} λ _{j} ⟨ A R L _{j} ⟩ C _{j}}$	$L_{e x p} : 62.7 (none), 26.2 (current), 20.6 (optimum) wafers$	$H a l l e t a l . : s q u a r e - r oo t a l l oc a t i o n a cr oss l a y er s; B e an : ma t er ia l a t r i s k a s M A R - W I P pl u s M A R - P L A N$ $(co m p u t e d : a l a y er w i t h f o u r t im es t h e r i s k p r o d u c t g e t s tw i ce t h e s am pl es; in s p ec t i o n c u t l oss b y 58 p er ce n t an d t h e o pt im u m b y a f u r t h er 21 p er ce n t)$

Recipe and Review Sampling

Name	Formula	Related Formulae	Variables/Constants
Care areas	$design \to care areas \to recipe$	$quiet dense regions \neq = noisy sparse regions$	$T e a g l e e t a l . : t a r g e t e d c a r e a r e a s r ai se se n s i t i v i t y w h er e D O I l i v e, s ma l l er co m p a r i so n a r e a s, n u i s an ce f r o m C D v a r ia t i o n an d co l o u r; D e f ec t D e t ec t i o n F u n d am e n t a l s p a g e f or t h r es h o l d s$ $(m y r e a d in g : a se p a r a t e t h r es h o l d p er r e g i o n l e t s q u i e t a r e a s r u n h o t w i t h o u t f l oo d in g n u i s an ce)$
Yield-weighted review sampling	$D_{i} = 1 - \frac{W Y L _{i}}{W Y L}, P_{i} = \frac{D _{i}}{\sum D}$	$S_{i} = P_{i} S_{T}, W Y L = \sum D Y L$	$S imm o n s : s i x s i z e bin s, w e i g h t s f r o m s i z e, p a r t g eo m e t r y an d d i e l oc a t i o n, r an d o m se l ec t i o n w i t hin bin s, 12 d e f ec t s p er w a f er e x am pl e, S_{T} se t b y r e v i e w c a p a c i t y$ $(co m p u t e d : bin s co n t r ib u t in g 0.5, 0.3 an d 0.2 o f t h e l oss g e t 6, 3.6 an d 2.4 o f 12 r e v i e w s)$
Review and relocation	$f_{r e v i e w} = f (ADC fraction)$	$manual review of a fraction of detections$	$H a l l e t a l . : r e v i e w f r a c t i o n f p er l a y er; B e an : man u a l r e v i e w f r a c t i o n; T o bin e t a l . : ab o u t 20 p er ce n t o f s am pl e d ma p s r e v i e w e d; E - B e am I n s p ec t i o n an d D e f ec t R e v i e w p a g e f or r e l oc a t i o n$ $(m y r e a d in g : r e v i e w i s t h e na r r o w es t p o in t o f t h e l oo p, so s am pl in g d ec i d es w ha t i s l e a r n t)$

Important Questions

Ques: What is the inspect, review, classify, root-cause loop?

It is the path from a defect count to a corrective action. Hall et al. describe in-line inspections at standard layers whose results go to automatic defect classification (ADC), are binned and stored, and are charted against excursion limits on count, density, characteristics or spatial pattern. An out-of-control lot is isolated and contained, its root cause found and fixed, and the fix verified before monitoring resumes. Bean adds that reviewed defects are classified to track shifts by defect type. For root cause, Hansen et al. group wafers with similar maps and check them for shared processing history, such as a batch bath or one chamber position. The Wafer-Map Spatial Signature Analysis page covers the spatial step. Reference: G. D. R. Hall, R. Young, M. Dunne and M. Muro (ON Semiconductor, Defect and Device Yield Engineering), ‘A quality-cost model of in-line inspections for excursion detection and reduction’ (venue and year not stated; file name indicates ASMC 2008): wafers sampled at standard inspection layers, n wafers per lot per inspection and ADC review fraction f, fixed n0 wafers per lot for all layers as the base plan, excursions as low-frequency high-impact events with limits on count, density, characteristics or spatial pattern, at-risk material as uninspected lots since the last known-good inspection, inspection results fed to ADC, binned and stored, out-of-control lots isolated, contained, root-caused, fixed and verified, expected cost E[C] = C0/lambda + C1(Delta)[I(ARL) - tau + gamma + T], cost of risk per layer about (1/2) C_i lambda_i I_i ARL_i, total CR = (1/2) sum ARL_i C_i lambda_i I_i, optimal allocation n_i = (n_t/n_0) sqrt(lambda_i ARL_i C_i)/sum_j sqrt(lambda_j ARL_j C_j), approximation about 10 per cent high for large shifts, false-alarm and fixed costs excluded (fetch-tool summary); J. W. Bean, ‘Variation reduction in a wafer fabrication line through inspection optimization’, MIT SM thesis (1997): KLA and Tencor monitors with Tencor after film deposition, skip-lot coverage of 15 tagged lots out of 150 per week (1:10), complete inspection of each wafer in tagged lots, two-phase excursion check with corrective action when more than one excursionary wafer is found or one in phase one and another in phase two, manual review of a fraction of detected defects classified to track trends by type, detection needing the material inspected, the defect detected and its source recognised, monitors highly effective within two or three modules of the source and ineffective about 10 modules away, material at risk as MAR-WIP plus MAR-PLAN, expected loss 26.2 wafers under the current plan, 62.7 with no inspection and 20.6 at the optimum, about 270 rising to about 500 wafer inspections per week (fetch-tool summary); J. D. Friedman, M. H. Hansen, J. R. Hoyer and V. N. Nair, ‘Method for characterizing failed circuits on semiconductor wafers’, US Patent 5,240,866 (1993): wafers grouped by map similarity and checked for shared processing history such as batch immersion, serial processing or the same part of a machine, then matched to a library of known pattern causes (fetch-tool summary); Wafer-Map Spatial Signature Analysis page of this vault.

Ques: Why does catching an excursion need more than a sensitive tool?

Because three things must all happen. Bean states that the excursionary material must be inspected, the defect must be detected by the monitor and its source must be recognised. A monitor is highly effective within two or three modules of the source but ineffective about 10 modules away, because later layers bury or change the defect. Tool sensitivity governs only the middle step, the capture rate of the Defect Detection Fundamentals page. Sampling governs the first, and review and classification the third. In my reading, the probabilities multiply, so a perfect detector on a rarely inspected layer still misses most excursions. Hall et al. accordingly count uninspected lots since the last good inspection as material at risk. Reference: J. W. Bean, ‘Variation reduction in a wafer fabrication line through inspection optimization’, MIT SM thesis (1997): KLA and Tencor monitors with Tencor after film deposition, skip-lot coverage of 15 tagged lots out of 150 per week (1:10), complete inspection of each wafer in tagged lots, two-phase excursion check with corrective action when more than one excursionary wafer is found or one in phase one and another in phase two, manual review of a fraction of detected defects classified to track trends by type, detection needing the material inspected, the defect detected and its source recognised, monitors highly effective within two or three modules of the source and ineffective about 10 modules away, material at risk as MAR-WIP plus MAR-PLAN, expected loss 26.2 wafers under the current plan, 62.7 with no inspection and 20.6 at the optimum, about 270 rising to about 500 wafer inspections per week (fetch-tool summary); Defect Detection Fundamentals page of this vault; G. D. R. Hall, R. Young, M. Dunne and M. Muro (ON Semiconductor, Defect and Device Yield Engineering), ‘A quality-cost model of in-line inspections for excursion detection and reduction’ (venue and year not stated; file name indicates ASMC 2008): wafers sampled at standard inspection layers, n wafers per lot per inspection and ADC review fraction f, fixed n0 wafers per lot for all layers as the base plan, excursions as low-frequency high-impact events with limits on count, density, characteristics or spatial pattern, at-risk material as uninspected lots since the last known-good inspection, inspection results fed to ADC, binned and stored, out-of-control lots isolated, contained, root-caused, fixed and verified, expected cost E[C] = C0/lambda + C1(Delta)[I(ARL) - tau + gamma + T], cost of risk per layer about (1/2) C_i lambda_i I_i ARL_i, total CR = (1/2) sum ARL_i C_i lambda_i I_i, optimal allocation n_i = (n_t/n_0) sqrt(lambda_i ARL_i C_i)/sum_j sqrt(lambda_j ARL_j C_j), approximation about 10 per cent high for large shifts, false-alarm and fixed costs excluded (fetch-tool summary).

Ques: How do care areas improve an inspection recipe?

By concentrating sensitivity where defects of interest occur. Teagle et al. (GLOBALFOUNDRIES and KLA-Tencor) describe generating care areas from the design file in a secure environment and transferring them to the tool to build the recipe. In logic, detection of defects of interest is limited by strong wafer noise. Targeted care areas raise sensitivity in critical regions, and smaller comparison areas between candidate and reference die improve detection. The approach separates dense, quiet regions from noisy, sparse ones, and the resulting Pareto distinguishes defects on critical and non-critical lines. Nuisance sources include CD variation and colour. In my reading, separate thresholds per region let quiet areas run at high sensitivity without flooding the nuisance rate. Reference: R. Teagle, H. Nguyen, R. Buengener, P. Lin (GLOBALFOUNDRIES), A. Jain, S. Kini, R. Lakhawat and R. Sanapala (KLA-Tencor), ‘Advanced broadband optical inspection on complex logic structures using NanoPoint at 28 nm design nodes’ (NIST document): design file used to generate care areas transferred to the inspection recipe, DOI detection in logic limited by strong wafer noise, targeted care areas raising sensitivity in critical regions, defects reported by comparing candidate and reference die with smaller comparison areas improving detection, separating dense quiet from noisy sparse regions, nuisance categories such as CD variation and colour, defect Pareto by critical and non-critical lines (fetch-tool summary); Defect Detection Fundamentals page of this vault.

Ques: Is it better to inspect every wafer of a few lots or a few wafers of many lots?

Spreading the sample over more lots is more likely to be better. Bean’s line inspected every wafer in 15 of 150 lots per week, a 1:10 skip-lot coverage. Tobin et al. describe maps for about 10 to 20 per cent of wafers, and Hall et al. fix a number of wafers per lot as their base plan. Assuming random tagging, an excursion lasting 5 lots is caught with probability 0.41 at 1:10 coverage, and one lasting 20 lots with 0.88 (computed). If an excursion affects whole lots, seeing more lots shortens the time to detection, while extra wafers from one lot add little (my reading). Bean’s two-phase wafer check shows that a few wafers can still confirm an excursion. Reference: J. W. Bean, ‘Variation reduction in a wafer fabrication line through inspection optimization’, MIT SM thesis (1997): KLA and Tencor monitors with Tencor after film deposition, skip-lot coverage of 15 tagged lots out of 150 per week (1:10), complete inspection of each wafer in tagged lots, two-phase excursion check with corrective action when more than one excursionary wafer is found or one in phase one and another in phase two, manual review of a fraction of detected defects classified to track trends by type, detection needing the material inspected, the defect detected and its source recognised, monitors highly effective within two or three modules of the source and ineffective about 10 modules away, material at risk as MAR-WIP plus MAR-PLAN, expected loss 26.2 wafers under the current plan, 62.7 with no inspection and 20.6 at the optimum, about 270 rising to about 500 wafer inspections per week (fetch-tool summary); K. W. Tobin, S. S. Gleason, T. P. Karnowski and H. Sari-Sarraf, ‘Automated defect spatial signature analysis for semiconductor manufacturing process’, US Patent 5,982,920 (1999): wafer maps for about 10 to 20 per cent of wafers, about 20 per cent of sampled data reviewed manually (fetch-tool summary); G. D. R. Hall, R. Young, M. Dunne and M. Muro (ON Semiconductor, Defect and Device Yield Engineering), ‘A quality-cost model of in-line inspections for excursion detection and reduction’ (venue and year not stated; file name indicates ASMC 2008): wafers sampled at standard inspection layers, n wafers per lot per inspection and ADC review fraction f, fixed n0 wafers per lot for all layers as the base plan, excursions as low-frequency high-impact events with limits on count, density, characteristics or spatial pattern, at-risk material as uninspected lots since the last known-good inspection, inspection results fed to ADC, binned and stored, out-of-control lots isolated, contained, root-caused, fixed and verified, expected cost E[C] = C0/lambda + C1(Delta)[I(ARL) - tau + gamma + T], cost of risk per layer about (1/2) C_i lambda_i I_i ARL_i, total CR = (1/2) sum ARL_i C_i lambda_i I_i, optimal allocation n_i = (n_t/n_0) sqrt(lambda_i ARL_i C_i)/sum_j sqrt(lambda_j ARL_j C_j), approximation about 10 per cent high for large shifts, false-alarm and fixed costs excluded (fetch-tool summary).

Ques: How should inspection capacity be split between layers?

In proportion to the square root of each layer’s risk. Hall et al. model the cost of risk as $C_{R} = \frac{1}{2} \sum ⟨ A R L_{i} ⟩ C_{i} λ_{i} I_{i}$ . Here $λ_{i}$ is the excursion rate, $C_{i}$ the cost per excursion, $I_{i}$ the inspection interval and $A R L_{i}$ the chart’s average run length. Minimising it gives wafers per lot proportional to $λ_{i} ⟨ A R L_{i} ⟩ C_{i}$ , so a layer with four times the risk product gets twice the samples (computed). Bean’s case shows the value of optimising: expected loss of 62.7 wafers with no inspection, 26.2 under the plan and 20.6 at the optimum. That is a 58 per cent cut, then a further 21 per cent (computed). Reference: G. D. R. Hall, R. Young, M. Dunne and M. Muro (ON Semiconductor, Defect and Device Yield Engineering), ‘A quality-cost model of in-line inspections for excursion detection and reduction’ (venue and year not stated; file name indicates ASMC 2008): wafers sampled at standard inspection layers, n wafers per lot per inspection and ADC review fraction f, fixed n0 wafers per lot for all layers as the base plan, excursions as low-frequency high-impact events with limits on count, density, characteristics or spatial pattern, at-risk material as uninspected lots since the last known-good inspection, inspection results fed to ADC, binned and stored, out-of-control lots isolated, contained, root-caused, fixed and verified, expected cost E[C] = C0/lambda + C1(Delta)[I(ARL) - tau + gamma + T], cost of risk per layer about (1/2) C_i lambda_i I_i ARL_i, total CR = (1/2) sum ARL_i C_i lambda_i I_i, optimal allocation n_i = (n_t/n_0) sqrt(lambda_i ARL_i C_i)/sum_j sqrt(lambda_j ARL_j C_j), approximation about 10 per cent high for large shifts, false-alarm and fixed costs excluded (fetch-tool summary); J. W. Bean, ‘Variation reduction in a wafer fabrication line through inspection optimization’, MIT SM thesis (1997): KLA and Tencor monitors with Tencor after film deposition, skip-lot coverage of 15 tagged lots out of 150 per week (1:10), complete inspection of each wafer in tagged lots, two-phase excursion check with corrective action when more than one excursionary wafer is found or one in phase one and another in phase two, manual review of a fraction of detected defects classified to track trends by type, detection needing the material inspected, the defect detected and its source recognised, monitors highly effective within two or three modules of the source and ineffective about 10 modules away, material at risk as MAR-WIP plus MAR-PLAN, expected loss 26.2 wafers under the current plan, 62.7 with no inspection and 20.6 at the optimum, about 270 rising to about 500 wafer inspections per week (fetch-tool summary).

Ques: Which defects should be sent to review?

Those that carry the most predicted yield loss. Simmons (Micron) sorts defects into six size bins, from below 0.5 to above 8 square $μ m$ . Each defect is weighted by size, part geometry and die location to give a die yield loss between 0 and 1, summed to a wafer yield loss. Removing each bin in turn gives its contribution $D_{i} = 1 - W Y L_{i} / W Y L$ , and review slots are shared as $S_{i} = P_{i} S_{T}$ with random picks within bins. In the example, 12 defects per wafer are reviewed. Bins contributing 0.5, 0.3 and 0.2 of the loss would get 6, 3.6 and 2.4 of those 12 (computed). Review capacity sets $S_{T}$ , and relocation follows the E-Beam Inspection and Defect Review page. Reference: S. J. Simmons (Micron Technology), ‘Yield based, in-line defect sampling method’, US Patent 6,265,232 (2001): defects sorted into six size bins (0 to 0.5, 0.5 to 1, 1 to 2, 2 to 4, 4 to 8 and above 8 square um), weighted by size, part-type geometry and die location, die yield loss DYL between 0 and 1 summed to wafer yield loss WYL, bin contribution D_i = 1 - WYL_i/WYL with bin i excluded, share P_i = D_i/sum D, samples S_i = P_i S_T with random selection within bins and an optional per-die limit, S_T set by review time and resources, 12 defects per wafer in the example (fetch-tool summary); E-Beam Inspection and Defect Review page of this vault.

References

G. D. R. Hall, R. Young, M. Dunne and M. Muro, “A quality-cost model of in-line inspections for excursion detection and reduction,” ON Semiconductor (file name indicates ASMC 2008). Available: https://www.onsemi.com/site/pdf/Hall_Session8_ASMC_MS_2008.pdf
J. W. Bean, “Variation reduction in a wafer fabrication line through inspection optimization,” SM thesis, Massachusetts Institute of Technology, 1997. Available: https://dspace.mit.edu/bitstream/1721.1/43446/2/37863465-MIT.pdf
S. J. Simmons, “Yield based, in-line defect sampling method,” US Patent 6,265,232, Micron Technology, 2001. Available: https://patents.google.com/patent/US6265232
R. Teagle, H. Nguyen, R. Buengener, P. Lin, A. Jain, S. Kini, R. Lakhawat and R. Sanapala, “Advanced broadband optical inspection on complex logic structures using NanoPoint at 28 nm design nodes,” GLOBALFOUNDRIES and KLA-Tencor. Available: https://www.nist.gov/document/40teaglepdf
K. W. Tobin, S. S. Gleason, T. P. Karnowski and H. Sari-Sarraf, “Automated defect spatial signature analysis for semiconductor manufacturing process,” US Patent 5,982,920, 1999. Available: https://patents.google.com/patent/US5982920
J. D. Friedman, M. H. Hansen, J. R. Hoyer and V. N. Nair, “Method for characterizing failed circuits on semiconductor wafers,” US Patent 5,240,866, AT&T Bell Laboratories, 1993. Available: https://uspto.report/patent/grant/5240866
Defect Detection Fundamentals page of this vault.
E-Beam Inspection and Defect Review page of this vault.
Wafer-Map Spatial Signature Analysis page of this vault.

Quartz 5

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Defect Inspection Workflow and Sampling Plans