1. Theory

  • Definition: Parameter extraction determines the values of compact-model parameters from measured current-voltage, capacitance-voltage and RF data so that the model reproduces the device (Silvaco; Ortiz-Conde et al. 2002).
  • Direct methods: Closed-form procedures extract individual quantities, such as threshold voltage, mobility, series resistance and effective length, from simple plots of measured curves (Ortiz-Conde et al. 2000, 2002 and 2013; Liao et al.; Trevisoli et al.).
  • Optimization: Full model cards are then fitted by numerical optimization in a fixed sequence, each step adjusting only the parameters that control one physical effect on the devices that show it most clearly (Silvaco).
  • Definitions matter: Threshold voltage has no unique definition, so different methods give different values on the same device; consistency between extraction and model definition is essential (Ortiz-Conde et al. 2002 and 2013; computed).

2. Working Principle

  • Isolation of effects: Large devices remove short- and narrow-channel effects, low drain bias removes saturation, and zero body bias removes body effect, so each step faces few unknowns (Silvaco; background knowledge).
  • Elimination of parasitics: Combinations such as cancel mobility degradation and series resistance to first order (Liao et al.; background knowledge for the cancellation).
  • Geometry arrays: Comparing devices of different lengths separates channel resistance, which scales with length, from series resistance, which does not (Ortiz-Conde et al. 2000; background knowledge).
  • Iteration: Global fits are checked against all geometries and the sequence is repeated until the errors are acceptable (Silvaco).

3. Applications

  • Foundry model cards: Geometry-scalable BSIM, PSP and similar cards for process design kits (Silvaco; BSIM3 and BSIM4 page).
  • Process monitoring: Threshold voltage, mobility and series resistance tracked on test structures (Ortiz-Conde et al. 2013; Trevisoli et al.).
  • New devices: Extraction on nanowires, FinFETs and two-dimensional-material transistors (Trevisoli et al.; Liao et al.).
  • Hand-design models: Few-parameter ACM or EKV extraction for analog sizing (Coitinho et al.; EKV page).

Threshold Voltage Extraction

NameFormulaRelated FormulaeVariables/Constants
Maximum-transconductance linear extrapolation




Constant-current and second-derivative methods
ACM inversion-level definition of threshold






Mobility, Series Resistance and Length

NameFormulaRelated FormulaeVariables/Constants
Y-function





Series resistance from the Y-function
Channel-resistance (Terada-Muta) method



Extraction Strategy

NameFormulaRelated FormulaeVariables/Constants
Extraction sequence for a scalable model


Datasheet extraction of discrete devices



Important Questions

Ques: Why do different threshold-extraction methods give different values?

Because threshold is a definition, not a sharp physical event. Ortiz-Conde et al. review 11 linear-region methods, two saturation methods and one for thin-film devices, and their 2013 update uses 2-D simulation to show how series resistance biases them. On a synthetic device with a true of 0.400 , mobility attenuation and a subthreshold factor of 1.3, maximum- extrapolation gives 0.358 , the second-derivative peak 0.395 , a constant current of 100 per square 0.319 and the Y-function 0.400 (computed). The 81 spread is larger than typical process variations. The rule is to use the method that matches the model’s own threshold definition and to report it with the value. Reference: A. Ortiz-Conde, F. J. Garcia Sanchez, J. J. Liou, A. Cerdeira, M. Estrada and Y. Yue, ‘A review of recent MOSFET threshold voltage extraction methods’, Microelectronics Reliability 42(4-5), 583-596 (2002), doi:10.1016/s0026-2714(02)00027-6 (abstract only) (fetch-tool summary); A. Ortiz-Conde, F. J. Garcia-Sanchez, J. Muci, A. Teran Barrios and J. J. Liou, ‘Revisiting MOSFET threshold voltage extraction methods’, Microelectronics Reliability 53(1), 90-104 (2013), doi:10.1016/j.microrel.2012.09.015 (abstract only) (fetch-tool summary).

Ques: How does the Y-function remove mobility degradation and series resistance?

By dividing them out. With the linear-region current , the transconductance carries the same denominator squared, so is a straight line whose slope gives and whose intercept gives (background knowledge, as written by Liao et al.). The attenuation factor then follows from , and since series resistance adds to , (background knowledge). On a synthetic device the fit returned , and , all exact to (computed). It fails when second-order degradation or subthreshold conduction matters, so the fit window must lie in strong inversion; Trevisoli et al. add second-order degradation for this reason. Reference: F. Liao et al. (18 authors), ‘MoS2 Dual-gate Transistors with Electrostatically Doped Contacts’, arXiv:1912.07885, Supplementary Section 3 (fetch-tool summary); R. Trevisoli, R. T. Doria, M. de Souza, S. Barraud, M. Vinet, M. Casse, G. Reimbold, O. Faynot, G. Ghibaudo and M. A. Pavanello, ‘A New Method for Series Resistance Extraction of Nanometer MOSFETs’, IEEE Transactions on Electron Devices (2017) (abstract only, CEA-Leti listing) (fetch-tool summary).

Ques: Is the Y-function prefactor the square root of beta VD or of 2 mu0 Cox VD W/L?

The standard form is with . Liao et al. write and . From the linear current , Y must equal , and series resistance must add to (background knowledge), so their factor of 2 inside the root would overstate the mobility by a factor of 2 (computed) unless their current is defined differently. Their factor of 4 matches only if , which is not the usual two-contact sum (computed). The textbook form is more likely correct, and the Liao factors are probably a convention of their device model or a typesetting slip (my reading). Reference: F. Liao et al. (18 authors), ‘MoS2 Dual-gate Transistors with Electrostatically Doped Contacts’, arXiv:1912.07885, Supplementary Section 3 (fetch-tool summary).

Ques: How reliable is the Y-function for series resistance?

Good for silicon devices, less so for some new materials. Trevisoli et al. extend the method to ultra-scaled MOSFETs, extracting series resistance from a plot of total resistance against the inverse of the Y-function from a single I-V curve, including first- and second-order mobility degradation, and validate it by simulation and on silicon nanowires and FinFETs; using several lengths reveals how much mobility degradation biases the result. Liao et al., working on MoS2 transistors whose contact resistance falls from 190 to 14 with side-gate bias, found contact resistances from rational-function fitting more reasonable than from the Y-function, since the method assumes negligible and a simple mobility law. The Y-function is therefore most trustworthy where its current model holds, as in silicon strong inversion (my reading). Reference: R. Trevisoli, R. T. Doria, M. de Souza, S. Barraud, M. Vinet, M. Casse, G. Reimbold, O. Faynot, G. Ghibaudo and M. A. Pavanello, ‘A New Method for Series Resistance Extraction of Nanometer MOSFETs’, IEEE Transactions on Electron Devices (2017) (abstract only, CEA-Leti listing) (fetch-tool summary); F. Liao et al. (18 authors), ‘MoS2 Dual-gate Transistors with Electrostatically Doped Contacts’, arXiv:1912.07885, Supplementary Section 3 (fetch-tool summary).

Ques: In what order should BSIM3 parameters be extracted?

From the simplest device to the most complex, one effect at a time. Silvaco’s BSIM3v3 example uses nine steps: a large device in the linear region for VTH0, U0, UA, UB, K1, K2, UC, NFACTOR and VOFF; a length array for LINT, DVT0, DVT1, NLX and RDSW; a width array for WINT, K3, W0 and K3B; small devices for binning; saturation curves for A0, AGS, VSAT, PCLM, PDIBLC1, ETA0 and PVAG; back-bias curves for KETA, ETAB and PDIBLCB; and three temperature steps for KT1, KT2, UTE, UA1, UB1, UC1, PRT and AT. Multiple sizes are needed for a scalable model, and steps one to four are repeated until all data fit. Extracting saturation parameters before threshold and mobility would let them absorb errors from the earlier physics (background knowledge). Reference: Silvaco, ‘opt_ex09: BSIM3 MOSFET Model Extraction’, UTMOST IV example (fetch-tool summary); BSIM3 and BSIM4 page of this vault.

Ques: How can a few points give the parameters of the ACM model?

Because the model’s parameters are tied to simple bias conditions. Coitinho et al. extract the specific current from two strong-inversion saturation points at 40 and 4 , giving about 310 for an AMS 0.8 nMOS simulated with BSIM3v3 as reference. The threshold voltage is the gate voltage at which the current equals three times the specific current, an inversion level of 3, about 0.845 ; the slope factor, 1.25, follows from the pinch-off voltage; and the low-field mobility, about 514 , and the degradation coefficient come from against in the linear region. They note that a -based method gives the specific current more accurately. This threshold definition differs from extrapolated ones, so values should not be mixed between models (my reading). Reference: R. M. Coitinho, L. H. Spiller, M. C. Schneider and C. Galup-Montoro, ‘A Simplified Methodology for the Extraction of Parameters of the ACM MOST Model’, seminar slides, Texas A&M University (26 November 2001) (equations garbled in the extract) (fetch-tool summary); Charge-Based Models (EKV) page of this vault.

Ques: How is the effective channel length extracted?

From devices of several lengths. In the channel-resistance method, after Terada and Muta (1979), the measured linear-region resistance is ; plotting against mask length for several gate voltages gives lines that intersect at (background knowledge). For W = 10 , , and at 1 overdrive, the 1 and 0.5 devices give 238 and 165 (computed). Ortiz-Conde et al. (2000) review this and related methods for threshold voltage, effective length and individual source and drain resistances. Bias-dependent and , common in scaled devices, blur the intersection, which is why later methods use single curves. Reference: A. Ortiz-Conde, F. J. Garcia Sanchez and J. J. Liou, ‘On the extraction of threshold voltage, effective channel length and series resistance of MOSFETs’, Journal of Telecommunications and Information Technology 2(3-4), 43-58 (2000), doi:10.26636/jtit.2000.3-4.28 (abstract and reference list only) (fetch-tool summary).

References

  1. A. Ortiz-Conde, F. J. Garcia Sanchez, J. J. Liou, A. Cerdeira, M. Estrada and Y. Yue, “A review of recent MOSFET threshold voltage extraction methods,” Microelectronics Reliability, vol. 42, no. 4-5, pp. 583-596, 2002, doi:10.1016/s0026-2714(02)00027-6. Available: https://stars.library.ucf.edu/facultybib2000/3388
  2. A. Ortiz-Conde, F. J. Garcia-Sanchez, J. Muci, A. Teran Barrios and J. J. Liou, “Revisiting MOSFET threshold voltage extraction methods,” Microelectronics Reliability, vol. 53, no. 1, pp. 90-104, 2013, doi:10.1016/j.microrel.2012.09.015. Available: https://stars.library.ucf.edu/scopus2010/7890
  3. F. Liao et al., “MoS2 Dual-gate Transistors with Electrostatically Doped Contacts,” arXiv:1912.07885 (Supplementary Section 3). Available: https://arxiv.org/abs/1912.07885
  4. R. Trevisoli, R. T. Doria, M. de Souza, S. Barraud, M. Vinet, M. Casse, G. Reimbold, O. Faynot, G. Ghibaudo and M. A. Pavanello, “A New Method for Series Resistance Extraction of Nanometer MOSFETs,” IEEE Transactions on Electron Devices, 2017 (CEA-Leti publication listing). Available: https://cea.fr/cea-tech/leti/english/Lists/Publications/StructuredDisplayForm.aspx?ID=449
  5. Silvaco, “opt_ex09: BSIM3 MOSFET Model Extraction,” UTMOST IV examples. Available: https://silvaco.com/examples/utmost4/section1/example9/index.html
  6. R. M. Coitinho, L. H. Spiller, M. C. Schneider and C. Galup-Montoro, “A Simplified Methodology for the Extraction of Parameters of the ACM MOST Model,” seminar slides, Texas A&M University, Nov. 2001. Available: https://people.engr.tamu.edu/s-sanchez/607%20ACM%20extraction%20parameters.pdf
  7. A. Ortiz-Conde, F. J. Garcia Sanchez and J. J. Liou, “On the extraction of threshold voltage, effective channel length and series resistance of MOSFETs,” Journal of Telecommunications and Information Technology, vol. 2, no. 3-4, pp. 43-58, 2000, doi:10.26636/jtit.2000.3-4.28. Available: https://jtit.pl/jtit/article/view/28

Related pages in this vault: BSIM3 and BSIM4, Temperature Scaling, Binning and Geometry Scaling, Charge-Based Models (EKV), Diode Compact Models, Surface-Potential Models (PSP and HiSIM), Model Quality and Benchmark Tests, Process Corners and Statistical Models, SMU and Probe Station, GUM Uncertainty Budgets.