Binning and Geometry Scaling

1. Theory

• Definition: Geometry scaling makes one model card describe transistors of every drawn length, width and finger count, either through physically based scaling functions of the effective dimensions (global scaling) or by splitting the geometry range into bins, each with its own parameter set (All About Circuits; Chauhan et al.).
• Binning: Within a bin, parameters vary as $P_0+P_L/L+P_W/W+P_P/(LW)$, and the simulator picks the bin from LMIN, LMAX, WMIN and WMAX (All About Circuits; background knowledge for the form).
• Layout-dependent effects: Stress from shallow-trench isolation, well proximity, contact placement and neighbouring structures change threshold voltage and mobility for the same W and L, so post-layout instance parameters are added (MOS-AK 2012 industry slides).
• Trade-off: Bins fit data closely but multiply parameters and risk discontinuities; global scaling is compact and smooth but harder to extract (All About Circuits; Chauhan et al.; computed).

2. Working Principle

• Effective dimensions: Drawn sizes are corrected by process offsets and per-side reductions, evaluated per finger (BSIM3 and BSIM4 page; background knowledge).
• Bin selection: The simulator chooses the bin containing the instance’s L and W and evaluates that card; a mismatch between selection and evaluation width causes out-of-bin errors (Clapp).
• Layout parameters: Extraction tools measure distances such as SA, SB and SCA from the layout and pass them to the model, which shifts parameters relative to the reference layout used in extraction (MOS-AK 2012 industry slides; background knowledge).
• Statistics with geometry: Mismatch scales with gate area, so statistical models also depend on geometry (All About Circuits; Mismatch and Variability page).

3. Applications

• Process design kits: Binned BSIM cards, as in the heavily binned sky130 kit, and globally scaled cards (Clapp; All About Circuits).
• Post-layout simulation: Back-annotating stress and well-proximity parameters for analog matching and timing (MOS-AK 2012 industry slides).
• Layout practice: Dummy fingers and long diffusions to reduce stress sensitivity (background knowledge).
• Model development: Global scaling in BSIM6 and its successors (Chauhan et al.).

Geometry and Binning

Name	Formula	Related Formulae	Variables/Constants
Effective channel length and width	$L_{eff}=L_{drawn}+XL-2dL,W_{eff}=\frac{W_{drawn}}{NF}+XW-2dW$	$dL=LINT+\frac{LL}{L^{LLN}}+\frac{LW}{W^{LWN}}+\frac{LWL}{L^{LLN}{W}^{LWN}},dW=WINT+\dots$	$\begin{array}{r}{L}_{eff},W_{eff}:effectivelengthandwidth(per\\ finger)\end{array}$ $L_{drawn},W_{drawn}:layoutdimensions$ $XL,XW:processoffsets$ $dL,dW:lengthandwidthreductionsperside$ $NF:numberoffingers,LINT$ $WINT:offsets,LL,LW,LWL,LLN$ $\begin{array}{r}LWN:geometryterms(BSIM4forms,\\ backgroundknowledge);XLandXWareamong\\ theglobalstatisticalparametersonthe\\ ProcessCornersandStatisticalModels\\ page;LINTandWINTextractiononthe\\ ParameterExtractionMethodspage\end{array}$ $(nocomputedvalue)$
Geometry binning of model parameters	$P=P_0+\frac{P_L}{L_{eff}}+\frac{P_W}{W_{eff}}+\frac{P_P}{L_{eff}{W}_{eff}}$	$LMIN\le L<LMAX,WMIN\le W<WMAX(\text{bin selection})$	$\begin{array}{r}P:binnedparameter(forexampleVTH0,K1,\\ U0,VSAT)\end{array}$ $\begin{array}{r}{P}_0,P_L,P_W,P_P:itsbase,length,width\\ andproductcoefficients(BSIMformwith\\ L,WandPprefixes,background\\ knowledge),LMIN,LMAX,WMIN\end{array}$ $\begin{array}{r}WMAX:binlimits(boundaryinclusivity\\ variesbysimulator,background\\ knowledge);AllAboutCircuits:BSIM\\ modelswriteseveralversionsofthesame\\ devicefordifferentgeometryranges,\\ selectedbyLMIN,LMAX,WMINandWMAX,\\ binningnotstrictlynecessary(AMSmodels\\ withoutit),andthemultiplierMusedfor\\ widthsbeyondWMAX;Silvacostep4onthe\\ ParameterExtractionMethodspagefits\\ PVTH0,PK1,PK2,PUAandPRDSW\end{array}$ $\begin{array}{r}(computed:anassumedVTH0=0.4\mathrm{V}withPL\\ =0.01\mathrm{V}\mu \mathrm{m}gives0.50,0.42and0.41\mathrm{V}\\ atL=0.1,0.5and1\mu \mathrm{m})\end{array}$
Finger count and bin selection	$W_{finger}=\frac{W_{total}}{NF}$	$\text{bin chosen by }{W}_{total}\text{but model evaluated at }{W}_{finger}\Rightarrow \text{out-of-bin evaluation}$	$W_{finger}:widthperfinger$ $\begin{array}{r}{W}_{total}:totalwidth;Clapp(xyce-users):Xyce\\ selectedbinsbytotalWwhileBSIM4bins\\ byW/NF,sowithNFgreaterthan1the\\ widthsevaluatedfallbelowthebin\\ minimum,causingsolvererrorsfrom\\ equationsusedoutofbin,affectingthe\\ heavilybinnedsky130kit(GitHubissue\\ 179)\end{array}$ $\begin{array}{r}(computed:10\mu \mathrm{m}in10fingersis1\mu \mathrm{m}per\\ finger,fivetimesbelowaWMINof5\mu \mathrm{m}\\ chosenbytotalwidth)\end{array}$

Layout-Dependent Effects

Name	Formula	Related Formulae	Variables/Constants
Length-of-diffusion (STI) stress	$In{v}_{sa}=\frac{1}{SA+0.5L_{drawn}},In{v}_{sb}=\frac{1}{SB+0.5L_{drawn}}$	${\rho }_{eff}\propto In{v}_{sa}+In{v}_{sb}-{\left(In{v}_{sa}+In{v}_{sb}\right)}_{ref},\Delta \mu ,\Delta V_{th}\propto {\rho }_{eff}$	$\begin{array}{r}SA,SB:distancesfromthegatetothetwo\\ edgesofthediffusion\end{array}$ $\begin{array}{r}{L}_{drawn}:gatelength,In{v}_{sa},In{v}_{sb}:inverse\\ distances\end{array}$ $\begin{array}{r}{\rho }_{eff}:stressfactorrelativetothe\\ referencelayoutusedforextraction\\ (BSIM4stress-modelforms,background\\ knowledge);industryslides(MOS-AK2012):\\ STIlength-of-diffusionstressonthe\\ source/draindiffusionwithacritical\\ distanceofabout1\mu \mathrm{m},post-layout\\ instanceparametersSAandSB,andVTand\\ mobilitycorrections,withstressmainly\\ affectingmobilityanddiffusionaffecting\\ VTinregularlayouts\end{array}$ $\begin{array}{r}(computed:forL=0.1\mu \mathrm{m},SA=SB=1\mu \mathrm{m}\\ givesIn{v}_{sa}+In{v}_{sb}=1.90\mu {\mathrm{m}}^{-1},andSA=SB=\\ 0.2\mu \mathrm{m}gives8.0\mu {\mathrm{m}}^{-1},afourfoldincreasein\\ thestressterm)\end{array}$
Well-proximity and other layout-dependent effects	$\Delta V_{th,WPE}\propto KVTH0WE\cdot \left(SCA+WEB\cdot SCB+WEC\cdot SCC\right)$	$SCA,SCB,SCC=\text{integrals of the well-edge distance distribution}$	$\begin{array}{r}\Delta V_{th,WPE}:thresholdshiftfromwell\\ proximity,KVTH0WE,WEB\end{array}$ $WEC:modelcoefficients,SCA,SCB$ $\begin{array}{r}SCC:layoutinstanceparameters(BSIM4\\ forms,backgroundknowledge);industry\\ slides(MOS-AK2012):WPEfromion\\ scatteringoffthewellphotoresist\\ (criticaldistanceabove1\mu \mathrm{m},instance\\ parametersSCA,SCB,SCC),STIOD-to-OD\\ contexteffects,activeandgatecorner\\ rounding(local{W}_{eff}and{L}_{eff}corrections),\\ gatepitch,CESLstress(upto1\mu \mathrm{m})and\\ contactposition(local{R}_{s}and{C}_s),each\\ withabout1to10percentperformance\\ impactinlow-powertechnologyandmorein\\ high-powertechnologywherestress\\ dominates,sensitivitydependingonWand\\ L,andabout394DUTsforWPEalone(4W\\ by4Lby6distancesby2orientationsby\\ N/P)andabout2000perdevicetype\end{array}$ $\begin{array}{r}(computed:thestatedmatrix4x4x6x2\\ x2is384devices,not394(seetheQ/A))\end{array}$

Global Scaling

Name	Formula	Related Formulae	Variables/Constants
Global geometry scaling	$P\left(L,W\right)=f\left(L_{eff},W_{eff};\text{one parameter set}\right)(\text{no bins})$	$\sigma \left(\Delta P\right)=\frac{A_P}{\sqrt{WL}}(\text{area scaling of mismatch})$	$\begin{array}{r}f:physicallybasedscalingfunctionsof\\ theeffectivedimensions\end{array}$ $\begin{array}{r}{A}_P:mismatchcoefficient;Chauhanetal.:\\ globalgeometricalscalinginBSIM6\\ validatedonST40\mathrm{nm}bulkCMOSwith\\ correctbehaviouratcornergeometries,\\ about1percentRMSfittingerror\\ targeted;AllAboutCircuits:MonteCarlo\\ variationstiedtochannelarea;Pelgrom\\ lawontheMismatchandVariabilitypage\end{array}$ $\begin{array}{r}(computed:binning100parametersinto20\\ binswithfourcoefficientseachcarries\\ 8000coefficients,against100fora\\ singleglobalset)\end{array}$

Important Questions

Ques: What is model binning and how does a simulator choose a bin?

Binning splits the geometry range into rectangles in length and width, each with its own model card. All About Circuits describes BSIM models written in several versions for different gate widths and lengths, selected by LMIN, LMAX, WMIN and WMAX; widths beyond WMAX are built with the multiplier M. Within a bin, each binned parameter follows $P_0+P_L/L_{eff}+P_W/W_{eff}+P_P/(L_{eff}{W}_{eff})$ (background knowledge), so an assumed VTH0 of 0.4 $\mathrm{V}$ with PL = 0.01 $\mathrm{V}\mu \mathrm{m}$ gives 0.50, 0.42 and 0.41 $\mathrm{V}$ at 0.1, 0.5 and 1 $\mu \mathrm{m}$ (computed). Whether a boundary value belongs to the lower or upper bin depends on the simulator (background knowledge), which is why the next bin’s card must give the same result there. Reference: ‘MOS Transistor SPICE Models’, Designing Analog Chips, Simulation chapter, All About Circuits (author not named on the page) (fetch-tool summary).

Ques: Is binning necessary for accurate models?

No, but many kits use it. All About Circuits notes that binning is not strictly necessary and that some foundries, notably AMS, build equally accurate models without it, while Clapp describes sky130 as very heavily binned. BSIM6 was developed with global geometrical scaling, one parameter set for all sizes, and Chauhan et al. show correct behaviour at corner geometries of an ST 40 $\mathrm{nm}$ process. The two approaches trade differently: 20 bins of 100 parameters with four coefficients each carry 8000 coefficients, against 100 for a global set (computed), and bins can fit stubborn data quickly but risk discontinuities and poor behaviour between measured sizes. Global scaling is more physical and smooth, so it is preferable when the model’s scaling equations can fit the technology (my reading). Reference: ‘MOS Transistor SPICE Models’, Designing Analog Chips, Simulation chapter, All About Circuits (author not named on the page) (fetch-tool summary); M. Clapp, ‘Model binning ignores NF: bin is selected by total W, but BSIM4 evaluates at W/NF’, xyce-users Google Group post (with Xyce GitHub issue 179; versions not stated) (fetch-tool summary); Y. S. Chauhan, M. Chalkiadaki, S. Venugopalan, M. A. Karim, N. Paydavosi, S. Jandhyala, J. P. Duarte, C. Enz, A. Niknejad and C. Hu, ‘Global Geometrical Scaling in BSIM6’, MOS-AK San Francisco (12 December 2012) (slides) (fetch-tool summary).

Ques: Why must binned parameters be continuous at bin boundaries?

Because a circuit optimizer or a sweep of transistor size must see a smooth function. If two neighbouring bins give different currents at their shared length, the current jumps when a device crosses the boundary, so sizing loops, Monte Carlo of geometry and layout-dependent widths can produce spurious steps (background knowledge). With the binning form $P_0+P_L/L$, an assumed VTH0 of 0.4 $\mathrm{V}$ and PL of 0.01 $\mathrm{V}\mu \mathrm{m}$ gives 0.42 $\mathrm{V}$ at 0.5 $\mu \mathrm{m}$ (computed); a neighbouring bin fitted independently could give, say, 0.43 $\mathrm{V}$ there, a 10 $\mathrm{mV}$ step. Extraction tools therefore fit all bins together with continuity constraints, as in the binning step of the Silvaco BSIM3 sequence, which is repeated until all geometries fit (Parameter Extraction Methods page). Reference: Parameter Extraction Methods page of this vault.

Ques: Should a bin be selected by total width or by finger width?

By the width the model actually evaluates, the width per finger. Clapp reported that Xyce selected bins using the total width, while BSIM4 evaluates its equations at W/NF, so a multi-finger device could be assigned a bin for a large width and then evaluated at a much smaller one, outside the bin, producing misbehaving equations and solver errors. A 10 $\mu \mathrm{m}$ device in 10 fingers has 1 $\mu \mathrm{m}$ fingers, five times below a WMIN of 5 $\mu \mathrm{m}$ chosen from the total (computed). The issue mattered for the heavily binned sky130 kit and was raised as Xyce GitHub issue 179; the post does not state its resolution. Kits must document whether WMIN and WMAX refer to total or finger width (my reading). Reference: M. Clapp, ‘Model binning ignores NF: bin is selected by total W, but BSIM4 evaluates at W/NF’, xyce-users Google Group post (with Xyce GitHub issue 179; versions not stated) (fetch-tool summary).

Ques: What are layout-dependent effects and how large are they?

Shifts in transistor behaviour caused by the surrounding layout rather than W and L. The 2012 industry slides list well-proximity effects from ion scattering off the well photoresist, STI stress through the length of diffusion and diffusion-to-diffusion spacing, active and gate corner rounding, gate pitch, contact-etch-stop-layer stress and contact position, with critical distances around 1 $\mu \mathrm{m}$. In regular layouts stress mainly changes mobility and diffusion effects change the threshold. Each effect costs about 1 to 10 per cent of performance in low-power technologies and more in high-power ones, where stress dominates, and its sensitivity depends on W and L. Post-layout parameters such as SA, SB, SCA, SCB and SCC carry the layout into the model. Reference: ‘Compact Model Extensions for Realistic Circuit Simulation: a Perspective from Industry’, MOS-AK Workshop, JIIT Noida (16 March 2012) (presenter not named; acknowledges the ST team; file name Juge_MOS-AK_India12) (fetch-tool summary).

Ques: How many test devices does layout-dependent-effect characterization need?

Hundreds per effect. The 2012 industry slides quote about 394 devices for the well-proximity effect alone, built from 4 widths, 4 lengths, 6 distances, 2 orientations and both n- and p-channel devices, and about 2000 per device type for all effects. The stated matrix gives $4\times 4\times 6\times 2\times 2=384$ (computed), not 394; the extra 10 are probably reference devices without a nearby well edge, or the figure is a typo (my reading). Either way, the count shows why layout-effect models are expensive: each effect needs its own distance sweeps across geometries, orientations and device types, and the test structures must isolate one effect while holding the others at reference values. Foundries reduce the work by sharing structures between effects (background knowledge). Reference: ‘Compact Model Extensions for Realistic Circuit Simulation: a Perspective from Industry’, MOS-AK Workshop, JIIT Noida (16 March 2012) (presenter not named; acknowledges the ST team; file name Juge_MOS-AK_India12) (fetch-tool summary).

Ques: How is STI stress from the length of diffusion represented?

Through the distances from the gate to the diffusion edges. The industry slides name the instance parameters SA and SB for the STI length-of-diffusion effect, with VT and mobility corrections and a critical distance of about 1 $\mu \mathrm{m}$. In the BSIM4 stress model, the stress scales with $1/(SA+0.5L)+1/(SB+0.5L)$ relative to the reference layout used for extraction (background knowledge). For a 0.1 $\mu \mathrm{m}$ gate, SA = SB = 1 $\mu \mathrm{m}$ gives 1.90 $\mu {\mathrm{m}}^{-1}$, while 0.2 $\mu \mathrm{m}$ gives 8.0 $\mu {\mathrm{m}}^{-1}$ (computed), a fourfold increase. Compressive STI stress lowers electron mobility and raises hole mobility in typical orientations (background knowledge), so nMOS and pMOS shift in opposite directions. Designers add dummy fingers or longer diffusions to keep SA and SB large and equal for matched devices. Reference: ‘Compact Model Extensions for Realistic Circuit Simulation: a Perspective from Industry’, MOS-AK Workshop, JIIT Noida (16 March 2012) (presenter not named; acknowledges the ST team; file name Juge_MOS-AK_India12) (fetch-tool summary).

References

1. “MOS Transistor SPICE Models,” Designing Analog Chips, Simulation chapter, All About Circuits (author not named on the page). Available: https://www.allaboutcircuits.com/textbook/designing-analog-chips/simulation/mos-transistor-spice-models/
2. M. Clapp, “Model binning ignores NF: bin is selected by total W, but BSIM4 evaluates at W/NF,” xyce-users Google Group post. Available: https://groups.google.com/g/xyce-users/c/-FEl6hVh3EE
3. Y. S. Chauhan, M. Chalkiadaki, S. Venugopalan, M. A. Karim, N. Paydavosi, S. Jandhyala, J. P. Duarte, C. Enz, A. Niknejad and C. Hu, “Global Geometrical Scaling in BSIM6,” MOS-AK Workshop, San Francisco, Dec. 2012. Available: https://www.mos-ak.org/sanfrancisco_2012/presentations/T07_Chauhan_MOS-AK_121212.pdf
4. “Compact Model Extensions for Realistic Circuit Simulation: a Perspective from Industry,” MOS-AK Workshop, JIIT Noida, Mar. 2012 (presenter not named on the slides). Available: https://www.mos-ak.org/india/presentations/Juge_MOS-AK_India12.pdf

Related pages in this vault: Parameter Extraction Methods, Mismatch and Variability, Process Corners and Statistical Models, BSIM3 and BSIM4, Model Quality and Benchmark Tests, Temperature Scaling.