1. Theory
- Definition: A furnace anneal system heats batches of wafers in a quartz tube under , Ar or forming gas to repair implant damage, activate dopants, and passivate interfaces (Jaeger; Jin et al.).
- Regrowth: Amorphized silicon recrystallizes by solid-phase epitaxy at 500 to 650 with an activation energy of about 2.7 (Johnson and McCallum).
- Dopant motion: Residual interstitials cause transient enhanced diffusion before ordinary diffusion takes over (Stanford).
- Interface passivation: Hydrogen anneals at 400 to 600 passivate interface dangling bonds ( centres), cutting them from about to cm (Pobegen; Jin et al.).
2. Working Principle
- Load: A batch of more than 150 wafers is loaded into the tube (furnace patent).
- Ramp: The tube ramps at 4 to 8 , which adds minutes of effective soak (furnace patent; computed).
- Soak: Typically 800 to 1000 for 30 min for activation, or 400 for forming gas (Jaeger; Jin et al.).
- Cool and unload: Temperatures and ramps are limited to avoid slip, which typically occurs above 900 (furnace patent).
3. Applications
- Low-temperature regrowth: Solid-phase epitaxy of amorphized layers (Johnson and McCallum).
- Forming gas anneal: MOS interface passivation at about 400 (Jin et al.; Pobegen).
- Deep junctions and wells: Long anneals where diffusion is wanted (Diffusion Furnace page).
Damage Repair and Regrowth
| Name | Formula | Related Formulae | Variables/Constants |
|---|---|---|---|
| Solid-phase epitaxial regrowth | |||
| Dopant-enhanced regrowth | |||
| Annealing energy scale |
Dopant Redistribution
| Name | Formula | Related Formulae | Variables/Constants |
|---|---|---|---|
| Transient enhanced diffusion | |||
| Profile broadening | |||
| Ramp contribution |
Interface Passivation and Budget
| Name | Formula | Related Formulae | Variables/Constants |
|---|---|---|---|
| Forming gas anneal | |||
| Post-oxidation nitrogen anneal | |||
| Thermal budget |
Important Questions
Ques: How fast does implant-amorphized silicon regrow by solid-phase epitaxy?
The amorphous-crystalline interface moves at . Johnson and McCallum measured buried amorphous layers from 460 to 660 and found 2.68 with angstrom per second. That gives 1.56 angstrom per second at 550 , so a 100 layer regrows in about 11 minutes, and 13.6 angstrom per second at 600 (computed). The steep temperature dependence means a 50 K change alters regrowth time almost tenfold (computed). Dopants speed regrowth: boron at raised the rate about 30 times at 460 , and Csepregi’s earlier work found up to 6 times for phosphorus and arsenic. Equal n- and p-type dopants cancel, giving nearly intrinsic rates. Reference: B. C. Johnson and J. C. McCallum, ‘Dopant-enhanced solid phase epitaxy in buried amorphous silicon layers’, University of Melbourne, arXiv:1007.5372 (fetch-tool summary).
Ques: Is the solid-phase epitaxy activation energy 2.3 eV or 2.7 eV?
The sources differ. Doolittle’s lecture lists about 2.3 for solid-phase epitaxy in silicon, while Johnson and McCallum measure 2.68 and cite Roth et al. at 2.7 with a prefactor of angstrom per second. The two measured sets agree closely, giving rates within 11 to 14 per cent of each other between 500 and 600 (computed). The 2.7 value is more likely correct, because it comes from direct interface-velocity measurements over a 200 K range, while the 2.3 appears as a rounded lecture figure (my reading). With 2.3 and the same prefactor, regrowth at 550 would be about 200 times faster than measured (computed), which would make low-temperature anneals far shorter than observed. Reference: W. A. Doolittle, ECE 6450 Lecture 5, ‘Ion Implantation’, Georgia Institute of Technology (fetch-tool summary); B. C. Johnson and J. C. McCallum, ‘Dopant-enhanced solid phase epitaxy in buried amorphous silicon layers’, University of Melbourne, arXiv:1007.5372 (fetch-tool summary).
Ques: Why does a furnace anneal make implanted junctions deeper than expected?
Because of transient enhanced diffusion and the slow ramps. After implantation, damage recombines quickly but leaves roughly one interstitial per dopant, which forms {311} clusters that keep releasing interstitials for seconds to minutes (Stanford). At 750 the interstitial concentration exceeds equilibrium by more than , so boron diffuses far faster than its intrinsic rate. A vertical furnace ramping at 4 to 8 (furnace patent) passes slowly through this range, and each ramp adds about 5 to 10 minutes of equivalent soak at 1000 (computed). Even intrinsic diffusion for 30 minutes at 1000 widens a 70 straggle to 100 (computed). Jaeger notes that rapid anneals at 950 to 1050 with 50 /s ramps give much lower Dt. Reference: J. D. Plummer, M. D. Deal and P. B. Griffin, EE 212 class handout 14, chapter 8 ‘Ion Implantation’ (Stanford, 1999-2000), hosted on the University of Washington EE 528 site (fetch-tool summary); US patent 6,296,709, ‘Temperature ramp for vertical diffusion furnace’ (USPTO full text; assignee not shown): tube ramps of 8 K/min from 1273 to 1323 K and 4 K/min from 1323 to 1373 K, batches of more than 150 wafers, slip typically above 900 C (fetch-tool summary); W. A. Doolittle, ECE 6450 Lecture 5, ‘Ion Implantation’, Georgia Institute of Technology (fetch-tool summary); R. C. Jaeger, Introduction to Microelectronic Fabrication, 2nd ed., chapter 5 ‘Ion Implantation’ lecture slides (Pearson 2002), hosted by KMITL (fetch-tool summary); Diffusion Furnace page of this vault.
Ques: What does a forming gas anneal do?
It passivates interface defects with hydrogen. Jin, Weber and Blakers used 5 per cent hydrogen in argon at 400 for 30 minutes after oxidation. Pobegen describes the targets as silicon dangling bonds ( centres) at about cm, which optimized forming gas reduces to about cm. The authors also found that an in-situ nitrogen anneal right after oxidation lowered the (111) density from to , 58 per cent fewer (computed), and reduced surface recombination. After forming gas, the difference between annealed and unannealed samples became small, but after a 600 , 3 minute anneal the in-situ annealed samples kept about half the surface recombination velocity. Hydrogen passivation therefore degrades at higher temperatures, while defects removed structurally stay removed (my reading). Reference: H. Jin, K. J. Weber and A. W. Blakers, ‘The effect of a post oxidation in-situ nitrogen anneal on Si surface passivation’, Australian National University conference paper (about 2006) (fetch-tool summary); G. Pobegen, ‘Degradation of Electrical Parameters of Power Semiconductor Devices - Process Influences and Modeling’, PhD thesis, TU Wien, section 1.3.1 on the Pb centre (fetch-tool summary).
Ques: When is a furnace still the right anneal tool?
When a long, uniform, low-temperature or batch treatment is wanted. Solid-phase epitaxy at 500 to 650 needs minutes to hours and benefits from the furnace’s uniform temperature (Johnson and McCallum; my reading). Forming gas anneals at 400 for 30 minutes are naturally batch processes (Jin et al.). Deep wells and drive-ins want large Dt (Diffusion Furnace page). For shallow junctions the furnace is unsuitable, since the total thermal budget, the sum of over every step including ramps (each weighted as in the effective-time integral of Timans et al.), must stay small against the junction depth (my reading). Jaeger contrasts 800 to 1000 furnace anneals of 30 minutes with rapid anneals at 950 to 1050 of seconds, which is why the next pages cover RTP, laser and flash annealing (my reading). Reference: B. C. Johnson and J. C. McCallum, ‘Dopant-enhanced solid phase epitaxy in buried amorphous silicon layers’, University of Melbourne, arXiv:1007.5372 (fetch-tool summary); H. Jin, K. J. Weber and A. W. Blakers, ‘The effect of a post oxidation in-situ nitrogen anneal on Si surface passivation’, Australian National University conference paper (about 2006) (fetch-tool summary); Diffusion Furnace page of this vault; R. C. Jaeger, Introduction to Microelectronic Fabrication, 2nd ed., chapter 5 ‘Ion Implantation’ lecture slides (Pearson 2002), hosted by KMITL (fetch-tool summary); P. Timans et al., ‘Flat-Top Flash Annealing For Advanced CMOS Processing’, Mattson Technology (2012): effective time as an Arrhenius-weighted integral (fetch-tool summary).
References
- B. C. Johnson and J. C. McCallum, “Dopant-enhanced solid phase epitaxy in buried amorphous silicon layers,” arXiv:1007.5372. Available: https://arxiv.org/pdf/1007.5372
- W. A. Doolittle, “Lecture 5: Ion Implantation,” ECE 6450, Georgia Institute of Technology. Available: https://alan.ece.gatech.edu/ECE6450/Lectures/ECE6450L5-Ion%20Implantation.pdf
- J. D. Plummer, M. D. Deal and P. B. Griffin, EE 212 Handout 14, “Chapter 8: Ion Implantation,” Stanford University, 1999-2000. Available: https://dunham.ece.uw.edu/ee528/notes/Chapter8.pdf
- “Temperature ramp for vertical diffusion furnace,” US Patent 6,296,709. Available: https://image-ppubs.uspto.gov/dirsearch-public/print/downloadPdf/6296709
- G. Pobegen, “Degradation of Electrical Parameters of Power Semiconductor Devices - Process Influences and Modeling,” PhD thesis, TU Wien, section 1.3.1. Available: https://www.iue.tuwien.ac.at/phd/pobegen/Semiconductor-insulator-interface-point-defects.html
- P. Timans et al., “Flat-Top Flash Annealing For Advanced CMOS Processing,” Mattson Technology, AVS NCCAVS, 2012. Available: https://www.nccavs-usergroups.avs.org/wp-content/uploads/JTG2012/JTG2012_7timans_mattson.pdf
- R. C. Jaeger, Introduction to Microelectronic Fabrication, 2nd ed., Pearson, 2002, chapter 5 lecture slides. Available: https://www.ami.kmitl.ac.th/wp-content/uploads/2018/05/12026118_Lecture8.pdf
- Diffusion Furnace page of this vault.
- H. Jin, K. J. Weber and A. W. Blakers, “The effect of a post oxidation in-situ nitrogen anneal on Si surface passivation,” Australian National University. Available: https://openresearch-repository.anu.edu.au/bitstream/1885/29156/2/01_Jin_The_effect_of_a_post_oxidation_2006.pdf
Related pages in this vault: Beamline Ion Implanter, Diffusion Furnace, Thermal Oxidation Furnace, MOS Capacitor, Charge Pumping, Lifetime Testers, Rapid Thermal Processor, Laser Annealing System, Flash Lamp Annealing System.