1. Theory
- Definition: A laser annealing system heats only the near-surface layer of the wafer for microseconds to milliseconds by scanning a line-focused laser, reaching temperatures near the silicon melting point while bulk and buried layers stay cool (Ultratech patent; Illgen et al.).
- Dwell time: Heating time equals line width divided by scan speed, and sets the heated depth through the thermal diffusion length (Ultratech patent).
- Non-melt and melt modes: Laser spike annealing stays below melting for dopant activation; excimer laser annealing melts thin amorphous silicon to recrystallize it (Illgen et al.; Yao-Peng and Chen).
- Absorption: CO2 light at 10.6 is coupled at Brewster’s angle; visible pre-heat beams can raise absorption (Illgen et al.; Ultratech patent).
2. Working Principle
- Form the line: Shape the beam into a long, narrow line image with uniform intensity (Ultratech patent).
- Scan: Move the wafer or beam so each point is heated for the dwell time (Ultratech patent).
- Control: Hold the peak temperature to about plus or minus 3 with feedback (Ultratech patent).
- Overlap: For pulsed excimer lasers, overlap pulses so each point receives many shots (Yao-Peng and Chen).
3. Applications
- Dopant activation: Millisecond or microsecond activation of source, drain and extensions with almost no diffusion (Illgen et al.; Ultratech patent).
- LTPS displays: Excimer crystallization of amorphous silicon on glass for TFT backplanes (Yao-Peng and Chen).
- Back-end-compatible anneals: Front-side heating above copper or aluminium limits for 3D integration (Ultratech patent).
Scanning and Heat Flow
| Name | Formula | Related Formulae | Variables/Constants |
|---|---|---|---|
| Dwell time | |||
| Thermal diffusion length | |||
| Absorbed-power check |
Optical Coupling and Limits
| Name | Formula | Related Formulae | Variables/Constants |
|---|---|---|---|
| Brewster-angle CO2 coupling | |||
| Two-beam preheat | |||
| Device-side temperature limits |
Melt Annealing and Pattern Effects
| Name | Formula | Related Formulae | Variables/Constants |
|---|---|---|---|
| Excimer laser conditions | |||
| Melt regimes and grain size | |||
| Pattern effects in device annealing |
Important Questions
Ques: How do dwell time and scan speed set the heated depth?
Each point is heated for the line width divided by the scan speed (Ultratech patent). A conventional 100 line scanned at about 100 mm/s gives 1 (computed), inside the conventional 0.1 to 10 range, while Ultratech’s ultra-short scheme scans a 25 image at 25 m/s for 1 . Heat spreads over a thermal diffusion length . The patent’s figure gives 10 at about 10 and 30 at about 100 , which implies a diffusivity of about (computed), about one eighth of Ioffe’s room-temperature value of 0.8 , as expected for hot silicon (computed). Microsecond dwell therefore heats only the top 10 or so, letting the surface reach 1000 or more while copper or aluminium layers below stay under their limits (my reading). Reference: A. M. Hawryluk and S. Anikitchev, ‘Laser annealing systems and methods with ultra-short dwell times’, US patent 9,558,973 B2, Ultratech (priority June 2012) (fetch-tool summary); Ioffe Institute, NSM archive, ‘Si - Silicon: Thermal properties’: thermal diffusivity 0.8 cm2/s (fetch-tool summary).
Ques: Is 200 W enough to heat the laser line by 1000 degrees?
Yes, by a simple energy estimate. Ultratech’s patent states that 200 W absorbed in a 50 by 1 mm area raises it by about 1000 at dwell times of 5 or less. Over 5 the heat reaches about = 7.1 deep, using the implied by the patent’s own diffusion lengths (computed). With Ioffe’s density and the JANAF heat capacity at 1000 K, the heated volume holds about J/K, so 1 mJ raises it by about 1290 K (computed), the same order as the patent’s figure. The patent holds peak temperature to plus or minus 3 with line intensity uniform to about plus or minus 5 per cent. The thin heated layer also cools quickly by conduction into the cold bulk, which is why laser anneals need no gas cooling, unlike RTP (Rapid Thermal Processor page; my reading). Reference: A. M. Hawryluk and S. Anikitchev, ‘Laser annealing systems and methods with ultra-short dwell times’, US patent 9,558,973 B2, Ultratech (priority June 2012) (fetch-tool summary); Ioffe Institute, NSM archive, ‘Si - Silicon: Mechanical properties’: density 2.329 g/cm3 (fetch-tool summary); NIST-JANAF Thermochemical Tables, Si(cr), table Si-002: Cp = 26.338 J/(K mol) at 1000 K (fetch-tool summary); Rapid Thermal Processor page of this vault.
Ques: Why is the CO2 laser used at Brewster’s angle?
To make absorption insensitive to the film stack. Illgen et al. describe laser spike annealing with a 10.6 CO2 laser, p-polarized and incident at Brewster’s angle to minimize reflectivity variation. For silicon with UniversityWafer’s index of about 3.42, quoted without a wavelength, Brewster’s angle is 73.7 degrees, while normal incidence would reflect 30 per cent (computed) and vary with oxide and nitride thicknesses (my reading). Pattern effects remain: threshold voltage at saturation falls as STI density rises. Illgen et al. found LSA and flash lamp annealing give the same transistor performance and leakage without absorber layers, and that removing the preceding RTA reduced threshold fluctuation between the highest and lowest STI density by about 50 per cent. Reference: R. Illgen, S. Flachowsky, T. Herrmann, T. Feudel, D. Thron, B. Bayha, W. Klix, M. Horstmann and R. Stenzel, ‘A Comparative Study of Non-melt Laser Spike Annealing and Flash Lamp Annealing in Terms of Transistor Performance and Pattern Effects on SOI-CMOSFETs for the 32 nm Node and Below’, ULIS 2009, HTW Dresden and AMD Saxony (fetch-tool summary); UniversityWafer, ‘What is the Refractive Index of Substrates?’: silicon about 3.42 (wavelength not stated) (fetch-tool summary).
Ques: How does excimer laser annealing crystallize amorphous silicon?
By melting a thin film with nanosecond ultraviolet pulses. Yao-Peng and Chen used a 308 XeCl laser with 23 pulses at 300 Hz and 250 to 400 on 50 a-Si:H, dehydrogenated at 470 for 6 minutes. With 95 per cent overlap, each point receives about 20 pulses (computed). Grain size depends on fluence: partial melting gives small grains, near-complete melting gives large grains, and full melting gives small grains again. Just below full melt, unmelted seeds at the film base let grains grow laterally before new nuclei form (my reading). Their regularly arranged poly-Si reached an average grain size of 0.3 , against under 0.5 for conventional ELA, and poly-Si TFT mobility approaches 100 times that of a-Si TFTs. Reference: Yao-Peng and C. N. Chen, ‘The Influence of Poly-Si Morphology with Excimer Laser Optics System’, NCTU, IMID ‘05 Digest (2005) (fetch-tool summary).
Ques: When is laser annealing preferred over spike RTP?
When diffusion must be almost eliminated or underlying layers protected. A 1 dwell at peak temperature gives about a thousandth of a spike anneal’s time near the peak (computed from a spike residence of about 1 , Rapid Thermal Processor page), so dopants activate at higher temperature with nanometre-scale motion (my reading). Ultratech’s microsecond scheme also keeps copper below about 900 and aluminium below 600 on device wafers. The costs are pattern effects, scan stitching and limited depth (Illgen et al.; my reading). For LTPS, excimer lasers are the only practical way to crystallize silicon on glass at high quality (Yao-Peng and Chen; my reading). Reference: Rapid Thermal Processor page of this vault; A. M. Hawryluk and S. Anikitchev, ‘Laser annealing systems and methods with ultra-short dwell times’, US patent 9,558,973 B2, Ultratech (priority June 2012) (fetch-tool summary); R. Illgen, S. Flachowsky, T. Herrmann, T. Feudel, D. Thron, B. Bayha, W. Klix, M. Horstmann and R. Stenzel, ‘A Comparative Study of Non-melt Laser Spike Annealing and Flash Lamp Annealing in Terms of Transistor Performance and Pattern Effects on SOI-CMOSFETs for the 32 nm Node and Below’, ULIS 2009, HTW Dresden and AMD Saxony (fetch-tool summary); Yao-Peng and C. N. Chen, ‘The Influence of Poly-Si Morphology with Excimer Laser Optics System’, NCTU, IMID ‘05 Digest (2005) (fetch-tool summary).
References
- A. M. Hawryluk and S. Anikitchev, “Laser annealing systems and methods with ultra-short dwell times,” US Patent 9,558,973 B2, Ultratech, 2017. Available: https://patents.google.com/patent/US9558973
- Ioffe Physico-Technical Institute, “Si - Silicon: Thermal properties,” New Semiconductor Materials. Available: https://www.ioffe.ru/SVA/NSM/Semicond/Si/thermal.html
- Ioffe Physico-Technical Institute, “Si - Silicon: Mechanical properties,” New Semiconductor Materials. Available: https://www.ioffe.ru/SVA/NSM/Semicond/Si/mechanic.html
- NIST-JANAF Thermochemical Tables, “Silicon (Si), crystal,” table Si-002. Available: https://janaf.nist.gov/tables/Si-002.html
- UniversityWafer, “What is the Refractive Index of Substrates?” Available: https://universitywafer.com/refractive-index.html
- Rapid Thermal Processor page of this vault.
- R. Illgen et al., “A Comparative Study of Non-melt Laser Spike Annealing and Flash Lamp Annealing in Terms of Transistor Performance and Pattern Effects on SOI-CMOSFETs for the 32 nm Node and Below,” ULIS 2009. Available: https://www.htw-dresden.de/fileadmin/HTW/Fakultaeten/Elektrotechnik/Dokumente/Personen/Roland_Stenzel/Veroeffentlichungen/ulis2009_ri.pdf
- Yao-Peng and C. N. Chen, “The Influence of Poly-Si Morphology with Excimer Laser Optics System,” IMID ‘05 Digest, 2005. Available: https://koreascience.kr/article/CFKO200524282624710.pdf
Related pages in this vault: Rapid Thermal Processor, Furnace Anneal System, Beamline Ion Implanter, Thin-Film Transistors (a-Si, LTPS, IGZO, Organic), Silicon on Insulator (SOI) MOSFET, Pyrometers and Wafer Temperature Sensors, Flash Lamp Annealing System.