1. Theory

  • Definition: A flash lamp annealing system first heats the wafer from the back to an intermediate temperature with lamps, then fires a millisecond xenon flash at the front surface, raising it by up to several hundred kelvin while the bulk stays near the intermediate temperature (Timans et al.; Mattson page).
  • Millisecond window: Pulses of about 1 to 10 reach peak temperatures up to 1300 (Timans et al.; Gebel et al.).
  • Kinetic selectivity: Activation (about 5 ) rises faster with temperature than boron diffusion (about 3.5 ), so short, hot anneals activate more for less diffusion (Timans et al.).
  • Whole-wafer exposure: Unlike scanned lasers, the whole wafer is heated at once, avoiding stitching (Timans et al.; my reading).

2. Working Principle

  • Preheat: Backside lamps ramp the wafer at about 150 to 250 to 1050 (Timans et al.; Mattson page).
  • Flash: A capacitor bank discharges into xenon flash lamps, delivering more than 10 to the front (Timans et al.; flash patent).
  • Measure: Front and back temperatures are monitored in real time (Mattson page).
  • Cool: The heated surface cools by conduction into the bulk, then the whole wafer cools radiatively (flash patent; my reading; Rapid Thermal Processor page).

3. Applications

  • Ultra-shallow junctions: Source, drain and extension activation (Timans et al.; Gebel et al.).
  • Halo and high-k anneals: Short anneals that preserve gate stacks (Mattson page).
  • Silicides: Nickel and titanium silicide formation (Mattson page).
  • Strain-preserving anneals: Activation without relaxing SiGe or Si:C stressors (Timans et al.).

Thermal Cycle

NameFormulaRelated FormulaeVariables/Constants
Two-stage thermal cycle

Pulsed power requirement

Heated depth

Kinetic Selectivity

NameFormulaRelated FormulaeVariables/Constants
Effective anneal time


Activation against diffusion
Boron flash activation

Results and Applications

NameFormulaRelated FormulaeVariables/Constants
Pulse shape and sheet resistance
Device result
Process applications

Important Questions

Ques: How does a flash lamp system heat only the wafer surface?

In two stages. Backside lamps ramp the wafer at about 150 to an intermediate temperature, then a flash above 10 heats the front (Timans et al.); a patented system uses capacitor-fed xenon lamps with 0.1 to 100 pulses after halogen preheat to 600 to 800 (flash patent). During the pulse heat spreads only about , 100 in 1 and 316 in 10 for the hot-silicon diffusivity implied on the Laser Annealing System page (computed), so in an assumed 775 wafer the back stays near the intermediate temperature. The surface then cools by conduction into the cooler bulk, faster than radiation alone (my reading; Rapid Thermal Processor page). Reference: P. Timans, G. Xing, S. Hamm, S. McCoy, J. Cibere, G. Stuart and D. Camm, ‘Flat-Top Flash Annealing For Advanced CMOS Processing’, Mattson Technology, AVS NCCAVS Joint Technical Group talk (July 2012) (fetch-tool summary); Mattson Technology, ‘Millisecond Anneal’ product page (Millios) (fetch-tool summary); US patent 10,998,214, ‘Light irradiation type heat treatment method’ (USPTO full text; assignee not shown in the fetched text): xenon or krypton flash lamps fed from a capacitor, pulses of 0.1 to 100 ms, halogen preheat to 600 to 800 C (700 C in the embodiment), surface momentarily at 1000 C or higher with a rise only near the surface (fetch-tool summary); Laser Annealing System page of this vault; Rapid Thermal Processor page of this vault.

Ques: Can a flash anneal reach 1650 degrees C, or is the peak limited to 1300 degrees C?

The sources suggest different limits. Mattson’s product page lists intermediate temperatures up to 1050 and a temperature jump up to 600 , which taken together would imply 1650 (computed), while Timans et al. give a practical peak of up to 1300 and prefer a few milliseconds below 1250 . Silicon melts at 1412 (Ioffe), so the two Mattson figures are separate limits that cannot be combined, and the 1300 peak is more likely the real working limit (my reading). Gebel et al. used lower rear preheats of 250, 500 and 750 , consistent with jumps of several hundred kelvin to a peak below melting. Reference: Mattson Technology, ‘Millisecond Anneal’ product page (Millios) (fetch-tool summary); P. Timans, G. Xing, S. Hamm, S. McCoy, J. Cibere, G. Stuart and D. Camm, ‘Flat-Top Flash Annealing For Advanced CMOS Processing’, Mattson Technology, AVS NCCAVS Joint Technical Group talk (July 2012) (fetch-tool summary); Ioffe Institute, New Semiconductor Materials archive, ‘Si - Silicon: Thermal properties’ (melting point 1412 C, thermal diffusivity 0.8 cm2/s) (fetch-tool summary); T. Gebel, M. Voelskow, F. Eichhorn, W. Skorupa, G. Mannino, V. Privitera, F. Priolo, E. Napolitani and A. Carnera, ‘Flash-lamp processing with millisecond pulses for ultra-shallow boron implants in silicon’, IIT 2002, HZDR publication record (fetch-tool summary).

Ques: Why does a short, hot flash activate dopants with less diffusion?

Because activation has the higher activation energy. Timans et al. define an effective anneal time as the Arrhenius-weighted integral of the temperature profile referred to 1000 , and take about 5 for boron activation against 3.5 for diffusion. Their ratio of effective times for the two processes lies between 6.5 and 9.5 for 0.1 to 10 pulses, with flat-top profiles best. A flat 4 pulse at 1250 gives effective times of 7.1 for activation and 0.75 for diffusion, a ratio of 9.4 (computed). Raising the peak from 1050 to 1300 improves the activation-to-diffusion ratio by about 8 times (computed). Reference: P. Timans, G. Xing, S. Hamm, S. McCoy, J. Cibere, G. Stuart and D. Camm, ‘Flat-Top Flash Annealing For Advanced CMOS Processing’, Mattson Technology, AVS NCCAVS Joint Technical Group talk (July 2012) (fetch-tool summary).

Ques: Is the flash soak time up to 10 ms or up to 20 ms?

The sources quote different ranges. Gebel et al. used flash soak times of 2 to 20 with the final temperature reached within 1 , while Timans et al. give a practical duration of up to 10 and prefer a few milliseconds. The heated depth explains the difference: at 20 heat spreads about 450 , more than half of an assumed 775 wafer, so the bulk heats and the method approaches a spike anneal (computed; my reading). Gebel’s 20 is therefore a valid research condition, while Timans’ 10 limit is more likely the useful production range (my reading). Gebel activated up to 20 per cent of a , 500 boron dose, , within 60 . Reference: T. Gebel, M. Voelskow, F. Eichhorn, W. Skorupa, G. Mannino, V. Privitera, F. Priolo, E. Napolitani and A. Carnera, ‘Flash-lamp processing with millisecond pulses for ultra-shallow boron implants in silicon’, IIT 2002, HZDR publication record (fetch-tool summary); P. Timans, G. Xing, S. Hamm, S. McCoy, J. Cibere, G. Stuart and D. Camm, ‘Flat-Top Flash Annealing For Advanced CMOS Processing’, Mattson Technology, AVS NCCAVS Joint Technical Group talk (July 2012) (fetch-tool summary).

Ques: What do flash pulse shape and device results show?

Longer flat-top pulses lower sheet resistance with little extra depth. Timans et al. report arsenic at 2.5 and falling from 564 to 511 and 442 ohm per square from pulse A to C, with profile abruptness improving from 3.6 to 2.4 per decade, and boron at 1 from 497 to 381 and 335 ohm per square. That is 22 and 33 per cent lower sheet resistance (computed). In an SOI process, long millisecond flash NFETs matched spike-plus-laser devices in roll-off with about half the boron halo dose, and showed no corner leakage. Illgen et al. likewise found laser spike and flash anneals equivalent in device performance (Laser Annealing System page). Reference: P. Timans, G. Xing, S. Hamm, S. McCoy, J. Cibere, G. Stuart and D. Camm, ‘Flat-Top Flash Annealing For Advanced CMOS Processing’, Mattson Technology, AVS NCCAVS Joint Technical Group talk (July 2012) (fetch-tool summary); Laser Annealing System page of this vault.

References

  1. P. Timans, G. Xing, S. Hamm, S. McCoy, J. Cibere, G. Stuart and D. Camm, “Flat-Top Flash Annealing For Advanced CMOS Processing,” Mattson Technology, AVS NCCAVS Joint Technical Group, 2012. Available: https://www.nccavs-usergroups.avs.org/wp-content/uploads/JTG2012/JTG2012_7timans_mattson.pdf
  2. Mattson Technology, “Millisecond Anneal.” Available: https://mattson.com/?p=109
  3. Ioffe Physico-Technical Institute, “Si - Silicon: Thermal properties,” New Semiconductor Materials, Characteristics and Properties. Available: https://www.ioffe.ru/SVA/NSM/Semicond/Si/thermal.html
  4. “Light irradiation type heat treatment method,” US Patent 10,998,214. Available: https://image-ppubs.uspto.gov/dirsearch-public/print/downloadPdf/10998214
  5. Rapid Thermal Processor page of this vault.
  6. T. Gebel et al., “Flash-lamp processing with millisecond pulses for ultra-shallow boron implants in silicon,” IIT 2002, Taos. Available: https://www.hzdr.de/publications/Publ-4874
  7. Laser Annealing System page of this vault.

Related pages in this vault: Rapid Thermal Processor, Laser Annealing System, Furnace Anneal System, Beamline Ion Implanter, Pyrometers and Wafer Temperature Sensors, Silicon on Insulator (SOI) MOSFET.