1. Theory
- Definition: A rapid thermal oxidation (RTO) system heats a single wafer with lamps to 900 to 1200 for tens of seconds in oxygen or steam, growing thin oxides with a small thermal budget (Lassig; patent).
- Kinetics: Growth follows linear-parabolic kinetics, with most RTO oxides in the reaction-limited regime where thickness is very sensitive to temperature (patent; Thermal Oxidation Furnace page).
- Ramps: Fast ramps add an equivalent oxidation time and must be subtracted when extracting rate constants (patent; background knowledge).
- Temperature control: Pyrometry sets the wafer temperature, so emissivity and uniformity errors appear directly as thickness errors (patent).
2. Working Principle
- Load and purge: One wafer enters a quartz chamber, purged with inert gas (patent).
- Ramp and oxidize: Ramp at about 50 to the soak temperature in dry oxygen or pyrogenic steam (patent).
- Flush: Replace the oxidizing ambient before annealing (patent).
- Anneal: A short inert post-oxidation anneal removes hydrogen and reduces defects (patent).
3. Applications
- Thin gate oxides: 2 to 10 oxides and oxynitride bases with minimal dopant diffusion (background knowledge).
- Tunnel oxides: Flash tunnel oxides needing low defect density (background knowledge).
- Interface layers: Thin oxides under high-k dielectrics (background knowledge).
- Single-wafer flexibility: Short cycle times for advanced logic (background knowledge).
Thermal Cycle
| Name | Formula | Related Formulae | Variables/Constants |
|---|---|---|---|
| Ramp-equivalent time | |||
| Temperature sensitivity | |||
| Rate-constant extraction plot |
Kinetics and Ambient
| Name | Formula | Related Formulae | Variables/Constants |
|---|---|---|---|
| Activation energies | |||
| Pyrogenic steam composition | |||
| Dry RTO against Deal-Grove |
Anneal and Yield
| Name | Formula | Related Formulae | Variables/Constants |
|---|---|---|---|
| Post-oxidation anneal | |||
| Yield and defect density | |||
| Thermal budget against a furnace |
Important Questions
Ques: What is rapid thermal oxidation and how do ramps contribute to the oxide?
RTO heats a single wafer with lamps for tens of seconds, for example 30 at 1050 in steam after a 50 ramp (patent). Growth during the ramps is not negligible: the patent reports 137 angstrom grown during the ramps alone at 1150 and 27 angstrom at 965 . A linear ramp is equivalent to holding at the peak for about , which for 2 and 1150 is 1.75 up at 50 and 3.5 down at 25 (computed; background knowledge). That isothermal estimate is smaller than the measured ramp growth, probably because fast initial growth in the first nanometres is much faster than Deal-Grove predicts (my reading). The patent therefore subtracts the ramp growth before extracting rate constants. Reference: US patent 5,935,650, ‘Method of oxidation of semiconductor wafers in a rapid thermal processing (RTP) system’ (USPTO full text; assignee and inventors not shown in the fetched text) (fetch-tool summary); Effective-time integral for a linear temperature ramp; H. Z. Massoud and J. D. Plummer (1985) short-time furnace kinetics; J. D. Plummer, M. D. Deal and P. B. Griffin, Silicon VLSI Technology (background knowledge; not opened).
Ques: Is the activation energy for rapid thermal oxidation 1.31 eV or about 2 eV?
The sources differ. Lassig, Debolske and Crowley report a single 1.31 for dry oxidation of (100) silicon from 900 to 1200 and 60 to 240 in an arc-lamp system. The RTP patent gives 1.77 to 2.10 depending on doping and orientation, close to the Si-Si bond energy of 1.83 and Deal-Grove’s 1.95 linear value. The 2 range is more likely the correct value for the interface-reaction step, because the patent separates ramp growth and fits the linear constant, while one energy fitted over 60 to 240 spans the linear and parabolic regimes and so mixes in the lower diffusion energy (my reading). Lassig also notes ultraviolet-enhanced oxidation, a photon effect that would lower the apparent energy in lamp systems. Reference: S. E. Lassig, T. J. Debolske and J. L. Crowley, ‘Kinetics of Rapid Thermal Oxidation of Silicon’, MRS Online Proceedings Library vol. 92 (1987), abstract (fetch-tool summary); US patent 5,935,650, ‘Method of oxidation of semiconductor wafers in a rapid thermal processing (RTP) system’ (USPTO full text; assignee and inventors not shown in the fetched text) (fetch-tool summary).
Ques: Why does RTO thickness uniformity depend so strongly on temperature?
In the linear regime thickness grows as , so the fractional change is per kelvin. With 2 this is 1.33 per cent per kelvin at 1050 (computed). The patent’s 1.7 per cent uniformity on 200 mm wafers therefore implies a temperature spread of only about 1.3 K across the wafer (computed), and its quoted sensitivity of 4 angstrom per kelvin matches a film of roughly 300 angstrom (computed). Pyrometer errors from emissivity changes therefore appear directly as thickness errors (my reading). For comparison, a furnace batch reaches uniformity by long soaks in a near-isothermal tube, at the cost of a large thermal budget (Thermal Oxidation Furnace page). Reference: US patent 5,935,650, ‘Method of oxidation of semiconductor wafers in a rapid thermal processing (RTP) system’ (USPTO full text; assignee and inventors not shown in the fetched text) (fetch-tool summary); Thermal Oxidation Furnace page of this vault.
Ques: How is safe pyrogenic steam made in an RTO system?
Hydrogen is burned with excess oxygen in an external torch at 700 , above the 650 autoignition point (patent). The patent’s controllers cap the : ratio at 2 and use a safety ratio of 1.67, giving at most 91 per cent steam with 9 per cent excess oxygen; 1.82 slm of hydrogen with 1.09 slm of oxygen gives exactly that mixture (computed). The Thermal Oxidation Furnace page quotes ratios of 1.8 to 1.9 from background knowledge, so the two sources differ. The patent’s 1.67 is more likely the better figure for a single-wafer chamber, because it is a stated design value with a larger margin from stoichiometry (my reading). After oxidation the chamber is flushed at 750 for 130 , since a 10 flush lowered yield from 100 to 86 per cent. Reference: US patent 5,935,650, ‘Method of oxidation of semiconductor wafers in a rapid thermal processing (RTP) system’ (USPTO full text; assignee and inventors not shown in the fetched text) (fetch-tool summary); Thermal Oxidation Furnace page of this vault.
Ques: How does dry RTO thickness compare with the Deal-Grove prediction?
Measured oxide is about twice the prediction. The patent grows 118 angstrom in 240 of dry oxidation at 1050 , while the Deal-Grove law with the furnace page’s Arrhenius constants, adjusted to (100) silicon and with no initial offset, gives about 58 angstrom (computed). The gap reflects the anomalously fast initial growth of the first 20 to 30 in dry oxygen, which Massoud and Plummer modelled with an extra exponential term (background knowledge). RTO operates almost entirely in this regime, so furnace constants underestimate it and RTO recipes are calibrated empirically (my reading). In thermal budget terms, 30 at 1050 corresponds to about 5 minutes at 900 (computed), but without the slow furnace ramps that drive dopant diffusion. Reference: US patent 5,935,650, ‘Method of oxidation of semiconductor wafers in a rapid thermal processing (RTP) system’ (USPTO full text; assignee and inventors not shown in the fetched text) (fetch-tool summary); Thermal Oxidation Furnace page of this vault; Effective-time integral for a linear temperature ramp; H. Z. Massoud and J. D. Plummer (1985) short-time furnace kinetics; J. D. Plummer, M. D. Deal and P. B. Griffin, Silicon VLSI Technology (background knowledge; not opened).
References
- “Method of oxidation of semiconductor wafers in a rapid thermal processing (RTP) system,” US Patent 5,935,650. Available: https://image-ppubs.uspto.gov/dirsearch-public/print/downloadPdf/5935650
- H. Z. Massoud and J. D. Plummer, “Analytical relationship for the oxidation of silicon in dry oxygen in the thin-film regime,” J. Appl. Phys., 1987, and related 1985 work; J. D. Plummer, M. D. Deal and P. B. Griffin, Silicon VLSI Technology, Prentice Hall, 2000 (cited from background knowledge).
- S. E. Lassig, T. J. Debolske and J. L. Crowley, “Kinetics of Rapid Thermal Oxidation of Silicon,” MRS Online Proceedings Library, vol. 92, 1987. Available: https://www.cambridge.org/core/journals/mrs-online-proceedings-library-archive/article/abs/kinetics-of-rapid-thermal-oxidation-of-silicon/A357740337B4639A8BDEDE0DAC22263B
- Thermal Oxidation Furnace page of this vault.
Related pages in this vault: Thermal Oxidation Furnace, Pyrometers and Wafer Temperature Sensors, Spectroscopic Ellipsometer, MOS Capacitor, Short Channel MOSFET, Floating Gate Flash Memory (NOR and NAND).