Floating Gate Flash Memory (NOR and NAND)

1. Theory

Definition: A floating-gate flash cell is an n-channel MOSFET with an electrically isolated polysilicon floating gate between the channel and the control gate; charge on the floating gate stores the bit.
Non-volatile storage: The floating gate is surrounded by oxide with a 3.1 eV barrier to silicon, so stored electrons stay for years without power.
Threshold shift: Stored charge shifts the threshold seen from the control gate by $Δ V_{T} = - Q_{F G} / C_{I P D}$ .
Capacitive coupling: The floating-gate potential is a weighted sum of the control-gate, drain, source and body voltages; the gate coupling ratio $α_{G} = C_{I P D} / C_{T}$ sets how much control-gate voltage reaches it.
Inter-poly dielectric: An ONO (oxide-nitride-oxide) stack between the floating and control gates provides high coupling with low leakage.
NOR vs NAND: NOR cells connect in parallel for random access; NAND cells connect in series strings for density.

2. Working Principle

NOR programming (channel hot electrons): Drain at about 4 to 5 V and gate at about 9 to 10 V accelerate channel electrons; a few “lucky” electrons cross the oxide barrier. Fast, but draws hundreds of $μ$ A per cell.
NAND programming (Fowler-Nordheim): About 15–20 V on the control gate gives 8–10 MV/cm across the tunnel oxide, and electrons tunnel in with only nA per cell, allowing massive parallel programming.
Block erase: Raising the shared p-well to about 20 V removes electrons by Fowler-Nordheim tunnelling from a whole block at once (hence “flash”).
Incremental step pulse programming (ISPP): Program-verify pulses that rise by a fixed step narrow each threshold distribution to about one step width.
Read: The cell either conducts or not at a read voltage between the programmed and erased thresholds.
NAND program inhibit: Unselected strings are self-boosted by the pass voltage so their tunnel-oxide field stays too low to program.
Scaling limits: The tunnel oxide cannot go below about 7–8 nm because of stress-induced leakage, neighbouring floating gates interfere, and the number of stored electrons falls to tens.

3. Applications

Code storage (NOR): Firmware, boot code and execute-in-place memory in microcontrollers, automotive ECUs and networking equipment.
High-density data storage (NAND): SSDs, phones and memory cards; some 3D NAND products still use floating-gate cells.

Name	Formula	Related Formulae	Variables/Constants
Floating gate potential (capacitive coupling)	$V_{F G} = α_{G} V_{C G} + α_{D} V_{D} + α_{S} V_{S} + α_{B} V_{B} + \frac{Q _{F G}}{C _{T}}$	$C_{T} = C_{I P D} + C_{t u n} + C_{S} + C_{D}$ $α_{x} = \frac{C _{x}}{C _{T}}$	$V_{F G} : p o t e n t ia l o f t h e f l o a t in g g a t e$ $V_{C G}, V_{D}, V_{S}, V_{B} : co n t r o l g a t e, d r ain, so u r ce an d b o d y v o l t a g es$ $α_{G}, α_{D}, α_{S}, α_{B} : co u pl in g r a t i os o f t h e f l o a t in g g a t e t o t h e co n t r o l g a t e, d r ain, so u r ce an d b o d y$ $Q_{F G} : n e t c ha r g e o n t h e f l o a t in g g a t e (n e g a t i v e w h e n e l ec t r o n s a r e s t or e d)$ $C_{T} : t o t a l c a p a c i t an ce o f t h e f l o a t in g g a t e$ $C_{I P D} : c a p a c i t an ce o f t h e in t er - p o l y d i e l ec t r i c b e tw ee n t h e co n t r o l g a t e an d t h e f l o a t in g g a t e$ $C_{t u n} : c a p a c i t an ce o f t h e t u nn e l o x i d e t o t h e c hann e l (b o d y)$ $C_{S}, C_{D} : c a p a c i t an ces o f t h e f l o a t in g g a t e t o t h e so u r ce an d d r ain o v er l a p s$
Inter-poly dielectric capacitance (ONO)	$C_{I P D} = \frac{ε _{0} A _{I P D}}{E O T _{O N O}}$	$E O T_{O N O} = t_{o x 1} + \frac{ε _{S i O_{2}}}{ε _{N}} t_{N} + t_{o x 2}$ $α_{G} = \frac{C _{I P D}}{C _{T}}$	$C_{I P D} : c a p a c i t an ce b e tw ee n t h e co n t r o l g a t e an d t h e f l o a t in g g a t e$ $A_{I P D} : o v er l a p a r e a o f t h e tw o g a t es (in c l u d in g t h e s i d e w a l l s o f a w r a p - a r o u n d co n t r o l g a t e)$ $E O T_{O N O} : e q u i v a l e n t o x i d e t hi c k n ess o f t h e o x i d e - ni t r i d e - o x i d e s t a c k$ $t_{o x 1}, t_{N}, t_{o x 2} : t hi c k n esses o f t h e b o tt o m o x i d e, ni t r i d e an d t o p o x i d e$ $ε_{S i O_{2}}, ε_{N} : r e l a t i v e p er mi tt i v i t i es o f s i l i co n d i o x i d e (3.9) an d s i l i co n ni t r i d e (ab o u t 7.5)$ $α_{G} : g a t e co u pl in g r a t i o, t y p i c a l l y 0.6 t o 0.7$
Threshold voltage shift and stored electrons	$Δ V_{T} = - \frac{Q _{F G}}{C _{I P D}}$	$N_{e} = \frac{C _{I P D} ∣ Δ V _{T} ∣}{q}$ $V_{T} = V_{T, 0} + Δ V_{T}$	$Δ V_{T} : s hi f t o f t h e t h r es h o l d v o l t a g e see n f r o m t h e co n t r o l g a t e$ $V_{T, 0} : t h r es h o l d v o l t a g e o f t h e n e u t r a l ce l l (Q_{F G} = 0)$ $N_{e} : n u mb er o f e l ec t r o n s t ha t p r o d u ce a s hi f t ∣ Δ V_{T} ∣$ $(t h e m e m or y w in d o w i s t h e d i f f er e n ce b e tw ee n t h e t h r es h o l d v o l t a g es o f t h e p r o g r amm e d an d er a se d s t a t es)$
Fowler-Nordheim tunnelling	$J_{F N} = A_{F N} E_{o x}^{2} exp (- \frac{B _{F N}}{E _{o x}})$	$A_{F N} = \frac{q ^{2}}{16 π ^{2} ℏ ϕ _{B}} \frac{m}{m _{o x}}$ $B_{F N} = \frac{4 2 m _{o x} ( q ϕ _{B} ) ^{3/2}}{3ℏ q}$ $E_{o x} = \frac{V _{o x}}{t _{t u n}}$	$J_{F N} : t u nn e l l in g c u r r e n t d e n s i t y t h r o ug h t h e t r ian g u l a r ba r r i er$ $E_{o x} : e l ec t r i c f i e l d in t h e t u nn e l o x i d e, w i t h V_{o x} t h e v o l t a g e a cr oss i t$ $t_{t u n} : t u nn e l o x i d e t hi c k n ess$ $ϕ_{B} : e l ec t r o n ba r r i er h e i g h t a t t h e inj ec t in g in t er f a ce in v o l t s (ab o u t 3.1 V f or S i - S i O_{2})$ $m, m_{o x} : e l ec t r o n ma ss in t h e inj ec t in g e l ec t r o d e an d in t h e o x i d e (ab o u t 0.42 m_{0})$ $(v a l i d w h e n V_{o x} > ϕ_{B}, so t ha t t h e ba r r i er i s t r ian g u l a r; b e l o w a t u nn e l o x i d e o f ab o u t 4 nm d i r ec t t u nn e l l in g t ak es o v er . T h e s i g n o f E_{o x} d ec i d es p r o g r am or er a se; m / m_{o x} i s t h e L e n z l in g er - S n o w f a c t or)$
Program and erase by tunnelling	$\frac{d Q _{F G}}{d t} = - A_{t u n} J_{F N} (E_{t u n})$	$E_{t u n} = \frac{V _{F G} - V _{c h}}{t _{t u n}}$ $V_{F G} = α_{G} V_{C G} + \frac{Q _{F G}}{C _{T}} (V_{D} = V_{S} = V_{B} = 0)$	$Q_{F G} : f l o a t in g g a t e c ha r g e (e l ec t r o n s inj ec t e d mak e i t m or e n e g a t i v e)$ $A_{t u n} : a r e a o f t h e t u nn e l o x i d e$ $E_{t u n} : f i e l d a cr oss t h e t u nn e l o x i d e$ $V_{c h} : c hann e l (s u r f a ce) p o t e n t ia l$ $(a s e l ec t r o n s a cc u m u l a t e, V_{F G} an d E_{t u n} f a l l, so t h e t u nn e l l in g c u r r e n t se l f - l imi t s an d t h e ce l l s a t u r a t es; er a se u ses t h e o pp os i t e f i e l d p o l a r i t y w i t h V_{C G} < 0 or V_{B} > 0)$ $(f l a t - ban d v o l t a g e, p o l y s i l i co n d e pl e t i o n an d t h e c hann e l s u r f a ce p o t e n t ia l a r e l u m p e d in t o V_{c h})$
Incremental step pulse programming (ISPP)	$Δ V_{T}^{(n)} \approx Δ V_{I S P P}$	$V_{C G}^{(n + 1)} = V_{C G}^{(n)} + Δ V_{I S P P}$	$Δ V_{T}^{(n)} : s hi f t o f t h e t h r es h o l d v o l t a g e a f t er t h e n - t h p r o g r am p u l se, o n ce t h e ini t ia l t r an s i e n t ha s p a sse d$ $Δ V_{I S P P} : in cr e m e n t o f t h e co n t r o l g a t e p u l se am pl i t u d e b e tw ee n s u ccess i v e p u l ses$ $V_{C G}^{(n)} : am pl i t u d e o f t h e n - t h p r o g r am p u l se$ $(t h e s t ee p f i e l d d e p e n d e n ce o f J_{F N} mak es t h e t h r es h o l d f o l l o w t h e g a t e p u l se w i t h u ni t y s l o p e, so t h e w i d t h o f t h e d i s t r ib u t i o n i s ab o u t Δ V_{I S P P})$
Channel hot-electron injection (lucky electron model)	$I_{G} = I_{D} P_{inj}$	$P_{inj} \propto exp (- \frac{ϕ _{B}}{λ E _{m}})$	$I_{G} : g a t e c u r r e n t c a r r y in g t h e h o t e l ec t r o n s in t o t h e f l o a t in g g a t e$ $I_{D} : d r ain c u r r e n t o f t h e ce l l d u r in g p r o g r ammin g$ $P_{inj} : p r o babi l i t y t ha t a c hann e l e l ec t r o n g ain s e n o ug h e n er g y an d i s r e d i r ec t e d t o w a r d t h e o x i d e w i t h o u t co l l i s i o n$ $ϕ_{B} : S i - S i O_{2} ba r r i er h e i g h t in v o l t s (ab o u t 3.1 V)$ $λ : h o t - e l ec t r o n sc a tt er in g m e an f r ee p a t h, ab o u t 9 nm in T am, K o an d H u$ $(p r o p or t i o na l i t y o n l y : t h e f u l l m o d e l m u l t i pl i es se p a r a t e p r o babi l i t i es f or g ainin g t h e e n er g y, b e in g r e d i r ec t e d an d cr oss in g t h e o x i d e, an d ϕ_{B} i s l o w er e d b y t h e ima g e f or ce an d t h e o x i d e f i e l d)$ $E_{m} : ma x im u m l a t er a l e l ec t r i c f i e l d n e a r t h e d r ain e n d o f t h e c hann e l$ $(u se d f or N O R ce l l p r o g r ammin g a t a d r ain v o l t a g e o f ab o u t 4 t o 5 V)$
Read current and memory window	$I_{D} = μ_{n} C_{t u n} \frac{W}{L} [α_{G} (V_{C G} - V_{T}) V_{D S} - \frac{V _{D S}^{2}}{2}]$	$Δ I_{D} \approx g_{m} ∣ Δ V_{T} ∣$ $V_{C G, r e a d} = \frac{V _{T, p r o g} + V _{T, er a se}}{2}$	$I_{D} : d r ain c u r r e n t o f t h e ce l l in t h e l in e a r r e g i o n (s ma l l V_{D S} f or r e a d in g)$ $V_{T} : t h r es h o l d v o l t a g e o f t h e ce l l r e f er r e d t o t h e co n t r o l g a t e, w hi c h in c l u d es t h e s t or e d c ha r g e$ $C_{t u n} : t u nn e l o x i d e c a p a c i t an ce p er u ni t a r e a, w hi c h co n t r o l s t h e c hann e l$ $α_{G} : g a t e co u pl in g r a t i o, s in ce t h e c hann e l r es p o n d s t o V_{F G} - V_{T, F G} = α_{G} (V_{C G} - V_{T})$ $Δ I_{D} : r e a d c u r r e n t d i f f er e n ce b e tw ee n t h e tw o s t a t es f or t h e s am e g a t e v o l t a g e$ $g_{m} : t r an sco n d u c t an ce o f t h e ce l l (co n t r o l - g a t e r e f er e n ce d)$ $V_{C G, r e a d} : r e a d v o l t a g e, c h ose n b e tw ee n t h e tw o t h r es h o l d v o l t a g es$ $(t h e d r ain co u pl in g α_{D} V_{D} t o t h e f l o a t in g g a t e i s n e g l ec t e d)$
NAND self-boosting channel potential (program inhibit)	$V_{c h} = V_{c h, 0} + B V_{p a ss}$	$B = \frac{C _{o x}}{C _{o x} + C _{d e p} + C _{j}}$	$V_{c h} : p o t e n t ia l o f t h e f l o a t in g c hann e l o f an inhibi t e d s t r in g$ $V_{c h, 0} : ini t ia l c hann e l p o t e n t ia l a f t er p r ec ha r g e$ $V_{p a ss} : p a ss v o l t a g e a ppl i e d t o t h e u n se l ec t e d co n t r o l g a t es$ $B : b oos t in g r a t i o o f t h e c a p a c i t i v e d i v i d er$ $C_{o x} : c a p a c i t an ce f r o m t h e co n t r o l g a t es t o t h e c hann e l$ $C_{d e p} : d e pl e t i o n c a p a c i t an ce o f t h e c hann e l$ $C_{j} : j u n c t i o n c a p a c i t an ce o f t h e so u r ce - d r ain r e g i o n s in t h e s t r in g$ $(t h e r ai se d c hann e l p o t e n t ia l r e d u ces t h e t u nn e l f i e l d b e l o w t h e p r o g r ammin g f i e l d; C_{d e p} an d C_{j} f a l l a s V_{c h} r i ses, so B i s bia s d e p e n d e n t)$
Floating gate to floating gate interference	$Δ V_{T, v i c t im} = \sum_{k} γ_{k} Δ V_{T, k}$	$γ_{k} = \frac{C _{F G - F G, k}}{C _{T}}$	$Δ V_{T, v i c t im} : t h r es h o l d s hi f t o f t h e v i c t im ce l l c a u se d b y p r o g r ammin g i t s n e i g hb or s$ $Δ V_{T, k} : t h r es h o l d s hi f t o f t h e k - t h n e i g hb or in g ce l l a f t er t h e v i c t im w a s p r o g r amm e d$ $γ_{k} : co u pl in g r a t i o t o n e i g hb or k (w or d l in e, bi t l in e or d ia g o na l d i r ec t i o n)$ $C_{F G - F G, k} : p a r a s i t i c c a p a c i t an ce b e tw ee n t h e tw o f l o a t in g g a t es$ $C_{T} : t o t a l f l o a t in g g a t e c a p a c i t an ce$
Charge loss and retention time	$t_{r e t} = \frac{C _{I P D} Δ V _{T, l oss}}{I _{l e ak}}$	$I_{l e ak} = A_{t u n} J_{l e ak}$ $J_{l e ak} = J_{S I L C} + J_{t h er m}$	$t_{r e t} : t im e f or t h e s t or e d c ha r g e t o l e ak u n t i l t h e t h r es h o l d v o l t a g e s hi f t s b y Δ V_{T, l oss}$ $Δ V_{T, l oss} : a l l o w e d l oss o f t h e t h r es h o l d v o l t a g e s hi f t$ $I_{l e ak} : t o t a l l e ak a g e c u r r e n t o f t h e f l o a t in g g a t e, t ak e n a s co n s t an t$ $J_{S I L C} : s t r ess - in d u ce d l e ak a g e c u r r e n t d e n s i t y t h r o ug h t h e t u nn e l o x i d e b y t r a p - a ss i s t e d t u nn e l l in g$ $J_{t h er m} : t h er ma l e mi ss i o n an d d e t r a pp in g c u r r e n t d e n s i t y$ $(r e t e n t i o n f a l l s a s t h e n u mb er o f p r o g r am - er a se cy c l es g r o w s an d a s t h e t e m p er a t u r e r i ses; co n s t an t I_{l e ak} i s a s im pl i f i c a t i o n, s in ce t h e l e ak a g e f a l l s a s t h e s t or e d c ha r g e an d i t s f i e l d d ec a y)$
Endurance limit	$N_{cy c} \approx \frac{Q _{B D} A _{t u n}}{2 C _{I P D} ∣ Δ V _{T} ∣}$	$Q_{cy c l e} = 2 C_{I P D} ∣ Δ V_{T} ∣$	$N_{cy c} : es t ima t e o f t h e n u mb er o f p r o g r am - er a se cy c l es u n t i l t h e t u nn e l o x i d e f ai l s$ $Q_{B D} : c ha r g e - t o - b r e ak d o w n p er u ni t a r e a o f t h e t u nn e l o x i d e$ $A_{t u n} : t u nn e l o x i d e a r e a$ $Q_{cy c l e} : c ha r g e p a sse d t h r o ug h t h e o x i d e in o n e p r o g r am an d o n e er a se o p er a t i o n$ $(t hi s es t ima t e i g n or es t h e t r a pp in g t ha t c l oses t h e m e m or y w in d o w b e f or e b r e ak d o w n an d t h e e x t r a c ha r g e p a sse d d u r in g t h e p r o g r am an d er a se t r an s i e n t s an d v er i f y o v er s h oo t, so i t i s an u pp er b o u n d)$

Important Questions

Ques: How does a floating gate store information without power?

The floating gate is a conductor completely surrounded by oxide, with a 3.1 eV barrier to the silicon and an even higher one to the control gate. Charge placed on it by tunnelling or hot-electron injection cannot cross the barrier at low field, so it stays for years. The stored charge $Q_{F G}$ shifts the threshold voltage seen from the control gate by $Δ V_{T} = - Q_{F G} / C_{I P D}$ , and the cell is read by checking whether it conducts at a gate voltage between the programmed and erased thresholds. Only tens to thousands of electrons (depending on the cell size) are needed for a window of a volt, and the number keeps decreasing as the cell is scaled. Reference: D. Kahng and S.M. Sze, “A floating gate and its application to memory devices,” Bell Syst. Tech. J. 46, 1288 (1967).

Ques: What is the difference between Fowler-Nordheim and channel hot-electron programming?

In Fowler-Nordheim programming, a high control-gate voltage (about 15 to 20 V) puts a field of 8 to 10 MV/cm across the tunnel oxide with the channel grounded, and electrons tunnel through the triangular barrier. The current is tiny (nanoamperes per cell), which allows thousands of cells to be programmed in parallel, as in NAND flash. In channel hot-electron programming, a drain voltage of 4 to 5 V and a gate voltage of about 9 to 10 V accelerate channel electrons until a few gain enough energy (the lucky-electron model) to cross the 3.1 eV barrier. This is fast but takes a channel current of hundreds of microamperes per cell, so it is used in NOR flash, where bytes are programmed individually. Reference: S.M. Tam, P.-K. Ko and C. Hu, “Lucky-electron model of channel hot-electron injection in MOSFET’s,” IEEE Trans. Electron Devices 31, 1116 (1984); R.H. Fowler and L. Nordheim, Proc. R. Soc. London A 119, 173 (1928); M. Lenzlinger and E.H. Snow, “Fowler-Nordheim tunneling into thermally grown SiO $_{2}$ ,” J. Appl. Phys. 40, 278 (1969).

Ques: Why is erase done on a whole block, and why is it called flash?

The erase in a flash cell removes electrons by Fowler-Nordheim tunnelling from the floating gate to the channel (the control gate is grounded or negative and the p-well is raised to about 20 V), and the p-well is shared by all the cells in a block. A cell therefore cannot be erased alone, and erasing the whole block at the same time (in a flash) gives the technology its name. This also lets the cell stay small, because no select transistor is needed for each cell. Programming selects bits within the erased block, so a page cannot be rewritten without erasing the block first. Reference: G. Cappelletti, C. Golla, P. Olivo and E. Zanoni, Flash Memories, Kluwer, 1999.

Ques: Why does incremental step pulse programming narrow the threshold distribution?

Because $J_{F N}$ depends exponentially on field, a pulse that raises the control gate voltage by a step $Δ V_{I S P P}$ increases the floating gate injection enough that the threshold shifts by the same amount, $Δ V_{T} \approx Δ V_{I S P P}$ . Each pulse is followed by a verify read; once a cell passes the verify level it is inhibited. A cell can therefore overshoot the verify level by at most about one step, so the distribution width is about $Δ V_{I S P P}$ . Variations in oxide thickness or coupling ratio change how many pulses a cell needs and its first-pulse response, but once a cell has reached the unity-slope regime they no longer change the final width much. A smaller step gives a narrower distribution but needs more pulses and a longer programming time. Reference: K.-D. Suh et al., “A 3.3 V 32 Mb NAND flash memory with incremental step pulse programming scheme,” IEEE J. Solid-State Circuits 30, 1149 (1995).

Ques: What does the gate coupling ratio do, and why is it a design target?

The ratio $α_{G} = C_{I P D} / C_{T}$ is the fraction of the control gate voltage that appears on the floating gate. A larger $α_{G}$ means a larger tunnel field for the same control gate voltage, so lower program voltages or faster programming. It is raised by using a thin ONO stack with a high equivalent capacitance, by wrapping the control gate around the floating gate (larger $A_{I P D}$ ), and by reducing overlap to the source and drain. The trade-off is that a wrap-around gate needs a tall floating gate, which increases the interference between neighbors. Reference: G. Cappelletti, C. Golla, P. Olivo and E. Zanoni, Flash Memories, Kluwer, 1999.

Ques: What limits the scaling of the tunnel oxide and the floating gate?

The tunnel oxide cannot be thinned below about 7 to 8 nm because trap-assisted leakage (SILC) grows with cycling, and a single weak spot discharges the whole floating gate, so retention fails. This keeps the program voltage high. As the cell pitch shrinks, the parasitic capacitance between neighboring floating gates increases the interference term $γ_{k}$ , and the programming of a neighbor shifts the threshold of an already programmed victim cell. Also the number of stored electrons falls to a few tens, so statistical fluctuation limits the window. These effects motivated charge-trap storage and 3D NAND. Reference: J.-D. Lee, S.-H. Hur and J.-D. Choi, “Effects of floating-gate interference on NAND flash memory cell operation,” IEEE Electron Device Lett. 23, 264 (2002).

Ques: How does self-boosting prevent unselected NAND cells from being programmed?

When a word line is programmed, the unselected strings on the same word line have their string select transistor turned off and their channel left floating. When the pass voltage $V_{p a ss}$ is applied to the other word lines, the channel potential is raised by capacitive coupling to $V_{c h} = V_{c h, 0} + B V_{p a ss}$ , with a boosting ratio $B$ of about 0.6 to 0.8. This reduces the voltage across the tunnel oxide of the inhibited cell, so the field falls below the tunnelling threshold, whereas the selected string has a grounded channel. Too high a $V_{p a ss}$ causes pass disturb of the other cells in the selected string. Reference: J. Brewer and M. Gill (eds.), Nonvolatile Memory Technologies with Emphasis on Flash, Wiley-IEEE Press, 2008.

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