Short Channel MOSFET

1. Theory

• Definition: A short-channel MOSFET is a planar MOSFET whose channel length is comparable to the source/drain depletion widths and the electrostatic scale length $\ell$, so the gate no longer controls the channel alone.
• Scope: This page extends the Long Channel MOSFET page (same NMOS reference device and notation) to devices where $L\gg \ell$ no longer holds.
• Scale length: $\ell =\sqrt{({\epsilon }_s/{\epsilon }_{ox})t_{ox}{W}_{dm}}$ measures how far the drain potential reaches into the channel; good gate control needs $L$ several times $\ell$.
• Charge sharing: The source and drain junctions balance part of the depletion charge under the gate, so less gate charge is needed and $V_{TH}$ falls as $L$ shrinks (roll-off).
• Drain-induced barrier lowering (DIBL): The drain voltage lowers the source-channel barrier, reducing $V_{TH}$ as $V_{DS}$ rises; it grows roughly as $\exp (-L/2\ell )$.
• Velocity saturation: High lateral fields cap the carrier velocity at $v_{sat}$ ($\approx 10^7$ cm/s for electrons in Si).
• Mobility degradation: A strong vertical field pushes carriers against the interface, lowering the effective mobility through surface-roughness and phonon scattering.

2. Working Principle

• Early saturation: Carriers reach $v_{sat}$ at the drain end before pinch-off, so $V_{Dsat}$ is smaller than $V_{GS}-V_{TH}$.
• Linear current law: In the fully velocity-saturated limit, $I_{Dsat}\approx Z{C}_{ox}{v}_{sat}(V_{GS}-V_{TH})$, linear in overdrive and independent of $L$.
• Transconductance and speed: $g_m$ saturates at $Z{C}_{ox}{v}_{sat}$, while $f_T\approx v_{sat}/2\pi L$ keeps improving as $L$ shrinks.
• Leakage and punchthrough: Short-channel effects degrade the subthreshold swing and raise off-current; at high $V_{DS}$ the source and drain depletion regions can merge (punchthrough).
• Output conductance: DIBL adds to channel-length modulation, lowering output resistance and intrinsic gain.
• Hot-carrier degradation: High fields near the drain create energetic carriers that cause impact ionization (substrate current) and oxide damage; LDD structures reduce the peak field.
• Scaling limits: Constant-field (Dennard) scaling breaks down because $k_{B}T/q$, oxide tunnelling and junction depth do not scale, leading to high-k gates and multi-gate structures.

3. Applications

• Planar CMOS logic down to about 28–20 nm: Microcontrollers, SoCs and ASICs at cost-effective planar nodes.
• RF CMOS transceivers: Wi-Fi, Bluetooth, GPS and cellular transceivers integrated with digital circuits.
• Embedded SRAM and mixed-signal SoCs: Dense on-chip memory and data converters at planar nodes.

Name	Formula	Related Formulae	Variables/Constants
Electrostatic scale length	$\ell =\sqrt{\frac{{\epsilon }_s}{{\epsilon }_{ox}}{t}_{ox}{W}_{dm}}$	$W_{dm}=\sqrt{\frac{4{\epsilon }_s{\varphi }_F}{q{N}_A}}$ $\begin{array}{r}L\gg \ell \\ \text{for long-channel behavior}\end{array}$	$\begin{array}{r}\ell :\text{electrostatic scale length of the}\\ \text{channel potential near the drain}\\ \text{(denoted }\lambda \text{ in some references;}\\ \ell \text{ is used here since }\lambda \text{ is the}\\ \text{channel-length modulation parameter)}\end{array}$ $t_{ox}:\text{oxide thickness}$ $W_{dm}:\text{maximum depletion width}$ ${\epsilon }_{ox},{\epsilon }_s:\text{oxide and semiconductor permittivity}$
Source and drain junction depletion widths	$\begin{array}{r}{W}_S=\sqrt{\frac{2{\epsilon }_s\left(V_{bi}+V_{SB}\right)}{q{N}_A}}\\ W_D=\sqrt{\frac{2{\epsilon }_s\left(V_{bi}+V_{SB}+V_{DS}\right)}{q{N}_A}}\end{array}$	$V_{bi}=\frac{k_{B}T}{q}\ln \left(\frac{N_A{N}_{SD}}{n_i^2}\right)$ $\text{(see PN Junction Diode page; one-sided junction)}$ $\begin{array}{r}{W}_S+W_D\to L\\ \text{marks the onset of punchthrough}\end{array}$	$\begin{array}{r}{W}_S,W_D:\text{depletion}\text{widths}\text{of}\text{the}\\ \text{source-substrate}\text{and}\text{drain-substrate}\\ \text{junctions}\end{array}$ $V_{bi}:\text{source/drain-substrate built-in potential}$ $N_{SD}:\text{source/drain doping concentration}$ $k_B:Boltzmannconstant$
Effective channel length	$L_{eff}=L_{drawn}-2\Delta L_{lat}$	$\begin{array}{r}L\to L_{eff}\text{in the long-channel}\\ \text{current equations}\end{array}$	$L_{drawn}:\text{mask-defined (drawn) gate length}$ $\begin{array}{r}\Delta L_{lat}:\text{lateral diffusion of the source/drain}\\ \text{under the gate edge (per side)}\end{array}$
Threshold voltage roll-off (charge sharing)	$\Delta V_{TH}=-\frac{q{N}_A{W}_{dm}}{C_{ox}}\frac{r_j}{L}\left[\sqrt{1+\frac{2W_{dm}}{r_j}}-1\right]$	$V_{TH}(L)=V_{TH}+\Delta V_{TH}$ $\Delta V_{TH}\approx -\frac{q{N}_A{W}_{dm}^2}{C_{ox}L}\left(r_j\gg W_{dm}\right)$	$\begin{array}{r}\Delta V_{TH}:\text{threshold}\text{voltage}\text{shift}\text{relative}\text{to}\\ \text{the}\text{long-channel}\text{value}\end{array}$ $\begin{array}{r}{r}_j:\text{source/drain junction depth}\\ \text{(radius of a cylindrical junction)}\end{array}$ $\begin{array}{r}\text{(charge-sharing}\text{model:}\text{the}\text{gate}\text{supports}\\ \text{only}\text{the}\text{part}\text{of}\text{the}\text{depletion}\text{charge}\text{not}\\ \text{already}\text{controlled}\text{by}\text{the}\text{source}\text{and}\text{drain}\\ \text{junctions;}\text{assumes}\text{uniform}\text{doping}\text{and}\\ \text{neglects}{V}_{DS}\text{)}\end{array}$
Drain-induced barrier lowering (DIBL)	${\eta }_{DIBL}=\frac{V_{TH}\left(V_{DS,lin}\right)-V_{TH}\left(V_{DS,sat}\right)}{V_{DS,sat}-V_{DS,lin}}$	$V_{TH}\left(V_{DS}\right)=V_{TH}\left(V_{DS,lin}\right)-{\eta }_{DIBL}\left(V_{DS}-V_{DS,lin}\right)$ ${\eta }_{DIBL}\propto \exp \left(-\frac{L}{2\ell }\right)$	${\eta }_{DIBL}:\text{DIBL coefficient (commonly quoted in mV/V)}$ $\begin{array}{r}{V}_{DS,lin}:\text{low}\text{drain}\text{voltage}\text{used}\text{to}\text{extract}\\ \text{the}\text{linear-region}\text{threshold}\end{array}$ $V_{DS,sat}:\text{high drain voltage (typically }{V}_{DD}\text{)}$
Punchthrough voltage	$V_{PT}=\frac{q{N}_A}{2{\epsilon }_s}{\left(L-W_S\right)}^2-V_{bi}$	$\begin{array}{r}{W}_S+W_D=L\\ \left(V_{SB}=0\right)\end{array}$	$\begin{array}{r}{V}_{PT}:\text{drain-source}\text{voltage}\text{at}\text{which}\text{the}\\ \text{source}\text{and}\text{drain}\text{depletion}\text{regions}\text{touch}\\ \text{below}\text{the}\text{channel}\end{array}$ $\begin{array}{r}\text{(bulk}\text{punchthrough;}\text{barrier}\text{lowering}\text{at}\\ \text{the}\text{surface}\text{sets}\text{in}\text{at}\text{lower}{V}_{DS}\text{and}\text{is}\\ \text{described}\text{by}\text{DIBL)}\end{array}$
Velocity-field relation (velocity saturation)	$v(E)=\frac{{\mu }_{n}E}{1+\frac{E}{E_c}}$	$E_c=\frac{v_{sat}}{{\mu }_n}$ $\begin{array}{r}v={\mu }_{n}E\left(E<E_c\right),v=v_{sat}\left(E\ge E_c\right)\\ \text{with }{E}_c=\frac{2v_{sat}}{{\mu }_n}\text{(piecewise model)}\end{array}$	$v:\text{carrier drift velocity}$ $E:\text{lateral electric field along the channel}$ $\begin{array}{r}{v}_{sat}:\text{saturation}\text{velocity}\text{(}\approx 10^{7}cm/s\text{for}\\ \text{electrons}\text{in}\text{Si}\text{at}\text{300}\text{K)}\end{array}$ $\begin{array}{r}{E}_c:\text{critical field. The two forms above define}\\ E_c\text{differently (}{v}_{sat}/{\mu }_n\text{vs. }2v_{sat}/{\mu }_n\text{);}\\ \text{the hyperbolic form is used on this page}\end{array}$
Vertical-field mobility degradation	${\mu }_{eff}=\frac{{\mu }_0}{1+\theta \left(V_{GS}-V_{TH}\right)}$	$E_{eff}=\frac{|Q_d|+{\eta }_Q|Q_n|}{{\epsilon }_s},{\eta }_Q=\frac{1}{2}\text{(electrons)},\frac{1}{3}\text{(holes)}$ $\frac{1}{{\mu }_{eff}}=\frac{1}{{\mu }_C}+\frac{1}{{\mu }_{ph}}+\frac{1}{{\mu }_{sr}}$	${\mu }_{eff}:\text{effective channel mobility}$ ${\mu }_0:\text{low-field mobility}$ $\theta :\text{mobility degradation coefficient (empirical)}$ $\begin{array}{r}{E}_{eff}:\text{effective}\text{transverse}\text{field}\text{seen}\text{by}\\ \text{inversion}\text{carriers}\end{array}$ $\begin{array}{r}{Q}_d,Q_n:\text{depletion}\text{and}\text{inversion}\text{charge}\text{per}\\ \text{unit}\text{area}\end{array}$ $\begin{array}{r}{\mu }_C,{\mu }_{ph},{\mu }_{sr}:\text{Coulomb,}\text{phonon}\text{and}\\ \text{surface-roughness}\text{limited}\text{mobilities}\\ \text{(Matthiessen’s}\text{rule)}\end{array}$
Linear-region drain current with velocity saturation	$\begin{array}{r}{I}_D=\frac{1}{1+\frac{V_{DS}}{E_{c}L}}{\mu }_n{C}_{ox}\frac{Z}{L}\\ \times \left[\left(V_{GS}-V_{TH}\right)V_{DS}-\frac{V_{DS}^2}{2}\right]\end{array}$	$\begin{array}{r}{I}_D\to {\mu }_n{C}_{ox}\frac{Z}{L}\left[\left(V_{GS}-V_{TH}\right)V_{DS}-\frac{V_{DS}^2}{2}\right]\\ \text{for }{E}_{c}L\gg V_{DS}\text{ (long-channel limit)}\end{array}$	$I_D:\text{drain current}$ $V_{DS},V_{GS}:\text{drain-source and gate-source voltages}$ $\begin{array}{r}\text{(gradual-channel}\text{result}\text{for}\text{the}\text{hyperbolic}\\ v(E)\text{relation;}{\mu }_n\text{may}\text{be}\text{replaced}\text{by}{\mu }_{eff}\text{)}\end{array}$
Saturation drain voltage with velocity saturation	$V_{Dsat}=E_{c}L\left[\sqrt{1+\frac{2\left(V_{GS}-V_{TH}\right)}{E_{c}L}}-1\right]$	$\begin{array}{r}{V}_{Dsat}\to V_{GS}-V_{TH}\\ \text{for }{E}_{c}L\gg V_{GS}-V_{TH}\end{array}$ $\begin{array}{r}{V}_{Dsat}\approx \sqrt{2E_{c}L\left(V_{GS}-V_{TH}\right)}\\ \text{for }{E}_{c}L\ll V_{GS}-V_{TH}\end{array}$	$\begin{array}{r}{V}_{Dsat}:\text{drain}\text{voltage}\text{at}\text{which}d{I}_D/d{V}_{DS}=0,\\ \text{i.e.}\text{where}\text{the}\text{carriers}\text{at}\text{the}\text{drain}\text{end}\\ \text{reach}{v}_{sat}\end{array}$ $\begin{array}{r}\text{(smaller than the long-channel value }{V}_{GS}-V_{TH}\text{,}\\ \text{so the device saturates earlier)}\end{array}$
Saturation drain current with velocity saturation	$I_{Dsat}=\frac{{\mu }_n{C}_{ox}}{2}\frac{Z}{L}{V}_{Dsat}^2=Z{C}_{ox}{v}_{sat}\left(V_{GS}-V_{TH}-V_{Dsat}\right)$	$I_{Dsat}\approx Z{C}_{ox}{v}_{sat}\left(V_{GS}-V_{TH}\right)\left(E_{c}L\ll V_{GS}-V_{TH}\right)$ $\begin{array}{r}{I}_{Dsat}\to \frac{{\mu }_n{C}_{ox}}{2}\frac{Z}{L}{\left(V_{GS}-V_{TH}\right)}^2\\ \text{for }{E}_{c}L\gg V_{GS}-V_{TH}\end{array}$	$I_{Dsat}:\text{drain current in the saturation region}$ $\begin{array}{r}uses{E}_c=v_{sat}/{\mu }_n\text{;}\text{in}\text{the}\text{fully}\\ \text{velocity-saturated}\text{limit}\text{the}\text{current}\text{is}\\ \text{linear}\text{in}{V}_{GS}\text{and}\text{independent}\text{of}L\text{)}\end{array}$
Transconductance (velocity-saturated)	$g_m=Z{C}_{ox}{v}_{sat}$	$g_m={\mu }_n{C}_{ox}\frac{Z}{L}\left(V_{GS}-V_{TH}\right)\text{(long channel)}$	$\begin{array}{r}{g}_m:\text{saturation}\text{transconductance}\text{in}\text{the}\\ \text{fully}\text{velocity-saturated}\text{limit,}\\ \text{independent}\text{of}L\text{and}{V}_{GS}\end{array}$
Cutoff frequency (velocity-saturated)	$f_T=\frac{g_m}{2\pi C_G}\approx \frac{v_{sat}}{2\pi L}$	$C_G\approx C_{ox}ZL$ $f_T=\frac{3{\mu }_n\left(V_{GS}-V_{TH}\right)}{4\pi L^2}\text{(long channel)}$	$\begin{array}{r}{f}_T:\text{frequency}\text{at}\text{which}\text{the}\text{short-circuit}\\ \text{current}\text{gain}\text{falls}\text{to}\text{unity}\end{array}$ $\begin{array}{r}\text{(intrinsic}\text{value;}\text{neglects}\text{overlap}\text{and}\\ \text{fringing}\text{capacitance}\text{and}\text{any}\text{change}\text{in}\text{the}\\ \text{gate}\text{charge}\text{distribution)}\end{array}$
Output conductance with DIBL	$g_{ds}\approx \lambda I_{Dsat}+{\eta }_{DIBL}{g}_m$	$r_o=\frac{1}{g_{ds}}$	$\begin{array}{r}{g}_{ds}:\text{small-signal}\text{output}\text{conductance}\text{in}\\ \text{saturation}\end{array}$ $\begin{array}{r}\lambda I_{Dsat}:\text{channel-length modulation term}\\ \text{(see Long Channel MOSFET page)}\end{array}$ $\begin{array}{r}{\eta }_{DIBL}{g}_m:\text{term from the shift of }{V}_{TH}\text{ with }{V}_{DS}\end{array}$
Source/drain series resistance	$g_{m,ext}=\frac{g_m}{1+g_m{R}_S}$	$\begin{array}{r}{V}_{GS,int}=V_{GS}-I_D{R}_S\\ V_{DS,int}=V_{DS}-I_D\left(R_S+R_D\right)\end{array}$	$g_{m,ext}:\text{extrinsic transconductance}$ $R_S,R_D:\text{source and drain series resistances}$ $\begin{array}{r}\text{(neglects}{g}_{ds}\text{;}\text{series}\text{resistance}\text{becomes}\\ \text{more}\text{significant}\text{as}\text{the}\text{intrinsic}\text{channel}\\ \text{resistance}\text{falls}\text{with}L\text{)}\end{array}$
Hot-carrier substrate current (lucky-electron model)	$\frac{I_{sub}}{I_D}=C_1\exp \left(-\frac{{\varphi }_{it}}{q{\lambda }_{mfp}{E}_m}\right)$	$\frac{I_G}{I_D}=C_2\exp \left(-\frac{{\varphi }_b}{q{\lambda }_r{E}_m}\right)$ $E_m\approx \frac{V_{DS}-V_{Dsat}}{l_d}$	$\begin{array}{r}{I}_{sub}:\text{substrate}\text{current}\text{from}\text{impact}\\ \text{ionization}\text{near}\text{the}\text{drain}\end{array}$ $\begin{array}{r}{I}_G:\text{gate}\text{current}\text{from}\text{hot-electron}\\ \text{injection}\text{into}\text{the}\text{oxide}\end{array}$ $C_1,C_2:\text{fitting constants}$ $\begin{array}{r}{\varphi }_{it}:\text{impact-ionization}\text{threshold}\text{energy}\\ \text{(}\approx 1.3\mathrm{eV}\text{in}\text{Si)}\end{array}$ ${\varphi }_b:{\text{Si/SiO}}_2\text{electron injection barrier height}$ $\begin{array}{r}{\lambda }_{mfp},{\lambda }_r:\text{electron}\text{scattering}\text{and}\\ \text{redirection}\text{mean}\text{free}\text{paths}\end{array}$ $E_m:\text{maximum lateral channel field near the drain}$ $\begin{array}{r}{l}_d:\text{characteristic}\text{length}\text{of}\text{the}\\ \text{high-field}\text{region}\text{(empirically}\text{scales}\text{as}\\ t_{ox}^{1/3}{x}_j^{1/2}\text{)}\end{array}$
Constant-field (Dennard) scaling	$\begin{array}{r}L,Z,t_{ox},x_j\to \frac{1}{\kappa }\\ V_{DD},V_{TH}\to \frac{1}{\kappa }\\ N_A\to \kappa N_A\end{array}$	$\begin{array}{r}{I}_D\to \frac{I_D}{\kappa },C_G\to \frac{C_G}{\kappa }\\ \text{gate delay}\to \frac{1}{\kappa }\\ \text{power per device}\to \frac{1}{{\kappa }^2}\\ \text{power density unchanged}\end{array}$ $\ell \to \frac{\ell }{\kappa },\frac{L}{\ell }\text{unchanged}$	$\kappa :\text{scaling factor }(\kappa >1)$ $x_j:\text{source/drain junction depth}$ $\begin{array}{r}\text{(all}\text{electric}\text{fields}\text{are}\text{unchanged;}\text{the}\\ \text{thermal}\text{voltage}{k}_{B}T/q\text{does}\text{not}\text{scale,}\text{so}\\ \text{the}\text{subthreshold}\text{swing}\text{and}\text{leakage}\text{do}\text{not}\\ \text{improve)}\end{array}$ $k_B:Boltzmannconstant$

Important Questions

Ques: What distinguishes a short-channel MOSFET from a long-channel MOSFET?

A MOSFET behaves as a long-channel device when the gate alone controls the potential in the channel, so the gradual-channel approximation holds and the drain only affects the device through the pinch-off region. As $L$ approaches the source/drain depletion widths $W_S$ and $W_D$, or equivalently the scale length $\ell$, the source and drain junctions start to share control of the depletion charge under the gate, and the lateral electric field becomes large enough to saturate the carrier velocity. The result is a set of deviations from the Long Channel MOSFET page: $V_{TH}$ falls with decreasing $L$ (roll-off) and with increasing $V_{DS}$ (DIBL), the subthreshold swing degrades, the current saturates at a lower $V_{Dsat}$ and becomes linear in $V_{GS}-V_{TH}$, and carriers reach energies high enough to cause impact ionization and oxide damage. Reference: S.M. Sze and Kwok K. Ng, Physics of Semiconductor Devices, 3rd ed., Wiley, 2007; Y. Taur and T.H. Ning, Fundamentals of Modern VLSI Devices, 2nd ed., Cambridge University Press, 2009.

Ques: Why does the threshold voltage drop as the channel gets shorter and as the drain voltage increases?

Two mechanisms are responsible, and they are often confused. In the charge-sharing picture, part of the depletion charge below the gate is already balanced by the source and drain junctions, so the gate needs to supply less charge and $V_{TH}$ falls as $L$ decreases (the Yau expression above). In the DIBL picture, a positive drain voltage lowers the potential barrier between the source and the channel, so less gate voltage is needed to inject carriers, and $V_{TH}$ falls with increasing $V_{DS}$. At very short $L$ the DIBL effect dominates and it grows roughly as $\exp (-L/2\ell )$, which is why thin oxides (small $\ell$) are needed to keep it small. Some devices show the opposite trend at moderately short $L$, called the reverse short-channel effect, caused by dopant redistribution near the source and drain (for example from halo or pocket implants). Reference: L.D. Yau, “A simple theory to predict the threshold voltage of short-channel IGFET’s,” Solid-State Electronics 17, 1059 (1974); Y. Taur and T.H. Ning, Fundamentals of Modern VLSI Devices, 2nd ed., Cambridge University Press, 2009.

Ques: Why does the saturation current become linear in the gate overdrive, and why does $g_m$ stop depending on $L$?

In a long-channel device the current saturates because the inversion charge goes to zero at the drain end (pinch-off). In a short-channel device the lateral field near the drain is large enough that the carrier velocity reaches $v_{sat}$ before pinch-off occurs. The current is then set by the product of the gate-induced charge and a fixed velocity, $I_{Dsat}\approx Z{C}_{ox}{v}_{sat}(V_{GS}-V_{TH})$, which is first order in the overdrive and does not contain $L$. The transconductance $g_m=Z{C}_{ox}{v}_{sat}$ therefore no longer improves as the channel is shortened, so the benefit of scaling comes mainly from the reduction in gate capacitance and the corresponding rise in $f_T\approx v_{sat}/2\pi L$. Reference: S.M. Sze and Kwok K. Ng, Physics of Semiconductor Devices, 3rd ed., Wiley, 2007.

Ques: What are hot carriers, and why do they degrade the device?

Near the drain end of a short channel the lateral field is highest, so a small fraction of electrons gain much more energy than the lattice. Some of these “lucky” electrons ionize atoms in the lattice, producing the substrate current $I_{sub}$ (a convenient monitor of hot-carrier stress), and some are injected over the Si/SiO${}_2$ barrier into the oxide, producing gate current and creating interface traps and trapped oxide charge. This shifts $V_{TH}$, lowers $g_m$ and degrades the subthreshold swing over time. Because $E_m$ rises with $V_{DS}$ and with shorter $L$, the effect grows rapidly with scaling unless the supply voltage is reduced or the drain field is relieved, for example with lightly doped drain (LDD) structures. Reference: C. Hu et al., “Hot-electron-induced MOSFET degradation - model, monitor, and improvement,” IEEE Trans. Electron Devices 32, 375 (1985).

Ques: Why can’t constant-field scaling be continued indefinitely?

Constant-field scaling assumes all voltages and dimensions shrink together, so fields, current per unit width and power density are kept constant. However, the thermal voltage $k_{B}T/q$ is fixed, so the subthreshold swing cannot scale: if $V_{TH}$ is reduced by $\kappa$, the off-state current rises exponentially, and in practice $V_{TH}$ and $V_{DD}$ are scaled more slowly than the dimensions. The oxide cannot be thinned indefinitely either, because direct tunneling through it raises the gate leakage, and short-channel effects (roll-off, DIBL, punchthrough) require $L/\ell$ to stay roughly constant, which requires higher doping and shallower junctions. These limits motivate modified scaling rules, high-$k$ gate dielectrics and non-planar structures. Reference: R.H. Dennard et al., “Design of ion-implanted MOSFET’s with very small physical dimensions,” IEEE J. Solid-State Circuits 9, 256 (1974); Y. Taur and T.H. Ning, Fundamentals of Modern VLSI Devices, 2nd ed., Cambridge University Press, 2009.

Related pages in this vault: Long Channel MOSFET, Metal Semiconductor Field Effect Transistor (MESFET), Junction Field Effect Transistor (JFET), Schottky Barrier and Dynamic Threshold_MOSFET, BSIM3 and BSIM4, SPICE Level 1-3 MOSFET Models, Surface-Potential Models (PSP and HiSIM), CMOS Logic Transistors, MOS Capacitor, Rapid Thermal Oxidation System, Beamline Ion Implanter, Rapid Thermal Processor.