1. Theory
- Definition: An on-chip transformer is two or more magnetically coupled spiral windings in the interconnect layers, interwound in one layer or stacked in adjacent layers; a balun is a transformer, or a coupled-line or lumped network, that converts between an unbalanced signal and a balanced, differential pair (Long; Burdin et al.).
- Coupling: The mutual inductance is , and on-chip coupling coefficients of about 0.8 to 0.9 are achievable, against only about 0.6 for concentric spirals (Long).
- Turns ratio: The ratio follows the self-inductances, roughly the square of the turns, and step-up ratios are made by splitting a winding into parallel turns (Long).
- Loss: The winding resistances, with winding Q of about 5 or less in early silicon processes, and substrate loss limit the efficiency, giving minimum passband losses of about 2.6 to 2.7 for 1:1 designs at 2 to 2.5 (Long).
- Bandwidth: The magnetizing inductance sets the low cutoff, and the interwinding and substrate capacitance the self-resonance, so a transformer is broadband between the two (Long).
- Symmetry: Symmetric layouts with a centre tap give balanced outputs with phase errors of about 1 degree (Long).
2. Working Principle
- Magnetic coupling: Current in the primary produces a magnetic field that links the secondary, inducing a voltage proportional to the rate of change of the primary current, (background knowledge; Long).
- Leakage and magnetizing inductance: The flux that does not link both windings appears as leakage inductance in series, and the shared flux as a magnetizing inductance in shunt, which an ideal transformer then scales by the turns ratio (Long; background knowledge for the circuit).
- Interwinding capacitance: Adjacent or stacked turns of the two windings form a distributed capacitance that couples the windings electrically, producing a notch in the noninverting connection and setting the self-resonance (Long).
- Balun action: Driving one end of the primary against ground induces a secondary voltage that a centre tap divides into two equal halves of opposite sign, so the outputs are balanced to the extent that the windings are symmetric (Long).
- Power combining: Several push-pull stages can drive primary slabs whose secondaries are in series, so their voltages add on one load while each stage sees a fraction of it (Aoki et al.).
3. Applications
- Differential interfaces: Single-ended to differential conversion at LNA inputs, mixer RF and LO ports and PA outputs, where a transformer balun also provides DC isolation and impedance transformation in a small area (Long).
- Fully integrated power amplifiers: On-chip power combining and output matching, as in the distributed active transformer (Aoki et al.).
- Transformer feedback and coupling: Transformer feedback in low-noise amplifiers and interstage coupling in transformer-coupled mixers and amplifiers at low supply voltages (Long).
- Current status: Transformer baluns are standard in RF CMOS up to about tens of GHz; at 60 to 100 transmission-line baluns such as rat-race couplers are often used instead, because transformers become harder to design and model there (Burdin et al.).
Coupling and Equivalent Circuit
| Name | Formula | Related Formulae | Variables/Constants |
|---|---|---|---|
| Mutual inductance and coupling coefficient | |||
| Equivalent circuit with magnetizing and leakage inductance | |||
| Series and shunt connection of coupled windings |
Loss and Bandwidth
| Name | Formula | Related Formulae | Variables/Constants |
|---|---|---|---|
| Maximum available efficiency of a transformer | |||
| Bandwidth, low cutoff and resonant tuning |
Baluns and Power Combining
| Name | Formula | Related Formulae | Variables/Constants |
|---|---|---|---|
| Balun amplitude and phase balance | |||
| Series power combining in a distributed active transformer |
Important Questions
Ques: Which on-chip transformer layout gives the highest coupling coefficient?
Long compares four. Stacked overlay windings of the Finlay type use broadside and edge coupling in adjacent metal layers and reach about with about 1 of dielectric, in about half the area for the same self-inductance, but they are electrically asymmetric because the lower winding is closer to the substrate (background knowledge). Interwound identical spirals of the Frlan type give matched windings, with coupling of about 0.8 typical of Long’s designs, edge-coupled Shibata windings have unequal self-inductances, and concentric spirals reach only about 0.6, which suits peaking coils rather than transformers. Long finds that three to four turns per winding maximize , with the narrowest practical lines and near-minimum spacing, since the coupling gain outweighs the extra interwinding capacitance. Reference: J. R. Long, ‘Monolithic Transformers for Silicon RF IC Design’, IEEE J. Solid-State Circuits 35(9), 1368-1382 (2000) (copy hosted by the Aristotle University of Thessaloniki; many equations lost in the extract) (fetch-tool summary).
Ques: How much loss does an on-chip transformer add?
A useful bound is the maximum available efficiency, with (background knowledge). With and windings of Q 5, typical of Long’s early silicon designs, it is 0.61, a loss of 2.1 , while Q of 10 gives 1.1 and with Q of 10 gives 0.96 (computed). Long predicts minimum passband attenuation of 2.7 for a 1:1 Frlan transformer at 2 and 2.6 for a 1:1 Finlay transformer at 2.5 , 54 to 55 per cent of the power (computed), somewhat below the bound because the terminations are 50 rather than optimum and the substrate adds loss (my reading). Higher coupling and Q, from thick top metal, therefore matter most. Reference: J. R. Long, ‘Monolithic Transformers for Silicon RF IC Design’, IEEE J. Solid-State Circuits 35(9), 1368-1382 (2000) (copy hosted by the Aristotle University of Thessaloniki; many equations lost in the extract) (fetch-tool summary).
Ques: Is the winding resistance in Long’s 7 nH design example 7.5 or 75 ohms?
The extract states that 10 lines with four turns give about 400 outer diameter, a 5 unwound length and about 7.5 at 0.15 . A 5 line of 10 width has 500 squares, so 0.15 gives 75 and 7.5 requires 0.015 (computed). The process example in the same paper has 2 of top metal, and aluminium of that thickness has a sheet resistance of about 0.014 (background knowledge), so 0.015 and 7.5 are the more likely values, with the 0.15 a lost digit in the extraction (my reading). At 7.5 the 7 winding has of about 11.7 at 2 (computed), before substrate loss lowers it toward the Q of about 5 that Long quotes for windings. Reference: J. R. Long, ‘Monolithic Transformers for Silicon RF IC Design’, IEEE J. Solid-State Circuits 35(9), 1368-1382 (2000) (copy hosted by the Aristotle University of Thessaloniki; many equations lost in the extract) (fetch-tool summary); Planar Spiral Inductors page of this vault.
Ques: How does a transformer balun produce balanced outputs, and how good is the balance?
The unbalanced input drives the primary against ground, and the secondary voltage is split by a centre tap into two halves of opposite sign. Balance therefore depends on the symmetry of the windings and of their capacitance to the substrate. Long’s square symmetric 4:5 balun, with its centre tap precisely located and all four terminals on the outer edge, was tuned by 425 at the primary and 1.7 at each secondary to resonate near 2.4 , implying 10.3 and 2.6 (computed). Tuning lowered the transmission loss from over 5 to close to the ideal 3 per output, with a phase error of about 1 degree from 2 to 3 . A trifilar balun of 500 side kept low amplitude and phase errors from 1 to 4 when driven differentially. Reference: J. R. Long, ‘Monolithic Transformers for Silicon RF IC Design’, IEEE J. Solid-State Circuits 35(9), 1368-1382 (2000) (copy hosted by the Aristotle University of Thessaloniki; many equations lost in the extract) (fetch-tool summary).
Ques: How can on-chip transformers combine the power of several amplifiers?
Aoki et al. place several low-voltage push-pull amplifiers around a ring of primary slabs whose secondaries are connected in series, so their voltages add on one load. If stages each swing , the output power is and each stage sees about (background knowledge). Their 2.4 amplifier in 0.35 CMOS gave 2 at 41 per cent PAE from 2 and 450 from 1 , with 50 matching and harmonics at least 64 down. Delivering 2 to 50 needs 14.1 peak, about 3.5 from each of four stages (computed, assuming four), within the swing of a 2 push-pull pair. Virtual AC grounds and magnetic coupling also make the design less sensitive to bond-wire inductance. Reference: I. Aoki, S. Kee, D. Rutledge and A. Hajimiri, ‘Fully Integrated CMOS Power Amplifier Design Using the Distributed Active-Transformer Architecture’ (Caltech CHIC publication page; IEEE J. Solid-State Circuits 37(3), 2002, journal details background knowledge) (abstract only).
Ques: When is a transmission-line or lumped balun preferred over a transformer balun?
At millimetre-wave frequencies and where a narrowband response is acceptable. Burdin et al. note that transformers become hard to design and model at 60 to 100 because of low coupled-inductor efficiency and parasitic capacitance, and their 65 CMOS rat-race balun with slow-wave lines covers 51 to 67 with return loss below -15 , a phase difference of 175.9 degrees, plus or minus 0.4, and 0.085 of area. At 10 , Pakasiri et al. use a lumped Wilkinson-type balun with left- and right-handed sections in 0.18 CMOS, with 1.98 insertion loss and 16.8 isolation; 1.98 leaves 63 per cent of the power (computed). A transformer balun stays more compact and broadband at lower frequencies, and also gives DC isolation and impedance transformation (Long). Reference: F. Burdin, F. Podevin, B. Blampey, N. Corrao, E. Pistono and P. Ferrari, ‘Millimeter-wave Rat-race Balun in a CMOS 65 nm Technology with Slow-wave Transmission Lines and Innovative Topology’, PIERS 2012 Moscow proceedings (fetch-tool summary); C. Pakasiri, J.-L. Xu and S. Wang, ‘A 10 GHz Compact Balun with Common Inductor on CMOS Process’, Electronics 12(2), 468 (2023), doi:10.3390/electronics12020468 (fetch-tool summary of a truncated text); J. R. Long, ‘Monolithic Transformers for Silicon RF IC Design’, IEEE J. Solid-State Circuits 35(9), 1368-1382 (2000) (copy hosted by the Aristotle University of Thessaloniki; many equations lost in the extract) (fetch-tool summary).
Related pages in this vault: Planar Spiral Inductors, On-Chip Transmission Lines, AC Circuits and Impedance, Vector Network Analyzer (VNA), Magnetism, Flux and Inductance, Magnetic Materials and Magnetic Circuits.