1. Theory

  • Definition: A planar spiral inductor is a metal line wound in a square, hexagonal, octagonal or circular spiral in the top interconnect layers, with an underpass or crossover to bring out the inner terminal, used as an integrated inductance of about 0.5 to 100 (Mohan et al.; Allen).
  • Inductance: The inductance grows roughly as the square of the number of turns times the average diameter and falls as the spiral fills in, which the modified Wheeler, current-sheet and monomial expressions capture within a few per cent (Mohan et al.; Papadopoulos and Antonopoulos).
  • Quality factor: Q is limited by the metal resistance, raised further by skin and proximity effects, and by electric and magnetic losses in the silicon substrate, so on-chip values are typically about 5 to 20 against 40 or more on glass (Niknejad; Allen; Yue and Wong).
  • Self-resonance: The capacitance between turns and to the substrate resonates with the inductance at , above which the device is no longer inductive (Allen; Niknejad).
  • Substrate dependence: Lightly doped substrates lose energy mainly through the electric field, heavily doped ones through induced eddy currents, which also reduce the inductance (Niknejad; Sonnet).
  • Shielding: A patterned ground shield of slotted polysilicon or metal under the spiral terminates the electric field without carrying eddy currents (Yue and Wong 1998; Sonnet).

2. Working Principle

  • Self and mutual inductance: Each segment contributes self-inductance, and parallel segments in neighbouring turns carrying current in the same direction add mutual inductance, while segments on opposite sides subtract it; the hollow centre keeps the opposing segments far apart (Mohan et al.; background knowledge for the segment picture).
  • Conductor loss: At high frequency the current crowds to the surface and to the inner edges of the turns, so the resistance rises above its DC value and wide lines stop helping (Allen; Yue and Wong).
  • Substrate loss: The voltage on the spiral drives displacement current through the oxide into the resistive silicon, and the changing magnetic field induces eddy currents in it; both dissipate energy and lower Q (Niknejad; Yue and Wong).
  • Shield action: The shield is slotted perpendicular to the spiral so that image currents cannot circulate, while it still grounds the electric field before it reaches the silicon (Yue and Wong 1998; Sonnet).

3. Applications

  • LC oscillators: Tank inductors of voltage-controlled oscillators, where the inductor Q usually sets the tank Q and the phase noise (Allen; Yue and Wong 1998).
  • Matching and loads in RF front ends: Input matching of low-noise amplifiers, interstage and output matching of power amplifiers, and tuned loads (background knowledge).
  • Bandwidth extension: Shunt and series peaking inductors in broadband amplifiers and drivers (background knowledge).
  • Current status: Spiral inductors in thick top metal are standard devices in RF CMOS, BiCMOS and SiGe processes, such as the inductor2 and inductor3 cells of IHP SG13G2 in TopMetal2 (IHP).

Inductance Expressions

NameFormulaRelated FormulaeVariables/Constants
Modified Wheeler expression






Current-sheet expression
Data-fitted monomial expression


Losses and Quality Factor

NameFormulaRelated FormulaeVariables/Constants
Series resistance with skin effect









Lumped pi model and quality factor








Self-Resonance and Substrate

NameFormulaRelated FormulaeVariables/Constants
Self-resonance frequency




Substrate eddy currents and skin depth in silicon







Patterned ground shield

Important Questions

Ques: How accurate are the simple spiral inductance expressions for a real design?

Mohan et al. report typical errors of about 2 to 3 per cent against the ASITIC field solver over 19,000 inductors and about 5 per cent against measurements, against about 20 per cent for earlier expressions. Applied to Allen’s ASITIC design of 3.5 turns, 200 outer diameter, 19 width and 1 spacing, the modified Wheeler, current-sheet and monomial expressions give 1.93, 1.92 and 1.94 against the simulated 2.06 , about 6.4 per cent lower (computed). The three agree with each other within 1 per cent, so the difference probably comes from the inner diameter of about 62 that I derived for a 3.5-turn layout (assumed) and from the leads and underpass included in the simulation (my reading). The expressions are therefore best used for first sizing, followed by an electromagnetic simulation. Reference: S. S. Mohan, M. del Mar Hershenson, S. P. Boyd and T. H. Lee, ‘Simple Accurate Expressions for Planar Spiral Inductances’, IEEE J. Solid-State Circuits 34(10), 1419-1424 (1999) (author PDF at Stanford; equations and coefficient tables did not come through the fetch tool, fetch-tool summary of the text); P. E. Allen, ECE 6440 lecture L045, inductor design in silicon technology, Georgia Tech, Summer 2003 (title from the file name; equations partly garbled) (fetch-tool summary).

Ques: Is the logarithm in the current-sheet expression ln(2.07/rho) or ln(2.07 rho)?

Mohan et al. write the current-sheet expression as with for square spirals (background knowledge, since the equation did not come through the fetch tool), while the text of Papadopoulos and Antonopoulos as read gives . The second form becomes negative for below 0.48 (computed), which would give a negative inductance for a hollow spiral. For the example spiral with it gives 0.28 against 1.92 with (computed). Since the same paper reports a mean error of only 0.63 per cent for this expression, its calculations must have used the division (my reading), so is the more likely correct form, and the product is probably a typesetting or extraction error. Reference: S. S. Mohan, M. del Mar Hershenson, S. P. Boyd and T. H. Lee, ‘Simple Accurate Expressions for Planar Spiral Inductances’, IEEE J. Solid-State Circuits 34(10), 1419-1424 (1999) (author PDF at Stanford; equations and coefficient tables did not come through the fetch tool, fetch-tool summary of the text); T. Papadopoulos and A. Antonopoulos, ‘Extension of Simple and Accurate Inductance Estimation for Rectangular Planar Windings’, arXiv:2507.16982v1 (2025) (fetch-tool summary).

Ques: Does a patterned ground shield raise Q by 33 per cent or by about 15 per cent?

Both are reported, under different conditions. Yue and Wong found improvements of up to 33 per cent at 1 to 2 with a polysilicon shield, nearly doubling the Q of a 2 LC tank and reducing coupling between adjacent inductors by up to 25 . Sonnet’s simulation of a spiral 11 above a 12.5 substrate gives a rise in peak Q from 12.4 to 14.2, 14.5 per cent (computed), with the peak moving from 8.2 to 9.2 and self-resonance falling from 25.2 to 23.6 . The gain depends on how much of the loss is electric coupling to the substrate, and Niknejad warns that a shield can lower Q where that loss does not dominate. For a typical layout, about 15 per cent is the more likely gain at peak Q, and 33 per cent an upper value (my reading). Reference: C. P. Yue and S. S. Wong, ‘On-chip spiral inductors with patterned ground shields for Si-based RF ICs’, IEEE J. Solid-State Circuits 33(5), 743-752 (1998) (abstract as summarized by SciSpace and the HKUST news page); J. C. Rautio, J. D. Merrill and M. J. Kobasa (Sonnet Software), ‘Efficient Electromagnetic Analysis of Spiral Inductor Patterned Ground Shields’ (venue and year not in the text, about 2011 to 2012) (fetch-tool summary); A. M. Niknejad, ‘Analysis, Simulation, and Applications of Passive Devices on Conductive Substrates’, PhD dissertation, UC Berkeley, Memorandum UCB/ERL M00/31 (2000) (fetch-tool summary of a truncated text).

Ques: Why does the substrate resistivity change the losses of a spiral inductor?

Because the electric and magnetic fields couple differently. Niknejad notes that bipolar and BiCMOS substrates of 10 to 20 lose energy mainly through the electric field in the 1 to 10 range, while heavily doped epi-CMOS bulk substrates are conductive enough for eddy currents to dominate and to act like a ground plane that lowers the inductance. Sonnet places the change between about 80 (1.25 ), below which capacitive effects dominate, and 800 (0.125 ), where the substrate currents are mainly inductive and a shield no longer helps. The skin depth at 5 explains this: about 2.25 in 10 silicon, far more than the wafer, but 250 at 0.125 and 71 at 0.01 (computed). Reference: A. M. Niknejad, ‘Analysis, Simulation, and Applications of Passive Devices on Conductive Substrates’, PhD dissertation, UC Berkeley, Memorandum UCB/ERL M00/31 (2000) (fetch-tool summary of a truncated text); J. C. Rautio, J. D. Merrill and M. J. Kobasa (Sonnet Software), ‘Efficient Electromagnetic Analysis of Spiral Inductor Patterned Ground Shields’ (venue and year not in the text, about 2011 to 2012) (fetch-tool summary).

Ques: What limits the useful frequency range of a spiral inductor, and how is it checked?

The self-resonance frequency, at which the shunt capacitance between turns and to the substrate resonates with the inductance. Allen’s ASITIC example for a 2 tank with 3 needs 2.11 (computed), and the chosen 3.5-turn spiral gives 2.06 , Q of 7.11 and of 9.99 . That resonance requires 123 of shunt capacitance (computed), the same as the first capacitance of the extracted pi model, which supports reading it as the total at one port (my reading). Since Q falls to zero at and peaks well below it, the operating frequency is usually kept several times lower. Allen recommends outer diameters below about 200 , because larger spirals add substrate capacitance, and Niknejad notes that a thicker oxide under the spiral raises . Reference: P. E. Allen, ECE 6440 lecture L045, inductor design in silicon technology, Georgia Tech, Summer 2003 (title from the file name; equations partly garbled) (fetch-tool summary); A. M. Niknejad, ‘Analysis, Simulation, and Applications of Passive Devices on Conductive Substrates’, PhD dissertation, UC Berkeley, Memorandum UCB/ERL M00/31 (2000) (fetch-tool summary of a truncated text).

Ques: What quality factors do on-chip spiral inductors reach?

Typically about 5 to 20 on standard silicon. Allen’s 2.06 design reaches 7.11 at 2 , an effective series resistance of 3.6 (computed), against a DC resistance of about 1.3 for an assumed 2 aluminium line (computed), so skin effect and substrate loss take more than half. Niknejad’s review lists 17.6 at 11.25 for 1.96 on a 2 substrate with 3.1 metal, 12 at 3.5 for 2.8 , 21 for 3.5 and 20 for 2 with buried-oxide isolation, and up to 40 at 5 on glass. Sonnet’s simulated spiral peaks at 12.4 without a shield. Thicker metal lowers the sheet resistance from about 55 to 7 for 0.5 to 4 aluminium, which is why inductors use the thick top metal. Reference: P. E. Allen, ECE 6440 lecture L045, inductor design in silicon technology, Georgia Tech, Summer 2003 (title from the file name; equations partly garbled) (fetch-tool summary); A. M. Niknejad, ‘Analysis, Simulation, and Applications of Passive Devices on Conductive Substrates’, PhD dissertation, UC Berkeley, Memorandum UCB/ERL M00/31 (2000) (fetch-tool summary of a truncated text); J. C. Rautio, J. D. Merrill and M. J. Kobasa (Sonnet Software), ‘Efficient Electromagnetic Analysis of Spiral Inductor Patterned Ground Shields’ (venue and year not in the text, about 2011 to 2012) (fetch-tool summary).

Related pages in this vault: On-Chip Transformers and Baluns, On-Chip Transmission Lines, MIM and MOM Capacitors, Through-Silicon Vias as Passives, Diffused and Implanted Resistors, Magnetism, Flux and Inductance, Polysilicon Resistors, MOS and Poly-Insulator Capacitors, Vector Network Analyzer (VNA).