On-Chip Transmission Lines

1. Theory

• Definition: An on-chip transmission line is a signal conductor in the interconnect stack with a defined return path, either a ground plane in a lower metal (microstrip) or ground strips beside it in the same layer (coplanar waveguide, CPW), used where the line is a significant fraction of a wavelength (Steer; Niknejad and Brodersen).
• Characteristic impedance: The impedance $Z_0=\sqrt{L/C}$ follows from the geometry and dielectric, set by width to height for microstrip and by width to gap for CPW (Steer).
• Loss and Q: The loss is mainly conductor loss in thin metals, plus substrate loss for CPW fields that reach the silicon; the line Q, $\beta /2\alpha$, reaches about 14 to 16 for standard lines at 60 $\mathrm{GHz}$ in CMOS (Venter et al.).
• Substrate modes: A line over oxidized silicon can run in dielectric quasi-TEM, slow-wave or skin-effect mode depending on the substrate conductivity, frequency and thickness (Tuncer and Neikirk).
• Slow-wave lines: Floating shield strips under a CPW raise the capacitance per length and shorten the wavelength while blocking the substrate, giving Q above 30 at 60 $\mathrm{GHz}$ with effective permittivities of 21 to 57 (Venter et al.).

2. Working Principle

• Wave propagation: Distributed series inductance and shunt capacitance carry a wave at a phase velocity of $1/\sqrt{LC}$, while series resistance and shunt conductance attenuate it (background knowledge; Venter et al.).
• Microstrip: The field is held between the strip and a lower metal ground, so the silicon is shielded and losses come mainly from the thin strip and ground metals (Niknejad and Brodersen; Venter et al.).
• Coplanar waveguide: The field spreads between the centre strip and ground strips in the same layer; the gap sets the impedance, and wide gaps let the field reach the lossy silicon (Steer; Venter et al.).
• Slow-wave action: The shield strips, narrow and cut perpendicular to the line, terminate the electric field close to the signal without carrying longitudinal current, so the capacitance rises while the magnetic field and inductance are hardly affected (Venter et al.).
• Substrate as a conductor: Below the dielectric relaxation frequency, charge in the silicon screens the electric field, so the silicon acts as a lossy lower plate, and at high conductivity eddy currents in it add series loss (Tuncer and Neikirk).

3. Applications

• Millimetre-wave matching networks: Quarter-wave and stub matching, and short lines as inductors to tune out device capacitance in amplifiers and oscillators above about 30 $\mathrm{GHz}$ (Niknejad and Brodersen).
• Couplers, baluns and filters: Rat-race and branch-line couplers, baluns and filters at 60 $\mathrm{GHz}$ and above, made compact by slow-wave lines (Burdin et al.).
• Routing of high-frequency signals: Clock and LO distribution and connections to pads where the line length approaches a wavelength (background knowledge).
• Current status: Microstrip, CPW and slow-wave CPW are standard elements of mm-wave CMOS and BiCMOS design, with lumped spirals preferred below about 10 to 20 $\mathrm{GHz}$, where lines become long (background knowledge; Planar Spiral Inductors page).

Line Parameters

Name	Formula	Related Formulae	Variables/Constants
Propagation constant and characteristic impedance	$\gamma =\alpha +j\beta =\sqrt{\left(R+j\omega L\right)\left(G+j\omega C\right)},Z_0=\sqrt{\frac{R+j\omega L}{G+j\omega C}}$	$\gamma =\frac{1}{l}{\cosh }^{-1}\left(\frac{A+D}{2}\right),Z_0=\sqrt{\frac{B}{C_{ABCD}}}$	$\gamma :propagationconstant$ $\alpha :attenuationconstant$ $\beta :phaseconstant$ $\begin{array}{r}R,L,G,C:seriesresistance,inductance,\\ shuntconductanceandcapacitanceperunit\\ length\end{array}$ $\omega :angularfrequency$ $Z_0:characteristicimpedance$ $l:linelength,A,B,C_{ABCD}$ $\begin{array}{r}D:ABCDparametersofthemeasuredline\\ (telegrapherform,backgroundknowledge);\\ Venteretal.:extractionfrommeasuredor\\ simulatedABCDparametersof300\mu \mathrm{m}lines\\ upto110\mathrm{GHz}inAMSC35(fourmetals,\\ about3\mu \mathrm{m}thickM4)\end{array}$ $(nocomputedvalue)$
Attenuation, quality factor and effective permittivity	$Q=\frac{\beta }{2\alpha },{\epsilon }_{eff}={\left(\frac{c_0\beta }{\omega }\right)}^2$	$\alpha [dB/mm]=8.686\alpha [Np/mm],{\lambda }_g=\frac{c_0}{f\sqrt{{\epsilon }_{eff}}}$	$Q:qualityfactoroftheline$ ${\epsilon }_{eff}:effectivepermittivity$ $c_0:speedoflightinvacuum$ ${\lambda }_g:guidedwavelength$ $\begin{array}{r}f:frequency;Venteretal.(60\mathrm{GHz},\\ measuredagainstsimulated):slow-waveCPW\\ linesof0.86against0.82,1.06against\\ 1.19,1.15against1.33and1.42against\\ 1.51dB/mmwith{\epsilon }_{eff}of21,37.3,50.5and\\ 56.5;standardCPWpeaksatQabout14\\ near69\Omega ,standardmicrostripat15.6\\ near45to55\Omega ,andslow-waveCPWabove\\ 30;Burdinetal.:a45\Omega slow-waveCPWin\\ 65\mathrm{nm}CMOSwith{\epsilon }_{eff}of12.5andQof24at\\ 60\mathrm{GHz}\end{array}$ $\begin{array}{r}(computed:thefourVenterlinesgive\beta =\\ 5.8to9.4rad/mmandQ=29,31,34and\\ 29,consistentwiththestatedpeakabove\\ 30;Burdi{n}^{\prime }sQof24impliesabout0.80\\ dB/mm;{\lambda }_{g}at60\mathrm{GHz}is1.09\mathrm{mm}for{\epsilon }_{eff}=21\\ and0.67\mathrm{mm}for56.5,against2.5\mathrm{mm}for\\ {\epsilon }_{eff}=4)\end{array}$
Conductor and dielectric loss of a quasi-TEM line	$\alpha \approx \frac{R}{2Z_0}+\frac{G{Z}_0}{2}$	$Q\approx \frac{\omega L}{R}(G\to 0),R\propto \sqrt{f}(\text{skin effect})$	$\begin{array}{r}R,G:seriesresistanceandshunt\\ conductanceperunitlength\end{array}$ $Z_0:characteristicimpedance$ $\begin{array}{r}L:inductanceperunitlength(low-loss\\ approximation,backgroundknowledge);\\ Venteretal.:theattenuationismodelled\\ asaresistivetermfromthestripand\\ eddycurrentsplusatermproportionalto\\ {\omega }^2{R}_p{C}_{l}fromtheresistance{R}_{p}oftheshielding\\ strips;standardCPWlosesQforwidegaps\\ asthefieldentersthelossysilicon,and\\ inslow-wavelinesthepeakQfallsat\\ largegroundspacingbecausethestrip\\ widensandthecapacitancerises\end{array}$ $(nocomputedvalue)$

Microstrip and Coplanar Waveguide

Name	Formula	Related Formulae	Variables/Constants
Microstrip synthesis	$\frac{w}{h}={\left(\frac{e^{H^{\prime }}}{8}-\frac{1}{4e^{H^{\prime }}}\right)}^{-1},H^{\prime }=\frac{Z_0\sqrt{2\left({\epsilon }_r+1\right)}}{119.9}+\frac{1}{2}\frac{{\epsilon }_r-1}{{\epsilon }_r+1}\left(\ln \frac{\pi }{2}+\frac{1}{{\epsilon }_r}\ln \frac{4}{\pi }\right)$	${\epsilon }_{eff}=\frac{{\epsilon }_r+1}{2}{\left[1+\frac{29.98}{Z_0}\sqrt{\frac{2}{{\epsilon }_r+1}}\frac{{\epsilon }_r-1}{{\epsilon }_r+1}\left(\ln \frac{\pi }{2}+\frac{1}{{\epsilon }_r}\ln \frac{4}{\pi }\right)\right]}^2$	$w:stripwidth$ $\begin{array}{r}h:dielectricheightabovetheground\\ plane,H^{\prime }:auxiliaryvariable\end{array}$ $Z_0:targetimpedance$ ${\epsilon }_r:relativepermittivityofthedielectric$ $\begin{array}{r}{\epsilon }_{eff}:effectivepermittivity;Steer:for{Z}_0\\ above(44-2{\epsilon }_r)\Omega ,withaseparate\\ wide-stripformbelow,accuratetobetter\\ than1percentfor8<{\epsilon }_r<12anduseful\\ outsidethatrangewithreducedaccuracy;\\ workedexample{Z}_0=75\Omega ,{\epsilon }_r=5.6,h=500\\ \mu \mathrm{m}:H^{\prime }about2.445,w/habout0.704and{\epsilon }_{eff}\\ about3.82;onchipthegroundplaneisa\\ lowermetalandhafewmicrometresof\\ oxide,sothelinesarenarrow(background\\ knowledge);NiknejadandBrodersen:\\ microstripshieldsthefieldsfromthe\\ substrate\end{array}$ $\begin{array}{r}(computed:theformulasreproduce{H}^{\prime }=\\ 2.445,w/h=0.704and{\epsilon }_{eff}=3.82)\end{array}$
Coplanar waveguide	$Z_0=\frac{30\pi }{\sqrt{{\epsilon }_{eff}}}\frac{K\left(k^{\prime }\right)}{K\left(k\right)},k=\frac{w}{w+2s},k^{\prime }=\sqrt{1-k^2}$	$\frac{K\left(k\right)}{K\left(k^{\prime }\right)}\approx \frac{1}{\pi }\ln \left(2\frac{1+\sqrt{k}}{1-\sqrt{k}}\right)(0\le k\le 0.707),{\epsilon }_{eff}\approx \frac{{\epsilon }_r+1}{2}$	$\begin{array}{r}K:completeellipticintegralofthefirst\\ kind,k,k^{\prime }:modulusandcomplementary\\ modulus\end{array}$ $w:centre-stripwidth$ $s:gaptothegroundstrips$ $\begin{array}{r}{\epsilon }_{eff}:effectivepermittivity;Steer:for\\ 0.707<k\le 1thesamelogarithmwith{k}^{\prime }\\ givesK(k^{\prime })/K(k)directly,afuller{\epsilon }_{eff}\\ expressionisaccurateto1.5percentfor\\ h/s\ge 1,andtheGaAsexamplewithw=500\\ \mu \mathrm{m}ands=200\mu \mathrm{m}hask=0.556,K(k)/K(k^{\prime })\\ about0.833,{\epsilon }_{eff}about6.28and{Z}_{0}about\\ 45.1\Omega (theproblemtextgivesa200\mu \mathrm{m}\\ strip,inconsistentwiththesolution);\\ NiknejadandBrodersen:the130\mathrm{nm}CMOS\\ mm-wavedesignsatBerkeleyusedCPW,with\\ thesignal-to-groundspacingsetting{Z}_{0}and\\ confiningthefields,bridgessuppressing\\ theoddmode,andCPWrealizinghigher-Q\\ inductivelinesfortuningoutdevice\\ capacitance\end{array}$ $\begin{array}{r}(computed:k=0.556givesK(k)/K(k^{\prime })=\\ 0.833and,with{\epsilon }_{eff}=6.28,Z_0=45.1\Omega )\end{array}$

Substrate Effects and Slow-Wave Lines

Name	Formula	Related Formulae	Variables/Constants
Modes of a microstrip on oxidized silicon	$f_{rel}=\frac{{\sigma }_{si}}{2\pi {\epsilon }_0{\epsilon }_{si}},{\delta }_{si}=\sqrt{\frac{2}{\omega {\mu }_0{\sigma }_{si}}}$	$\text{dielectric quasi-TEM: }f\gg f_{rel};\text{slow-wave: }f<f_{rel},{\delta }_{si}>t_{si};\text{skin-effect: }{\delta }_{si}<t_{si}$	$\begin{array}{r}{f}_{rel}:dielectricrelaxationfrequencyofthe\\ silicon\end{array}$ ${\sigma }_{si}:substrateconductivity$ $\begin{array}{r}{\epsilon }_{si}:relativepermittivityofsilicon\\ (11.7)\end{array}$ ${\delta }_{si}:skindepthinsilicon$ $\begin{array}{r}{t}_{si}:substratethickness(modeboundaries\\ inthisform,backgroundknowledgeafter\\ Hasegawaetal.);TuncerandNeikirk:in\\ theskin-effectmodethesubstrateis\\ thickerthantheskindepthandtheseries\\ resistancecauseslargeloss;belowthe\\ dielectricrelaxationfrequencythe\\ siliconbehaveslikeametalsheetforthe\\ electricfield,givingtheslow-wavemode;\\ for\omega above\sigma /\epsilon thesiliconactsasa\\ lossydielectric;near\omega about\sigma /\epsilon the\\ conductivityhasaverylargeeffecton\\ loss;theirquasi-staticmodelagreedwith\\ full-waveresultswithin5percentat1\\ \mathrm{GHz}for0.01to10S/cmandwithin20per\\ centfortheslow-wavefactorin\\ Hasegaw{a}^{\prime }s160\mu \mathrm{m}stripon1\mu \mathrm{m}SiO2and250\\ \mu \mathrm{m}silicon\end{array}$ $\begin{array}{r}(computed:f_{rel}=1.5\mathrm{GHz}for100\Omega \mathrm{cm},15\\ \mathrm{GHz}for10\Omega \mathrm{cm},154\mathrm{GHz}for1\Omega \mathrm{cm}and\\ 15\mathrm{THz}for0.01\Omega \mathrm{cm})\end{array}$
Slow-wave lines with floating shield strips	$v_p=\frac{1}{\sqrt{L_l{C}_l}}=\frac{c_0}{\sqrt{{\epsilon }_{eff}}},Z_0=\sqrt{\frac{L_l}{C_l}}$	$\text{S-CPW: }{C}_l\uparrow (L_l\text{kept}),\text{S-MS: }{L}_l\uparrow (C_l\text{kept})$	$v_p:phasevelocity$ $\begin{array}{r}{L}_l,C_l:inductanceandcapacitanceper\\ unitlength\end{array}$ $c_0:speedoflight$ ${\epsilon }_{eff}:effectivepermittivity$ $\begin{array}{r}{Z}_0:characteristicimpedance;Venteret\\ al.:inS-CPWfloatingshieldstripsunder\\ theline(signalonM4,stripsonM3,0.7\\ \mu \mathrm{m}wideandspaced)raisethecapacitance\\ withoutchangingtheinductance,whilein\\ slow-wavemicrostripaslottedlower\\ groundraisestheinductance;optimum{Z}_0\\ forpeakQfallsfrom40to23\Omega (S-CPW)\\ andfrom61to40\Omega (S-MS)astheground\\ spacinggrows,averagingabout23and43\\ \Omega ,withS-CPWabout12percenthigherin\\ peakQ,S-CPWpreferredforlowandS-MS\\ forhighimpedance;Burdinetal.:S-CPW\\ linesmakea65\mathrm{nm}rat-racebalunof0.085\\ \mathrm{m}{\mathrm{m}}^{2}for51to67\mathrm{GHz}\end{array}$ $\begin{array}{r}(computed:{\epsilon }_{eff}of21to56.5shortensthe\\ wavelength2.3to3.8timesagainst{\epsilon }_{eff}=\\ 4)\end{array}$

Important Questions

Ques: What line Q can standard and slow-wave on-chip lines reach at 60 GHz?

Venter et al. studied lines in a four-metal 0.35 $\mu \mathrm{m}$ CMOS process with a thick top metal. At 60 $\mathrm{GHz}$ a standard CPW peaked at Q about 14 near 69 $\Omega$, falling for wider gaps as the field reached the silicon, and a standard microstrip peaked at 15.6 between 45 and 55 $\Omega$. Slow-wave CPW lines exceeded 30: from the measured 0.86 to 1.42 $dB/mm$ and effective permittivities of 21 to 56.5, $Q=\beta /2\alpha$ gives 29 to 34 (computed), consistent with the paper. Burdin et al. report Q of 24 for a 45 $\Omega$ slow-wave CPW in 65 $\mathrm{nm}$ CMOS with an effective permittivity of 12.5, implying about 0.80 $dB/mm$ (computed). The slow-wave lines gain because the phase constant rises faster than the attenuation. Reference: J. J. P. Venter, A.-L. Franc, T. Stander and P. Ferrari, ‘Transmission Lines Characteristic Impedance versus Q-factor in CMOS Technology’, International Journal of Microwave and Wireless Technologies (Cambridge University Press; year not in the text, about 2021 to 2022), University of Pretoria repository copy (fetch-tool summary; equations garbled); F. Burdin, F. Podevin, B. Blampey, N. Corrao, E. Pistono and P. Ferrari, ‘Millimeter-wave Rat-race Balun in a CMOS 65 nm Technology with Slow-wave Transmission Lines and Innovative Topology’, PIERS 2012 Moscow proceedings (fetch-tool summary).

Ques: Why do slow-wave CPW lines make mm-wave circuits smaller?

Because the floating shield strips under the line raise the capacitance per unit length while leaving the inductance almost unchanged, so the phase velocity $1/\sqrt{L_l{C}_l}$ drops and the wavelength shrinks. At 60 $\mathrm{GHz}$ a line in oxide with an effective permittivity of about 4 (assumed) has a guided wavelength of 2.5 $\mathrm{mm}$, while Venter et al.’s slow-wave lines with 21 to 56.5 have 1.09 to 0.67 $\mathrm{mm}$, 2.3 to 3.8 times shorter (computed). The shield also keeps the field out of the lossy silicon. Burdin et al. used such lines to build a rat-race balun of only 0.085 $\mathrm{m}{\mathrm{m}}^2$ for 51 to 67 $\mathrm{GHz}$ in 65 $\mathrm{nm}$ CMOS. The penalty is a lower characteristic impedance, since $Z_0=\sqrt{L_l/C_l}$ falls, which is why the optimum impedance of S-CPW is only about 23 to 40 $\Omega$. Reference: J. J. P. Venter, A.-L. Franc, T. Stander and P. Ferrari, ‘Transmission Lines Characteristic Impedance versus Q-factor in CMOS Technology’, International Journal of Microwave and Wireless Technologies (Cambridge University Press; year not in the text, about 2021 to 2022), University of Pretoria repository copy (fetch-tool summary; equations garbled); F. Burdin, F. Podevin, B. Blampey, N. Corrao, E. Pistono and P. Ferrari, ‘Millimeter-wave Rat-race Balun in a CMOS 65 nm Technology with Slow-wave Transmission Lines and Innovative Topology’, PIERS 2012 Moscow proceedings (fetch-tool summary).

Ques: Which characteristic impedance gives the highest Q for slow-wave lines?

It depends on the ground spacing, so there is no single optimum. Venter et al. found that the impedance at peak Q falls from 40 to 23 $\Omega$ for slow-wave CPW and from 61 to 40 $\Omega$ for slow-wave microstrip as the ground-to-ground spacing grows from 10 to 120 $\mu \mathrm{m}$, averaging about 23 and 43 $\Omega$ at 60 $\mathrm{GHz}$. Slow-wave CPW had about 12 per cent higher peak Q on average. They therefore suggest slow-wave CPW for low impedances and slow-wave microstrip, which keeps the line narrow, for impedances above about 50 to 60 $\Omega$ at gaps up to 50 $\mu \mathrm{m}$. They also note that the two become very similar once the microstrip ground is coplanar with the signal, so the names are largely nomenclature. Reference: J. J. P. Venter, A.-L. Franc, T. Stander and P. Ferrari, ‘Transmission Lines Characteristic Impedance versus Q-factor in CMOS Technology’, International Journal of Microwave and Wireless Technologies (Cambridge University Press; year not in the text, about 2021 to 2022), University of Pretoria repository copy (fetch-tool summary; equations garbled).

Ques: In which mode does a line on a silicon substrate operate?

It depends on the substrate conductivity, frequency and thickness. Tuncer and Neikirk describe three regimes after Hasegawa et al.: a dielectric quasi-TEM mode when the frequency is above the dielectric relaxation frequency, so the silicon acts as a lossy dielectric; a slow-wave mode below it, when the silicon screens the electric field like a metal sheet but the magnetic field still penetrates; and a skin-effect mode when the substrate is thicker than the skin depth. The relaxation frequency $\sigma /(2\pi {\epsilon }_0{\epsilon }_{si})$ is 1.5 $\mathrm{GHz}$ for 100 $\Omega \mathrm{cm}$, 15 $\mathrm{GHz}$ for 10 $\Omega \mathrm{cm}$ and 154 $\mathrm{GHz}$ for 1 $\Omega \mathrm{cm}$ (computed). Loss is highest near the crossover, where the conductivity has a very large effect, so CMOS lines on about 10 $\Omega \mathrm{cm}$ silicon at 10 to 60 $\mathrm{GHz}$ need shielding. Reference: E. Tuncer and D. P. Neikirk, ‘Highly Accurate Quasi-Static Modeling of Microstrip Lines Over Lossy Substrates’, IEEE Microwave and Guided Wave Letters 2, 409-411 (1992) (UT Austin web summary; equations not in text) (fetch-tool summary).

Ques: Should mm-wave CMOS circuits use microstrip or coplanar waveguide?

Both are used, for different reasons. Microstrip, with its ground in a lower metal, shields the fields from the substrate, as Niknejad and Brodersen note, but the thin dielectric of a few micrometres makes the strip narrow and limits its impedance (background knowledge). CPW sets its impedance with the signal-to-ground spacing and, in the Berkeley 130 $\mathrm{nm}$ work, realized higher-Q inductive lines for tuning out device capacitance, so they chose CPW, with bridges to suppress the odd mode. Venter et al. measured similar peak Q at 60 $\mathrm{GHz}$: 14 for standard CPW and 15.6 for microstrip, both well below slow-wave CPW at above 30. The choice therefore depends on the required impedance, layout density and whether a CPW gap would expose the substrate. Reference: A. M. Niknejad and R. W. Brodersen with C. H. Doan, S. Emami et al., EECS 217 Lecture 22, Si Microwave Amplifier Survey, UC Berkeley (2005) (fetch-tool summary); J. J. P. Venter, A.-L. Franc, T. Stander and P. Ferrari, ‘Transmission Lines Characteristic Impedance versus Q-factor in CMOS Technology’, International Journal of Microwave and Wireless Technologies (Cambridge University Press; year not in the text, about 2021 to 2022), University of Pretoria repository copy (fetch-tool summary; equations garbled).

Ques: How accurate are the closed-form microstrip and CPW formulas for on-chip lines?

Steer quotes about 1 per cent for the microstrip formulas for relative permittivities of 8 to 12 and 1.5 per cent for the CPW effective permittivity for substrate heights above the gap, and the printed worked examples are reproduced exactly: 75 $\Omega$ microstrip with w/h of 0.704 and an effective permittivity of 3.82, and a 45.1 $\Omega$ CPW with modulus 0.556 (computed). On chip, the stack of oxide and nitride layers with permittivities of about 4 to 7, metal thicknesses comparable to widths and the nearby fill and lossy silicon move the lines outside these ranges, so the formulas give starting dimensions only (my reading). The Steer CPW example also has an inconsistency: the problem text gives a 200 $\mu \mathrm{m}$ strip, while the solution uses 500 $\mu \mathrm{m}$. Electromagnetic simulation and measured lines, as in Venter et al., set the final design. Reference: M. Steer, Microwave and RF Design II: Transmission Lines, Sec. 3.6 Microstrip Design Formulas, Engineering LibreTexts (CC BY-NC) (fetch-tool summary); M. Steer, Microwave and RF Design II: Transmission Lines, Sec. 3.8 Co-Planar Waveguide, Engineering LibreTexts (CC BY-NC) (fetch-tool summary); J. J. P. Venter, A.-L. Franc, T. Stander and P. Ferrari, ‘Transmission Lines Characteristic Impedance versus Q-factor in CMOS Technology’, International Journal of Microwave and Wireless Technologies (Cambridge University Press; year not in the text, about 2021 to 2022), University of Pretoria repository copy (fetch-tool summary; equations garbled).

Related pages in this vault: Planar Spiral Inductors, Through-Silicon Vias as Passives, On-Chip Transformers and Baluns, Vector Network Analyzer (VNA), Crosstalk and Inductive Effects.