1. Theory

  • Definition: Defects are classified by origin and appearance: random point defects from the clean room against systematic ones from equipment or mistakes, and global scatter against local clusters (globalsino).
  • Material sense: Additive defects are extra material and subtractive defects are missing material (Patsnap).
  • Categories: Particles, microcontamination, pattern anomalies and crystalline defects such as stacking faults (Bennett et al.).
  • Spatial signatures: Wafer maps show centre, ring, edge-ring, scratch and other patterns that point to specific process steps (globalsino; Bao et al.).
  • Failure modes: The structure hit decides the electrical effect: opens and shorts in metal, leakage and threshold shifts in oxides (globalsino).

2. Working Principle

  • Detect: Optical or e-beam inspection reports candidate defects (Defect Detection Fundamentals page).
  • Map: Defect and bin maps are grouped into spatial classes, for example the eight defect classes of WM-811K (Bao et al.).
  • Review and classify: Sampled defects are imaged and assigned to particle, scratch, residue, pattern or crystal classes, increasingly by automatic defect classification (Bennett et al.; Hattori).
  • Trace to source: Signatures and classes are linked to tools, such as CMP scratches to agglomerated slurry or pad debris (Kwon et al.; globalsino).

3. Applications

  • CMP: Scratches, residues and corrosion (Kwon et al.).
  • Lithography: Immersion bubbles and outgassing defects (High-NA DUV Immersion Scanner page).
  • Bare wafers: Particles and COPs (Hattori).
  • Yield modelling: Feeding class-specific densities and kill ratios into yield models (Yield Models and Critical Area page).

Defect Taxonomy

NameFormulaRelated FormulaeVariables/Constants
Random and systematic defects
Additive and subtractive defects
Failure modes by structure

Signatures and Classification

NameFormulaRelated FormulaeVariables/Constants
Wafer-map signatures
WM-811K class shares
Particle and COP discrimination

CMP-Induced Defects

NameFormulaRelated FormulaeVariables/Constants
CMP removal and scratch mechanics



CMP scratch sources
Scratch specifications

Important Questions

Ques: How do random and systematic defects differ, and how does a wafer map show which you have?

By cause and by spatial pattern. Globalsino attributes random point defects to clean-room problems, scattered globally across the wafer, and systematic ones to equipment faults or human mistakes, which form local clusters. It links centre or bulls-eye patterns and edge rings to deposition or RTA non-uniformity, circular rings to etching problems, elliptical zones to deposition, and linear or curvilinear scratches to handling. Bao et al. likewise describe wafer-map patterns as revealing equipment malfunction, process variation or material inconsistencies. A spatial signature can therefore point to a tool before any defect is reviewed, and random defects then set the density in the Poisson-type models while systematic ones lower systematic yield (my reading; Yield Models and Critical Area page). Reference: Y. Liao, globalsino.com, ‘Classification of Defects in ICs’, page 4287 (Tables 4300a and 4300b): random point defects from clean-room problems, systematic point defects from equipment faults or human mistakes, global defects from random clean-room particles, local clusters from assignable causes, cluster patterns (centre from deposition or RTA non-uniformity, ring from etch, edge ring from deposition or RTA, curvilinear and linear scratches from handling), defect types and failure modes by structure (metallization scratches, voids, electromigration, corrosion, W-plug bridging; oxide pinholes, mobile ions, TDDB; dielectric cracks; substrate crystal defects; CMP linked to opens and shorts), failure locations a tenth of a micron or larger and needing TEM as sizes shrink (fetch-tool summary); Y.-Y. Bao, E.-C. Li, H.-Q. Yang and B.-B. Jia, ‘Wafer Map Defect Classification Using Autoencoder-Based Data Augmentation and Convolutional Neural Network’, arXiv:2411.11029: WM-811K with 811457 maps from 47543 lots, 172950 labelled, 25519 defective and 147431 intact, classes Center 4294, Donut 555, Edge-Loc 5189, Edge-Ring 9680, Loc 3593, Random 866, Scratch 1193, Near-full 149, patterns revealing equipment malfunction, process variation or material inconsistencies, Table 1 total 24519 (fetch-tool summary); Yield Models and Critical Area page of this vault.

Ques: What does the WM-811K dataset say about how common each pattern is, and do its totals agree?

Edge patterns dominate, and the class counts add up to the text’s total. Bao et al. describe 811457 wafer maps, 172950 labelled, of which 25519 are defective and 147431 intact, so 14.8 per cent of labelled maps are defective (computed). Their class counts give Edge-Ring 37.9, Edge-Loc 20.3, Center 16.8, Loc 14.1, Scratch 4.7, Random 3.4, Donut 2.2 and Near-full 0.6 per cent of defective maps (computed). Their Table 1, however, totals 24519. The eight class counts sum exactly to 25519 (computed), so the text figure is more likely correct and the table total a typing error (my reading). The paper also states that the None class is 18.2 per cent of the dataset, which conflicts with 147431 intact of 172950 labelled, 85 per cent (computed). Reference: Y.-Y. Bao, E.-C. Li, H.-Q. Yang and B.-B. Jia, ‘Wafer Map Defect Classification Using Autoencoder-Based Data Augmentation and Convolutional Neural Network’, arXiv:2411.11029: WM-811K with 811457 maps from 47543 lots, 172950 labelled, 25519 defective and 147431 intact, classes Center 4294, Donut 555, Edge-Loc 5189, Edge-Ring 9680, Loc 3593, Random 866, Scratch 1193, Near-full 149, patterns revealing equipment malfunction, process variation or material inconsistencies, Table 1 total 24519 (fetch-tool summary).

Ques: What causes CMP scratches and how are they controlled?

Hard, oversized particles under load. Kwon et al. call scratches the most damaging CMP defect and trace them to agglomerated abrasives formed by pH shock, dilution, temperature change or pump stress, to pad debris torn off by the conditioner, and to released conditioner diamonds; brittle films show periodic chatter marks. Scratch counts rose linearly with particles above 0.469 , removing pad debris halved light-point defects, and 0.5 point-of-use filters reduced defect density. Lateral cracks deepen as load to the one-half and radial cracks as load to the two-thirds, 1.41 and 1.59 times for doubled load (computed). ITRS targets for STI CMP halved the critical scratch length from 17.9 to 8.9 between 2012 and 2018. Reference: T.-Y. Kwon, M. Ramachandran and J.-G. Park, ‘Scratch formation and its mechanism in chemical mechanical planarization (CMP)’, Friction 1, 279 (2013): CMP defects (particles, macro and micro scratches, corrosion, delamination, organic residue, water marks), scratches most detrimental, chatter marks on brittle films, agglomerated abrasives from pH shock, dilution, temperature or pump stress, pad debris and conditioner diamonds, Preston MRR = K_p P V, lateral crack depth scaling as load^1/2 and cone and radial cracks as load^2/3, ITRS 2010 STI critical scratch length 17.9 nm (2012) to 8.9 nm (2018) with allowed counts 40.1 to 104.6 per wafer, scratch count linear in large particles above 0.469 um, pad debris removal halving light-point defects, 0.5 um point-of-use filter reducing defects (fetch-tool summary).

Ques: How do additive and subtractive defects map to electrical failures?

Through the structure they land on. Patsnap defines additive defects as extra material, such as dust, process residues and deposition particles, and subtractive ones as unintended removal, from over-etch or excessive CMP, leaving pits and grooves; the first is controlled by contamination control, the second by process precision. Globalsino lists metallization defects (scratches, voids, corrosion, W-plug bridging) as causing opens and shorts, gate and field oxide defects (pinholes, mobile ions) as causing leakage, lower breakdown and threshold shifts, and dielectric cracks as causing shorts and leakage. Additive material bridging two lines therefore tends to short them and missing material to open them (my reading). Globalsino adds that shrinking failure sites eventually need TEM. Reference: Patsnap Eureka, ‘Particle defect classification: additive vs subtractive wafer defects’ (28 July 2025): additive defects as extra material such as dust, residues and deposition particles, subtractive defects as unintended removal such as over-etch or excess CMP removal giving pits and grooves, contamination control against process precision (fetch-tool summary); Y. Liao, globalsino.com, ‘Classification of Defects in ICs’, page 4287 (Tables 4300a and 4300b): random point defects from clean-room problems, systematic point defects from equipment faults or human mistakes, global defects from random clean-room particles, local clusters from assignable causes, cluster patterns (centre from deposition or RTA non-uniformity, ring from etch, edge ring from deposition or RTA, curvilinear and linear scratches from handling), defect types and failure modes by structure (metallization scratches, voids, electromigration, corrosion, W-plug bridging; oxide pinholes, mobile ions, TDDB; dielectric cracks; substrate crystal defects; CMP linked to opens and shorts), failure locations a tenth of a micron or larger and needing TEM as sizes shrink (fetch-tool summary).

Ques: How are defects classified and sent for review?

By sampling inspection events, imaging them and assigning classes. Bennett et al. describe defects as particles, microcontamination, pattern anomalies and crystalline defects such as stacking faults, and present automatic defect classification as part of SEMATECH’s strategy for in-line yield improvement. Hattori shows that unpatterned-wafer tools separate particles from crystal-originated pits using vertical and oblique incidence, with accuracies from 53 to 93 per cent across tools. Process-specific types add to the list, such as immersion bubbles and resist outgassing in lithography (High-NA DUV Immersion Scanner page). Classification accuracy then sets how many sampled events are defects of interest, which is measured by capture and nuisance rates (Defect Detection Fundamentals page). Reference: M. H. Bennett, K. W. Tobin and S. S. Gleason, ‘Automatic defect classification: status and industry trends’, Proc. SPIE 2439, 210 (1995), ORNL abstract: defects as particles, microcontamination, pattern anomalies or crystalline defects such as stacking faults, ADC part of SEMATECH strategy for in-line yield improvement (fetch-tool summary); T. Hattori (Sony), ‘Challenges of Smaller Particle Detection on Both Bulk-Silicon and SOI Wafers’, NIST presentation (2005): COPs, micro-scratches, microroughness and organic haze as surface conditions, particle and COP classification by vertical and oblique incidence, accuracies 53 to 93 per cent (fetch-tool summary); High-NA DUV Immersion Scanner page of this vault; Defect Detection Fundamentals page of this vault.

References

  1. Y. Liao, “Classification of defects in ICs,” globalsino.com, page 4287. Available: https://www.globalsino.com/ICsAndMaterials/page4287.html
  2. Y.-Y. Bao, E.-C. Li, H.-Q. Yang and B.-B. Jia, “Wafer map defect classification using autoencoder-based data augmentation and convolutional neural network,” arXiv:2411.11029, 2024. Available: https://arxiv.org/html/2411.11029v1
  3. T.-Y. Kwon, M. Ramachandran and J.-G. Park, “Scratch formation and its mechanism in chemical mechanical planarization (CMP),” Friction, vol. 1, pp. 279-305, 2013. Available: https://link.springer.com/content/pdf/10.1007/s40544-013-0026-y.pdf
  4. Patsnap Eureka, “Particle defect classification: additive vs subtractive wafer defects,” 28 July 2025. Available: https://eureka.patsnap.com/article/particle-defect-classification-additive-vs-subtractive-wafer-defects
  5. M. H. Bennett, K. W. Tobin and S. S. Gleason, “Automatic defect classification: status and industry trends,” Proc. SPIE 2439, pp. 210-220, 1995 (abstract read). Available: https://impact.ornl.gov/en/publications/automatic-defect-classification-status-and-industry-trends/
  6. T. Hattori, “Challenges of smaller particle detection on both bulk-silicon and SOI wafers,” Sony Corporation, NIST presentation, 2005. Available: https://www.nist.gov/document/hattori2005pdf
  7. High-NA DUV Immersion Scanner page of this vault.
  8. Defect Detection Fundamentals page of this vault.
  9. Yield Models and Critical Area page of this vault.

Related pages in this vault: Defect Detection Fundamentals, Yield Models and Critical Area, CMP Polisher, E-Beam Inspection and Defect Review, Laser-Scattering Particle Inspection, High-NA DUV Immersion Scanner, RCA Wet Bench, Megasonic Single-Wafer Cleaner, Spin Rinse Dryer and IPA Vapor Dryer, Vapor HF and Plasma Dry Clean Tool, Wafer-Map Spatial Signature Analysis, Defect Inspection Workflow and Sampling Plans, Automatic Defect Classification and Machine Learning.