1. Theory

  • Definition: An LCR meter measures the complex impedance of a device at a chosen frequency and AC level, superimposed on an optional DC bias, and reports it through a series or parallel equivalent circuit (Agilent handbook; Keithley).
  • C-V measurement: Sweeping the DC bias on a MOS capacitor or junction while measuring capacitance gives oxide thickness, doping profile, flat-band voltage and oxide charge (Keithley).
  • Low and high frequency: Comparing quasi-static and high-frequency C-V curves gives the interface trap density (Keithley Model 82 lab notes).
  • Device physics: The theory of MOS C-V curves is on the MOS Capacitor page; this page covers the instrument and the extraction formulas.

2. Working Principle

  • Auto-balancing bridge: A feedback loop holds the low terminal at virtual ground, so the DUT current flows through a range resistor and the impedance follows from the ratio of two vector voltages (Agilent handbook).
  • Four-terminal pair: Coaxial cables separate the current and sense paths, with a frequency-length limit (Agilent handbook).
  • Compensation: Open and short measurements remove fixture stray admittance and residual impedance (Agilent handbook; Keithley).
  • Model choice: Small capacitances are read in the parallel model, large ones in the series model; series resistance is removed using accumulation data (Keithley; Gokcen et al.).

3. Applications

  • Gate-dielectric monitoring: Oxide thickness, flat-band voltage and oxide charge (Keithley).
  • Doping profiles: Depletion C-V on MOS capacitors and Schottky or p-n junctions (Keithley; Mercury Probe page).
  • Interface quality: Interface trap density from combined C-V methods (Keithley Model 82 lab notes).
  • Passive components: Capacitor, inductor and resistor characterization against frequency (Agilent handbook).

Impedance Measurement

NameFormulaRelated FormulaeVariables/Constants
Impedance, Q and D









Auto-balancing bridge



Series and parallel models


Fixturing and Corrections

NameFormulaRelated FormulaeVariables/Constants
Four-terminal-pair cable limit

Open and short compensation


Series-resistance correction



C-V Extraction

NameFormulaRelated FormulaeVariables/Constants
Oxide thickness and doping profile





Work function and effective oxide charge




Interface traps from high- and low-frequency C-V



Important Questions

Ques: How does an LCR meter measure capacitance?

With an auto-balancing bridge. A small AC signal, in the millivolt range for C-V work (Keithley) and 5 to 1 V rms on the 4294A, drives the device. A detector controls a second oscillator so that the low terminal sits at virtual ground, forcing the device current through a known range resistor . The impedance follows from two vector voltages, , and the phase separates resistance from reactance. A 100 capacitor at 1 is 1.59 (computed). The meter then reports the result as a series or parallel pair, with Q and D. The bridge covers milliohms to about 100 from low to high frequencies (Agilent handbook). Reference: Agilent Technologies, Impedance Measurement Handbook (Q, D, auto-balancing bridge, 4TP, residual values) (fetch-tool summary of a university-hosted copy); Keithley, ‘C-V Characterization of MOS Capacitors Using the 4200-SCS’, application note 2896 (several formulas garbled in OCR and rebuilt) (fetch-tool summary).

Ques: Should the parallel or the series model be used?

The one that matches the dominant loss. Both describe the same measured impedance, related by (Agilent handbook, Table 1-3), so they agree when the dissipation factor is small: D of 0.1 separates them by 1 per cent, while D of 1 gives a factor of two (computed). For small capacitances and high impedances, parallel leakage dominates and the parallel model fits; for large capacitances and low impedances, series resistance dominates and the series model fits. Keithley’s thresholds express the same idea through compensation: open correction below 10 or above 1 , short correction above 10 or below 10 . MOS C-V is normally measured in the parallel Cp-Gp model, which Keithley’s series-resistance correction requires. Reference: Agilent Technologies, Impedance Measurement Handbook, 4th ed., section 1.7, Table 1-3: Cs = Cp(1 + D^2), Cp = Cs/(1 + D^2), Rp = Rs(1 + 1/D^2), Rs = Rp D^2/(1 + D^2) (fetch-tool summary); Keithley, ‘C-V Characterization of MOS Capacitors Using the 4200-SCS’, application note 2896 (several formulas garbled in OCR and rebuilt) (fetch-tool summary).

Ques: Why are compensation and cable length so important?

Because fixture parasitics are comparable to small devices. The Agilent handbook quotes residuals of 0.1 and 0.1 , a shorting bar with about 20 and 1 , and a fringe capacitance of 0.082 for a 7 open connector. An uncompensated 0.1 stray is a 10 per cent error on a 1 test structure (computed). Open compensation measures the stray admittance with the probes raised, short compensation the residual impedance with the probe shorted to the chuck (Keithley), and the meter removes both; the simple form is (computed for a series residual followed by a shunt stray). Four-terminal-pair cables keep current and sense paths apart but must satisfy : 15 at 1 , 1.5 at 10 (computed). Reference: Agilent Technologies, Impedance Measurement Handbook (Q, D, auto-balancing bridge, 4TP, residual values) (fetch-tool summary of a university-hosted copy); Keithley, ‘C-V Characterization of MOS Capacitors Using the 4200-SCS’, application note 2896 (several formulas garbled in OCR and rebuilt) (fetch-tool summary).

Ques: How does series resistance distort a C-V curve, and how is it removed?

It makes the measured parallel capacitance fall below the true value at high frequency, flattening accumulation. The substrate and back contact add a resistance in series with the capacitor; when is no longer small, the parallel-model reading drops by . For 100 at 1 , 100 gives only 0.39 per cent error, but 1 gives 28 per cent (computed), so a high-resistivity or poorly contacted wafer can mimic a thicker oxide. The correction measures and in strong accumulation, computes , and corrects every point (Gokcen et al., after Nicollian and Goetzberger; the forms follow from the series circuit, computed). Keithley implements this in the parallel model and notes substrate resistances are usually below 10 . Lowering the frequency also helps. Reference: Keithley, ‘C-V Characterization of MOS Capacitors Using the 4200-SCS’, application note 2896 (several formulas garbled in OCR and rebuilt) (fetch-tool summary); M. Gokcen, H. Altuntas and S. Altindal, Optoelectron. Adv. Mater. Rapid Commun. 2(12), 838-841, 2008: R_s from C_m and G_m in strong accumulation (Eq. 2, garbled in extraction), by the Nicollian and Goetzberger method (fetch-tool summary).

Ques: What does a C-V sweep give besides oxide thickness?

The doping profile and flat-band voltage. Oxide thickness comes from accumulation, ; Keithley’s example, 50 on 0.01 , corresponds to 690 (computed). In depletion the slope of against voltage gives the doping at depth , but Keithley warns this is inaccurate within two Debye lengths of the surface, about 82 at (computed: ). The flat-band capacitance follows from the Debye length, and is found by interpolating the curve at that capacitance; Keithley notes this fails when interface trap densities reach to . The threshold voltage follows from the doping and . Reference: Keithley, ‘C-V Characterization of MOS Capacitors Using the 4200-SCS’, application note 2896 (several formulas garbled in OCR and rebuilt) (fetch-tool summary); MOS Capacitor page of this vault.

Ques: How is the effective oxide charge obtained?

From the shift of the flat-band voltage from the work-function difference. Keithley gives , with for aluminium on silicon, which is -0.95 for p-type and -0.27 for n-type at ; these follow from at 293 (computed). In its worked example, 0.01 , 50 and a flat-band voltage of -5.95 give , or charges per square centimetre (computed). Keithley stresses that lumps fixed, mobile ionic and oxide-trapped charge, should be treated as a relative measure, and can be separated by temperature cycling, while mobile ions are measured by bias-temperature stress. Reference: Keithley, ‘C-V Characterization of MOS Capacitors Using the 4200-SCS’, application note 2896 (several formulas garbled in OCR and rebuilt) (fetch-tool summary).

Ques: Which intrinsic carrier density should be used, or ?

The two values come from different eras. Keithley’s software and its Model 82 lab notes use e10 . Altermatt et al. call the commonly used value, measured by Sproul and Green in 1991, and reinterpret those data with band-gap narrowing to obtain at 300 , in agreement with capacitance measurements by Misiakos and Tsamakis. The newer value is more likely correct, because two independent methods support it and it accounts for band-gap narrowing (my reading). The difference changes the bulk potential by at 300 (computed), shifting the work-function difference and by 10.5 and 21 . For oxide-charge estimates this is a few per cent of a volt-scale flat-band shift, but it matters when comparing extractions from different software. Reference: Keithley, ‘C-V Characterization of MOS Capacitors Using the 4200-SCS’, application note 2896 (several formulas garbled in OCR and rebuilt) (fetch-tool summary); Keithley Instruments, ‘Lab Notes: Model 82 C-V System’, 1994: DIT = (1e-12) CIT/(A q) with CIT = (1/CQ - 1/COX)^-1 - (1/CH - 1/COX)^-1, quasi-static capacitance from the integrator, nI = 1.45e10 cm-3 (fetch-tool summary); P. P. Altermatt, A. Schenk, F. Geelhaar and G. Heiser, J. Appl. Phys. 93, 1598-1604, 2003 (abstract): commonly used ni = 1.00e10 cm-3 at 300 K from Sproul and Green (1991), reinterpreted with band-gap narrowing as 9.65e9 cm-3, agreeing with Misiakos and Tsamakis (1993) (fetch-tool summary).

Ques: How is the interface trap density measured with C-V?

By comparing low- and high-frequency curves. At high frequency, interface traps cannot follow the AC signal and add no capacitance; in the quasi-static curve they respond and add a capacitance proportional to their density. The difference gives per square centimetre per electronvolt, mapped to energy through the surface potential; the Keithley Model 82 lab notes write , the same expression (computed). The quasi-static capacitance comes from the displacement current under a slow ramp, ; 100 at 0.1 draws only 10 (computed), so gate leakage must be far smaller, which limits the method on thin oxides. Keithley notes that high interface trap densities also distort flat-band extraction. Reference: Keithley Instruments, ‘Lab Notes: Model 82 C-V System’, 1994: DIT = (1e-12) CIT/(A q) with CIT = (1/CQ - 1/COX)^-1 - (1/CH - 1/COX)^-1, quasi-static capacitance from the integrator, nI = 1.45e10 cm-3 (fetch-tool summary); Keithley, ‘C-V Characterization of MOS Capacitors Using the 4200-SCS’, application note 2896 (several formulas garbled in OCR and rebuilt) (fetch-tool summary).

References

  1. Agilent Technologies, Impedance Measurement Handbook, Agilent (now Keysight) application note 5950-3000. Available: https://svelto.faculty.polimi.it/didattica/materiale_didattico/materiale%20didattico_MRF/appnote/handbook_imp-meas.pdf
  2. Keithley Instruments, “C-V Characterization of MOS Capacitors Using the Model 4200-SCS Semiconductor Characterization System,” application note 2896. Available: https://xdevs.com/doc/Keithley/Appnotes/2896%20C-V%20Char%20MOS%20Ca%2326C8B1.pdf
  3. Agilent Technologies, Impedance Measurement Handbook, 4th ed., application note 5950-3000, section 1.7. Available: https://xdevs.com/doc/HP/pub/5950-3000.pdf
  4. Keithley Instruments, Lab Notes: Model 82 C-V System, A Series of Experiments Using the Model 82 C-V Measurement System, Cleveland, OH, 1994. Available: https://valuetronics.com/cdn/shop/files/Keithley_82_C-V_System_Lab_Notes.pdf
  5. M. Gokcen, H. Altuntas and S. Altindal, “Temperature dependence of electrical characteristics of Au/SiO2/n-GaAs (MOS) structures,” Optoelectron. Adv. Mater. Rapid Commun., vol. 2, no. 12, pp. 838-841, 2008. Available: https://oam-rc.inoe.ro/articles/temperature-dependence-of-electrical-characteristics-of-ausio2n-gaas-mos-structures/fulltext
  6. P. P. Altermatt, A. Schenk, F. Geelhaar and G. Heiser, “Reassessment of the intrinsic carrier density in crystalline silicon in view of band-gap narrowing,” J. Appl. Phys., vol. 93, pp. 1598-1604, 2003 (abstract). Available: https://unsworks.unsw.edu.au/entities/publication/2c330f15-ece8-4dfd-b035-ec5d867c1d8d
  7. MOS Capacitor, page in this vault.

Related pages in this vault: Mercury Probe, Charge Pumping, SMU and Probe Station, MOS Capacitor, Corona-Kelvin Metrology, Vector Network Analyzer (VNA), AC Circuits and Impedance, Charge and Capacitance Modelling, PN Junction.