Mismatch and Variability

1. Theory

• Definition: Mismatch is the time-independent random difference between the parameters of identically designed devices on the same chip, and variability includes these local random variations as well as global wafer-to-wafer and die-to-die shifts (Kinget chapter; Pelgrom et al.).
• Pelgrom law: The standard deviation of the threshold and current-factor differences falls as $1/\sqrt{WL}$, set by matching coefficients $A_{VT}$ and $A_{\beta }$, because many independent microscopic fluctuations average over the gate area (Pelgrom et al.; Kinget chapter).
• Origin: The main contribution to $A_{VT}$ is the random number of dopants in the depletion layer, with smaller parts from dimensions, interface states and, at small sizes, line-edge roughness (Pelgrom et al.; Gielen and Dehaene).
• Scaling: $A_{VT}$ fell from about 30 $\mathrm{mV}\mu \mathrm{m}$ at 2.5 $\mu \mathrm{m}$ to about 5 to 15 $\mathrm{mV}\mu \mathrm{m}$ at 0.8 to 0.25 $\mu \mathrm{m}$, roughly with oxide thickness, but devices shrink faster than $A_{VT}$, so minimum-size devices match worse (Kinget chapter; Pelgrom et al.; background knowledge for the oxide link).
• Design limit: Mismatch sets a minimum power for given speed and accuracy far above the thermal-noise limit, so it dominates the design of fast, precise analog circuits (Kinget chapter; Pelgrom et al.).

2. Working Principle

• Averaging of random charges: Each dopant in the depletion region contributes a small threshold shift; the number in a device follows Poisson statistics, so the relative spread falls as the inverse square root of the number, and therefore of area (Pelgrom et al.; Gielen and Dehaene).
• Current mismatch: The threshold mismatch converts to current mismatch through $g_m/I$, so weak inversion, with the highest $g_m/I$, has the largest current mismatch and high overdrive the smallest, while $\Delta \beta /\beta$ adds independently (Kinget chapter).
• Systematic effects: Gradients across the die, layout topography, metal coverage, implant shadowing, packaging and strain add deterministic offsets that identical, closely placed and common-centroid layouts cancel (Pelgrom et al.).
• Statistical models: In simulation, mismatch is applied as random parameter shifts per device in Monte Carlo runs, and global variation as process corners or correlated parameter distributions (background knowledge).

3. Applications

• Analog design: Sizing input pairs, current mirrors and comparators for offset and current-matching targets in amplifiers, data converters and references (Kinget chapter; Pelgrom et al.).
• Data-converter yield: Relating input-pair offset to converter yield, as for 7 to 10 bit ADCs in Pelgrom et al. (Pelgrom et al.).
• Digital and SRAM design: Threshold variation of minimum devices sets SRAM stability, clock skew and timing margins (Pelgrom et al.; Gielen and Dehaene).
• Model cards: Matching parameters such as AVTO, AKP and AGAMMA in EKV and statistical options in BSIM and PSP (EKV page; background knowledge).

Matching Laws

Name	Formula	Related Formulae	Variables/Constants
Pelgrom area law	$\sigma \left(\Delta V_{T0}\right)=\frac{A_{VT}}{\sqrt{WL}},\sigma \left(\frac{\Delta \beta }{\beta }\right)=\frac{A_{\beta }}{\sqrt{WL}}$	${\sigma }^2\left(\Delta P\right)=\frac{A_P^2}{WL}+S_P^2{D}_x^2(\text{with distance term})$	$\begin{array}{r}\sigma (\Delta V_{T0}):standarddeviationofthe\\ thresholddifferencebetweentwoidentical\\ devices\end{array}$ $\begin{array}{r}{A}_{VT}:thresholdmatchingcoefficient,\\ \sigma (\Delta \beta /\beta ):relativecurrent-factormismatch,\\ A_{\beta }:current-factormatchingcoefficient\end{array}$ $W,L:gatewidthandlength$ $P:adeviceparameter$ $S_P:distancecoefficient$ $\begin{array}{r}{D}_x:separation(distanceform,background\\ knowledge);Pelgrometal.:thethreshold\\ differencefallsastheinversesquare\\ rootofarea,with{A}_{VT}dominatedbythe\\ uncertaintyinthenumberofactive\\ dopantsinthedepletionlayer,plus\\ dimensionalvariationsandinterface\\ states,validforindependentdisturbances\\ withcorrelationdistancesmallcompared\\ withthedevice,andextendablebelow0.1\\ \mu \mathrm{m}withcorrectedeffectivedimensions;A_{VT}\\ betweenabout5and15\mathrm{mV}\mu \mathrm{m}for0.25to\\ 0.8\mu \mathrm{m}processes;Kingetchapter:thesame\\ laws,withdistancetermsdroppedfor\\ analog-scalelayouts\end{array}$ $\begin{array}{r}(computed:A_{VT}=13\mathrm{mV}\mu \mathrm{m}gives13\mathrm{mV}for\\ a1\mu {\mathrm{m}}^{2}pairand18.6\mathrm{mV}fora0.7by0.7\mu \mathrm{m}\\ pair)\end{array}$
Measured matching coefficients	$A_{VT}[\mathrm{mV}\mu \mathrm{m}],A_{\beta }[\%\mu \mathrm{m}]$	$A_{VT}\text{falls with oxide thickness}$	$$\begin{gathered} \begin{array}{r}Kingetchapter(Tables3.1and3.4):A_{VT}\\ and{A}_{\beta }of30\mathrm{mV}\mu \mathrm{m}and2.3\%\mu \mathrm{m}\\ (nMOS)and35\mathrm{mV}\mu \mathrm{m}and3.2\%\mu \mathrm{m}\\ (pMOS)at2.5\mu \mathrm{m},21and1.8(nMOS)and25\\ and4.2(pMOS)at1.2\mu \mathrm{m},and13and1.9\\ (nMOS)and22and2.8(pMOS)at0.7\mu \mathrm{m};\\ Pelgrometal.:A_{VT}ofabout5to15\mathrm{mV}\mu \\ \mathrm{m}from0.8to0.25\mu \mathrm{m},highpMOSvaluesat\\ 0.8and1\mu \mathrm{m}fromcompensatingimplantsin\\ ann-wellprocess,gatedepletionand\\ boronpenetrationsignificantindeep\\ submicron,a3.3\mathrm{nm}oxideinthe0.18\mu \mathrm{m}\\ example,and{A}_{Vbe}=0.35\mathrm{mV}\mu \mathrm{m}forbipolar\\ transistors(theproportionalityof{A}_{VT}to\\ oxidethicknessisbackgroundknowledge)\end{array} \end{gathered}$$ $(nocomputedvalue)$

Current Mismatch and Offset

Name	Formula	Related Formulae	Variables/Constants
Drain-current mismatch	${\sigma }^2\left(\frac{\Delta I}{I}\right)={\sigma }^2\left(\frac{\Delta \beta }{\beta }\right)+\frac{4{\sigma }^2\left(\Delta V_{T0}\right)}{{\left(V_{GS}-V_T\right)}^2}(\text{strong inversion, saturation})$	${\sigma }^2\left(\frac{\Delta I}{I}\right)={\sigma }^2\left(\frac{\Delta \beta }{\beta }\right)+\frac{{\sigma }^2\left(\Delta V_{T0}\right)}{{\left(n{U}_T\right)}^2}(\text{weak inversion}),{\sigma }^2\left(\frac{\Delta I}{I}\right)={\sigma }^2\left(\frac{\Delta \beta }{\beta }\right)+{\left(\frac{g_m}{I}\right)}^2{\sigma }^2\left(\Delta V_{T0}\right)(\text{general})$	$\begin{array}{r}\Delta I/I:relativedrain-currentmismatch,V_{GS}\\ -V_T:overdrive\end{array}$ $n:slopefactor$ $\begin{array}{r}{U}_T:thermalvoltage,g_m/I:transconductance\\ efficiency(generalform,background\\ knowledgelinkingbothlimits);Kinget\\ chapter:thestrong-andweak-inversion\\ forms;the{g}_m/IdependenceontheEKVpage\end{array}$ $\begin{array}{r}(computed:with{A}_{VT}=13\mathrm{mV}\mu \mathrm{m}and{A}_{\beta }=\\ 1.9\%\mu \mathrm{m}fora1\mu {\mathrm{m}}^{2}pair,thecurrent\\ mismatchis13percentat0.2\mathrm{V}and3.2\\ percentat1\mathrm{V}overdrive,and39percent\\ inweakinversionwithn=1.3)\end{array}$
Input offset of a differential pair	$\sigma \left(V_{OS}\right)=\frac{A_{VT}}{\sqrt{WL}}(\text{threshold-dominated})$	${\sigma }^2\left(V_{OS}\right)={\sigma }^2\left(\Delta V_{T0}\right)+{\left(\frac{I}{g_m}\right)}^2{\sigma }^2\left(\frac{\Delta \beta }{\beta }\right)$	$\begin{array}{r}{V}_{OS}:input-referredoffsetvoltageofa\\ differentialpair,I/g_m:inverse\\ transconductanceefficiency(secondform,\\ backgroundknowledge);Kingetchapter:the\\ input-referredoffsetofapairequalto\\ A_{VT}/\sqrt{WL},thepaircontributing\sqrt{2}relative\\ toasingletransistor;Pelgrometal.:\\ yieldof7to10bitADCsfallingwith\\ input-pairoffsetstandarddeviationsfrom\\ 0to6\mathrm{mV}\end{array}$ $(nocomputedvalue)$

Design Limits

Name	Formula	Related Formulae	Variables/Constants
Speed, precision and power limit from mismatch	$P\ge 24C_{ox}{A}_{VT}^{2}fD{R}^2$	$\frac{{\mathrm{Gain}}^2\cdot BW\cdot {\mathrm{Acc}}^2}{P}=\frac{1}{192C_{ox}{A}_{VT}^2},P_{noise}\ge 8k_{B}TfD{R}^2$	$P:minimumpower$ $C_{ox}:oxidecapacitanceperarea$ $f:signalfrequencyorspeed$ $DR:dynamicrangeoraccuracy$ $BW:bandwidth$ $Acc:accuracy$ $P_{noise}:thermal-noiselimit$ $k_B:Boltzmannconstant$ $\begin{array}{r}T:temperature;Kingetchapter:the\\ minimalpowerforgivenspeed,precision\\ anddynamicrangeboundedbyaterm\\ proportionalto{C}_{ox}{A}_{VT}^2,withminimalenergies\\ percycle24C_{ox}{A}_{VT}^{2}ofabout4.3\times 10^{-2},2.12\times 10^{-2}\\ and6.3\times 10^{-3}\mathrm{fJ}for2.5,1.2and0.7\mu \mathrm{m}nMOS\\ against3.3\times 10^{-5}\mathrm{fJ}for8k_{B}T,somismatch,\\ notthermalnoise,setstheminimumpower\\ offast,accurateCMOScircuits;Pelgrom\\ etal.:thematchingerrorenergyabout\\ twoordersofmagnitudeabove{k}_{B}T;Gielen\\ andDehaene:matchingimprovesonly\\ slightlywithscalingwhilelowersupplies\\ tightensignalrange,sothepowerfor\\ fixedspeedandaccuracystaysroughly\\ constantorrises\end{array}$ $\begin{array}{r}(computed:8k_{B}T=3.3\times 10^{-5}\mathrm{fJ}at300\mathrm{K},\\ matchingthechapter;thetabulated\\ mismatchenergiesimply{C}_{ox}of2.0\times 10^{-3},\\ 2.0\times 10^{-3}and1.6\times 10^{-3}F/{\mathrm{m}}^2,oxidesof17,17\\ and22\mathrm{nm}(seetheQ/A))\end{array}$
Variability in digital circuits	$\Delta t_d\propto \frac{\Delta V_T}{V_{DD}-V_T}$	$V_{margin}\approx \left(6\text{to}10\right)\frac{A_{VT}}{\sqrt{WL}}$	$\Delta t_d:gate-delayvariation$ $\Delta V_T:thresholdvariation$ $V_{DD}:supply$ $\begin{array}{r}{V}_{margin}:overdrivemarginneeded(delay\\ proportionality,backgroundknowledge);\\ Pelgrometal.:digitalcircuitssuchas\\ flip-flopsneedanoverdrivemarginof6\\ to10times{A}_{VT}(readastimesthedevice\\ \sigma (\Delta V_T)),andenvironmentaleffectson\\ matchingincludedistance,topography,\\ metalcoverage,implantstriping,\\ packagingandmechanicalstrain;Gielen\\ andDehaene:dopant-countstatisticsvary\\ as{N}^{1/2},randomdopantplacementand\\ line-edgeroughnessmake{L}_{eff}lessuniform,\\ a50\mathrm{mV}variationmattersmoreat{V}_T=200\\ \mathrm{mV}thanat700\mathrm{mV},andworst-casesizing\\ againstVTvariationraisesenergy\end{array}$ $\begin{array}{r}(computed:50\mathrm{mV}is25percentofa200\\ \mathrm{mV}thresholdbut7percentof700\mathrm{mV})\end{array}$

Important Questions

Ques: How much worse is current matching in weak inversion than in strong inversion?

Much worse, because threshold mismatch is multiplied by $g_m/I$. With the Kinget chapter’s strong-inversion form ${\sigma }^2(\Delta I/I)={\sigma }^2(\Delta \beta /\beta )+4{\sigma }^2(\Delta V_{T0})/(V_{GS}-V_T{)}^2$ and its weak-inversion form with $(n{U}_T{)}^2$, a 1 $\mu {\mathrm{m}}^2$ pair with the 0.7 $\mu \mathrm{m}$ values $A_{VT}=13$ $\mathrm{mV}\mu \mathrm{m}$ and $A_{\beta }=1.9$ $\%\mu \mathrm{m}$ has a current mismatch of 3.2 per cent at 1 $\mathrm{V}$ overdrive, 13 per cent at 0.2 $\mathrm{V}$ and 39 per cent in weak inversion with $n=1.3$ (computed). Current mirrors are therefore biased at high overdrive, while differential pairs, whose offset is the threshold mismatch itself, prefer weak or moderate inversion for gain. The EKV inversion coefficient captures this trade-off. Reference: ‘Implications of transistor mismatch on analog circuit design and system performance’, Chapter 3 hosted on P. Kinget’s Columbia University page (author and year not stated in the excerpt; citations to 1996) (fetch-tool summary); Charge-Based Models (EKV) page of this vault.

Ques: Do the chapter’s minimum mismatch energies agree with its matching coefficients?

Only approximately. The Kinget chapter gives minimal energies per cycle of $24C_{ox}{A}_{VT}^2$ of about $4.3\times 10^{-2}$, $2.12\times 10^{-2}$ and $6.3\times 10^{-3}$ $\mathrm{fJ}$ for 2.5, 1.2 and 0.7 $\mu \mathrm{m}$ nMOS, with $A_{VT}$ of 30, 21 and 13 $\mathrm{mV}\mu \mathrm{m}$. Solving for the oxide capacitance gives $2.0\times 10^{-3}$, $2.0\times 10^{-3}$ and $1.6\times 10^{-3}$ $F/{\mathrm{m}}^2$, equivalent to 17, 17 and 22 $\mathrm{nm}$ of oxide (computed). Oxide thickness should fall from 2.5 to 0.7 $\mu \mathrm{m}$ processes, not rise (background knowledge), so the energies were probably computed with process-specific $C_{ox}$ values not listed in the extract, or rounded (my reading). The conclusion is robust either way: all three energies are two to three orders of magnitude above the $3.3\times 10^{-5}$ $\mathrm{fJ}$ thermal-noise limit $8k_{B}T$ (computed), so mismatch sets the minimum power. Reference: ‘Implications of transistor mismatch on analog circuit design and system performance’, Chapter 3 hosted on P. Kinget’s Columbia University page (author and year not stated in the excerpt; citations to 1996) (fetch-tool summary).

Ques: What values does the threshold matching coefficient take?

It has fallen with technology. The Kinget chapter tabulates $A_{VT}$ of 30 and 35 $\mathrm{mV}\mu \mathrm{m}$ for nMOS and pMOS at 2.5 $\mu \mathrm{m}$, 21 and 25 at 1.2 $\mu \mathrm{m}$, and 13 and 22 at 0.7 $\mu \mathrm{m}$, with $A_{\beta }$ of 1.8 to 4.2 $\%\mu \mathrm{m}$. Pelgrom et al. plot values of about 5 to 15 $\mathrm{mV}\mu \mathrm{m}$ for 0.8 to 0.25 $\mu \mathrm{m}$ processes and explain the high pMOS values at 0.8 and 1 $\mu \mathrm{m}$ by compensating implants in an n-well process. The fall tracks the thinner gate oxide, roughly 1 $\mathrm{mV}\mu \mathrm{m}$ per nm of oxide in mature processes (background knowledge). For a 1 $\mu {\mathrm{m}}^2$ pair at 13 $\mathrm{mV}\mu \mathrm{m}$ the threshold mismatch is 13 $\mathrm{mV}$, and for a 0.7 by 0.7 $\mu \mathrm{m}$ pair 18.6 $\mathrm{mV}$ (computed). Bipolar transistors match much better, with $A_{Vbe}=0.35$ $\mathrm{mV}\mu \mathrm{m}$. Reference: ‘Implications of transistor mismatch on analog circuit design and system performance’, Chapter 3 hosted on P. Kinget’s Columbia University page (author and year not stated in the excerpt; citations to 1996) (fetch-tool summary); M. J. M. Pelgrom, H. P. Tuinhout and M. Vertregt, ‘Transistor matching in analog CMOS applications’, IEDM 1998, 915-918 (Designer’s Guide forum copy; formula 1 and figure values illegible in the extract) (fetch-tool summary).

Ques: Why does mismatch, rather than thermal noise, set the minimum power of precise analog circuits?

Because removing mismatch requires larger devices, whose capacitance must be driven at speed. The Kinget chapter derives a minimum power $P\ge 24C_{ox}{A}_{VT}^{2}fD{R}^2$ for a given speed and dynamic range, against $8k_{B}TfD{R}^2$ for thermal noise, and finds the mismatch term two to three orders of magnitude larger, $6.3\times 10^{-3}$ against $3.3\times 10^{-5}$ $\mathrm{fJ}$ per cycle for 0.7 $\mu \mathrm{m}$ nMOS. Pelgrom et al. likewise place the matching error energy about two orders of magnitude above $k_{B}T$. Gielen and Dehaene add that matching improves only slightly with scaling while supply voltages, and with them signal swing, fall, so the power for fixed speed and accuracy stays about constant or rises. Calibration and offset cancellation are therefore used instead of brute-force sizing (background knowledge). Reference: ‘Implications of transistor mismatch on analog circuit design and system performance’, Chapter 3 hosted on P. Kinget’s Columbia University page (author and year not stated in the excerpt; citations to 1996) (fetch-tool summary); M. J. M. Pelgrom, H. P. Tuinhout and M. Vertregt, ‘Transistor matching in analog CMOS applications’, IEDM 1998, 915-918 (Designer’s Guide forum copy; formula 1 and figure values illegible in the extract) (fetch-tool summary); G. Gielen and W. Dehaene, ‘Analog and digital circuit design in 65 nm CMOS: end of the road?’, DATE 2005 (arXiv:0710.4709) (fetch-tool summary).

Ques: How does threshold variation affect digital circuits?

Through delay and margin. Gielen and Dehaene note that the same absolute threshold tolerance matters more at low threshold: a 50 $\mathrm{mV}$ variation is 25 per cent of a 200 $\mathrm{mV}$ threshold but 7 per cent of 700 $\mathrm{mV}$ (computed), and the shrinking overdrive $V_{DD}-V_T$ makes gate delay more sensitive, so worst-case sizing raises energy. Pelgrom et al. state that digital circuits such as flip-flops need an overdrive margin of 6 to 10 times the matching spread, and they simulated clock skew in a 0.25 $\mu \mathrm{m}$ clock tree over 200 trials. Random dopant fluctuation and line-edge roughness, which grow in importance as dopant counts fall, as $N^{1/2}$ statistics imply, make these effects worse at each node. SRAM cells, which use minimum devices, are most affected (background knowledge). Reference: G. Gielen and W. Dehaene, ‘Analog and digital circuit design in 65 nm CMOS: end of the road?’, DATE 2005 (arXiv:0710.4709) (fetch-tool summary); M. J. M. Pelgrom, H. P. Tuinhout and M. Vertregt, ‘Transistor matching in analog CMOS applications’, IEDM 1998, 915-918 (Designer’s Guide forum copy; formula 1 and figure values illegible in the extract) (fetch-tool summary).

Ques: Which layout practices reduce mismatch?

Pelgrom et al. state that matched elements must be identical in geometry, rotation, biasing and temperature, and list the environmental effects that degrade matching: distance, topography and resist crowding, metal coverage, implant striping, packaging and mechanical strain. These systematic effects are not captured by the area law, which assumes independent random disturbances with a correlation distance small compared with the device, so they must be removed by layout: placing devices close together, using the same orientation, common-centroid and interdigitated arrangements against gradients, dummy structures at array edges and avoiding metal over matched gates (background knowledge for the specific techniques). Random mismatch can then only be reduced by area, since $\sigma \propto 1/\sqrt{WL}$. Pelgrom et al. also suggest low-threshold devices or local body boost to increase signal swing. Reference: M. J. M. Pelgrom, H. P. Tuinhout and M. Vertregt, ‘Transistor matching in analog CMOS applications’, IEDM 1998, 915-918 (Designer’s Guide forum copy; formula 1 and figure values illegible in the extract) (fetch-tool summary).

Related pages in this vault: Process Corners and Statistical Models, Charge-Based Models (EKV), Binning and Geometry Scaling, Static Random Access Memory (SRAM), Surface-Potential Models (PSP and HiSIM), MOSFET Noise Models, Charge and Capacitance Modelling, RF and Non-Quasi-Static Effects, Thin-Film Metal Resistors (TaN, NiCr and SiCr), GUM Uncertainty Budgets.