Silicon on Insulator (SOI) MOSFET

1. Theory

• Definition: An SOI MOSFET is built in a thin silicon film that sits on a buried oxide (BOX) over a silicon substrate, which isolates every transistor from the substrate.
• Back gate: The substrate under the BOX acts as a second (back) gate with voltage $V_{G2}$.
• Partially depleted (PD): If the film is thicker than the maximum depletion width $W_{dm}$, a neutral, electrically floating body remains under the channel.
• Fully depleted (FD): If the film is thinner than $W_{dm}$, the whole film is depleted at threshold and the front and back gates couple through it.
• Back-gate coupling: In FD devices the front threshold shifts by $-{\alpha }_{bg}\Delta V_{G2}$, with ${\alpha }_{bg}\approx C_{BOX}/C_{ox}$ for a thin film on a thick BOX.
• Short scale length: The thin film replaces $W_{dm}$ in the scale length (${\ell }_{SOI}=\sqrt{({\epsilon }_s/{\epsilon }_{ox})t_{ox}{t}_{Si}}$), suppressing DIBL and roll-off.
• Low junction capacitance: Source and drain sit on thick oxide, so their capacitance is far smaller than bulk junctions.

2. Working Principle

• Channel operation: The front gate inverts the top of the film exactly as in a bulk MOSFET.
• Near-ideal swing (FD): With small ${\alpha }_{bg}$, the subthreshold swing approaches 60 mV/dec at 300 K.
• Body biasing (FD): Forward back bias lowers $V_{TH}$ for speed; reverse back bias raises it to cut leakage, adjustable after fabrication.
• Floating-body kink (PD): Holes from impact ionization charge the floating body, lowering $V_{TH}$ and causing a jump in drain current.
• Parasitic bipolar (PD): Source, body and drain form a lateral NPN that lowers drain breakdown; body contacts suppress it.
• Full isolation: No latch-up paths and much smaller sensitive volume for radiation strikes.
• Self-heating: The BOX conducts heat poorly, so the film warms up under high power, reducing mobility.

3. Applications

• RF front-end switches and tuners: RF-SOI dominates antenna switches and tuners in mobile phones because of its low capacitance and high isolation.
• Low-power FD-SOI SoCs: IoT, wearable and automotive chips that use body biasing to trade speed against leakage.
• Radiation-hardened electronics: Space and military ICs that need latch-up immunity and low single-event upset rates.
• High-temperature electronics: Downhole drilling, automotive and aerospace sensor electronics where junction leakage would cripple bulk CMOS.

Name	Formula	Related Formulae	Variables/Constants
Fully vs. partially depleted film	$t_{Si}\le W_{dm}(\text{FD}),t_{Si}>W_{dm}(\text{PD})$	$\begin{array}{r}{W}_{dm}=\sqrt{\frac{4{\epsilon }_s{\varphi }_F}{q{N}_A}}\\ \text{(see Long Channel MOSFET page)}\end{array}$	$\begin{array}{r}{t}_{Si}:\text{silicon film thickness}\\ W_{dm}:\text{maximum depletion width at the}\\ \text{onset of strong inversion}\end{array}$
Film and buried-oxide capacitances	$C_{Si}=\frac{{\epsilon }_s}{t_{Si}},C_{BOX}=\frac{{\epsilon }_{ox}}{t_{BOX}}$	$\begin{array}{r}{C}_{ox}=\frac{{\epsilon }_{ox}}{t_{ox}}\\ \text{(front gate oxide)}\end{array}$	$\begin{array}{r}{C}_{Si}:\text{capacitance of the depleted film}\\ \text{per unit area}\end{array}$ $\begin{array}{r}{C}_{BOX}:\text{buried oxide capacitance}\\ \text{per unit area}\end{array}$
Back-gate coupling of the front threshold (FD)	$\Delta V_{TH1}=-{\alpha }_{bg}\Delta V_{G2}$	$\begin{array}{r}{\alpha }_{bg}=\frac{C_{Si}{C}_{BOX}}{C_{ox}\left(C_{Si}+C_{BOX}\right)}\\ \approx \frac{C_{BOX}}{C_{ox}}\left(C_{Si}\gg C_{BOX}\right)\end{array}$	$\begin{array}{r}{\alpha }_{bg}:\text{back-gate coupling coefficient}\\ \text{(front threshold shift per volt}\\ \text{on the back gate)}\end{array}$ $\begin{array}{r}\text{(valid while both film surfaces are}\\ \text{depleted, before accumulation or}\\ \text{inversion forms at the back interface)}\end{array}$
Subthreshold swing (FD)	$S=\ln (10)\frac{k_{B}T}{q}\left(1+{\alpha }_{bg}\right)$	$\begin{array}{r}{m}_{FD}=1+{\alpha }_{bg}\\ \text{(replaces}m=1+C_d/C_{ox}\text{of the bulk device)}\end{array}$	$\begin{array}{r}\text{(for a thin film and thick BOX,}\\ {\alpha }_{bg}\to 0\text{and}S\to 60mV/dec\\ \text{at 300 K; compare the Long Channel}\\ \text{MOSFET page)}\end{array}$ $k_B:Boltzmannconstant$
Electrostatic scale length (FD, single gate)	${\ell }_{SOI}=\sqrt{\frac{{\epsilon }_s}{{\epsilon }_{ox}}{t}_{ox}{t}_{Si}}$	$\begin{array}{r}{\eta }_{DIBL}\propto \exp \left(-\frac{L}{2{\ell }_{SOI}}\right)\\ \text{(see Short Channel MOSFET page)}\end{array}$	$\begin{array}{r}{\ell }_{SOI}:\text{scale length of the channel}\\ \text{potential; the film thickness}\\ t_{Si}\text{replaces}{W}_{dm}\text{of the bulk}\\ \text{expression}\end{array}$ $\text{(approximate, thick BOX)}$
Source and drain junction capacitance	$C_{j,SOI}\approx \frac{{\epsilon }_{ox}{A}_{SD}}{t_{BOX}}$	$\begin{array}{r}{C}_j=\frac{{\epsilon }_{s}A}{W}\text{(bulk junction)}\\ \text{(see PN Junction Diode page)}\end{array}$	$\begin{array}{r}{A}_{SD}:\text{source or drain area over}\\ \text{the buried oxide}\end{array}$ $\begin{array}{r}\text{(the junction sits on thick oxide, so}\\ \text{the capacitance is much smaller than}\\ \text{for a bulk junction)}\end{array}$
Floating-body potential (PD)	$V_{BS}=n{V}_T\ln \left(1+\frac{I_{sub}}{I_S}\right)$	$\begin{array}{r}\frac{I_{sub}}{I_D}=C_1\exp \left(-\frac{{\varphi }_{it}}{q{\lambda }_{mfp}{E}_m}\right)\\ \text{(see Short Channel MOSFET page)}\end{array}$	$\begin{array}{r}{V}_{BS}:\text{potential of the floating body}\\ \text{relative to the source}\end{array}$ $\begin{array}{r}{I}_{sub}:\text{hole current generated by impact}\\ \text{ionization at the drain}\end{array}$ $\begin{array}{r}{I}_S,n:\text{saturation current and ideality}\\ \text{factor of the body-source junction}\end{array}$ $\begin{array}{r}\text{(steady state: the hole generation}\\ \text{current equals the forward current}\\ \text{of the body-source diode)}\end{array}$
Kink-effect threshold shift (PD)	$V_{TH}(V_{BS})=V_{TH0}+\gamma \left(\sqrt{2{\varphi }_F-V_{BS}}-\sqrt{2{\varphi }_F}\right)$	$\begin{array}{r}{V}_{SB}=-V_{BS}\\ \text{(body effect, see Long Channel MOSFET page)}\end{array}$	$\begin{array}{r}\text{(a rise in}{V}_{BS}\text{lowers}{V}_{TH}\text{, so the}\\ \text{drain current jumps upward (the kink)}\\ \text{once impact ionization charges the body)}\end{array}$
Parasitic bipolar breakdown (PD)	$B{V}_{DS}\approx \frac{B{V}_{CBO}}{{\beta }^{1/n}}$	$\begin{array}{r}\text{(same form as}B{V}_{CEO}\text{on the BJT page,}\\ \text{with source, body and drain as}\\ \text{emitter, base and collector)}\end{array}$	$\begin{array}{r}B{V}_{DS}:\text{drain breakdown voltage of the}\\ \text{floating-body device}\end{array}$ $\begin{array}{r}\beta :\text{current gain of the parasitic lateral}\\ \text{n-p-n transistor}\end{array}$ $\begin{array}{r}n:\text{empirical multiplication exponent}\\ \text{(see Avalanche Diode page)}\end{array}$
Self-heating	$\Delta T=I_D{V}_{DS}{R}_{th},R_{th}=\frac{t_{BOX}}{{\kappa }_{BOX}A}$	$\begin{array}{r}{R}_{th}=\frac{t}{\kappa A}\\ \text{(see SiC Schottky Diode page)}\end{array}$	$\begin{array}{r}\Delta T:\text{temperature rise of the film}\\ \text{above the substrate}\end{array}$ $\begin{array}{r}{\kappa }_{BOX}:\text{thermal conductivity of the}\\ \text{buried oxide (about 1.4 W/m K,}\\ \text{far below that of silicon)}\end{array}$

Important Questions

Ques: What distinguishes a fully depleted SOI MOSFET from a partially depleted one?

The distinction is the film thickness compared with the maximum depletion width $W_{dm}$ of the Long Channel MOSFET page. If $t_{Si}>W_{dm}$, the gate depletion region ends inside the film, leaving a neutral, floating body region below it, so the device behaves like a bulk MOSFET with an electrically floating body and picks up the floating-body effects described below. If $t_{Si}\le W_{dm}$, the whole film is depleted at threshold, there is no neutral body, and the front and back interfaces are coupled electrostatically through the film. The FD device therefore has better electrostatic control (smaller swing and weaker short-channel effects) and no floating-body kink, at the price of a threshold voltage that depends on the film thickness and on the back-gate voltage. Reference: J.-P. Colinge, Silicon-on-Insulator Technology: Materials to VLSI, 3rd ed., Kluwer Academic, 2004.

Ques: Why does a thin film on a thick buried oxide give a near-ideal subthreshold swing, and how does back bias control the threshold?

In a fully depleted device, a change in gate voltage divides between the front oxide and a series combination of the film and buried-oxide capacitances. The factor that sets the swing is therefore ${\alpha }_{bg}=C_{Si}{C}_{BOX}/[C_{ox}(C_{Si}+C_{BOX})]$ instead of the bulk $C_d/C_{ox}$. A thin film makes $C_{Si}$ large and a thick buried oxide makes $C_{BOX}$ small, so ${\alpha }_{bg}\approx C_{BOX}/C_{ox}$ is small and $S\to 60$ mV/dec. The same factor is the back-gate coupling: changing the substrate voltage by $\Delta V_{G2}$ shifts the front threshold by $-{\alpha }_{bg}\Delta V_{G2}$, so a forward back bias lowers $V_{TH}$ and a reverse back bias raises it, which is how fully depleted SOI devices adjust the speed and leakage trade-off after fabrication. Reference: H.-K. Lim and J.G. Fossum, “Threshold voltage of thin-film silicon-on-insulator (SOI) MOSFET’s,” IEEE Trans. Electron Devices 30, 1244 (1983); J.-P. Colinge, Silicon-on-Insulator Technology: Materials to VLSI, 3rd ed., Kluwer Academic, 2004.

Ques: What are the floating-body effects in a partially depleted device?

In a PD device the neutral body is isolated by the source and drain junctions and the buried oxide, so its potential is set by charge balance. At high drain voltage, impact ionization near the drain generates holes that flow into the body and raise its potential until the forward current of the body-source junction balances them, $V_{BS}=n{V}_T\ln (1+I_{sub}/I_S)$. This forward body bias lowers $V_{TH}$, which produces an abrupt rise in drain current (the kink) and a lower output resistance. The body also forms the base of a lateral n-p-n transistor with the source as emitter and the drain as collector; once the body is forward biased this parasitic bipolar transistor adds current and lowers the drain breakdown voltage to about $B{V}_{CBO}/{\beta }^{1/n}$. Body contacts, which tie the body to the source, remove these effects at the cost of area and speed. Reference: J.-P. Colinge, Silicon-on-Insulator Technology: Materials to VLSI, 3rd ed., Kluwer Academic, 2004.

Ques: What are the advantages and disadvantages of SOI compared with bulk silicon?

The main advantages follow from the buried oxide. Source and drain junction capacitance drops to about ${\epsilon }_{ox}{A}_{SD}/t_{BOX}$, which speeds up circuits and cuts switching power; devices are fully isolated, which removes latch-up and the parasitic substrate leakage paths; and in an FD device the thin film gives a short electrostatic scale length ${\ell }_{SOI}=\sqrt{({\epsilon }_s/{\epsilon }_{ox})t_{ox}{t}_{Si}}$, which suppresses DIBL and threshold roll-off (see the Short Channel MOSFET page). The main disadvantages are the floating-body effects of PD devices, the sensitivity of the FD threshold voltage to film thickness variation, the higher substrate cost, and self-heating: the buried oxide conducts heat poorly, so the temperature rise $\Delta T=I_D{V}_{DS}{R}_{th}$ with $R_{th}=t_{BOX}/({\kappa }_{BOX}A)$ can degrade mobility and reliability in high-power operation. Reference: J.-P. Colinge, Silicon-on-Insulator Technology: Materials to VLSI, 3rd ed., Kluwer Academic, 2004; Y. Taur and T.H. Ning, Fundamentals of Modern VLSI Devices, 2nd ed., Cambridge University Press, 2009.

Related pages in this vault: Short Channel MOSFET, Long Channel MOSFET, Schottky Barrier and Dynamic Threshold_MOSFET, Floating Body Random Access Memory (Capacitorless 1T DRAM), Double-Gate MOSFET, Junctionless Transistor, Radiation, Multi-Gate Models (BSIM-CMG and BSIM-IMG), CMOS Logic Transistors, Laser Annealing System, Flash Lamp Annealing System.