1. Theory

Definition: On-chip ESD protection devices are diodes, snapback transistors such as the grounded-gate NMOS (GGNMOS), silicon-controlled rectifiers (SCRs) and RC-triggered power clamps, placed at the pads and between the supply rails to conduct electrostatic discharge current around the internal circuits (Jiang et al.; Tseng et al.; Yeh et al.).
Stress models: Protection is rated against the human body model, a 100 $pF$ discharge through 1500 $Ω$ with about 0.67 A per kV, and the charged device model, a discharge of the package itself of about 2 to 30 A in less than 1 $ns$ (Thermo Fisher).
Design window: A protection device must trigger below the breakdown of the gate oxides it protects, must not trigger or latch during normal operation, and must carry the discharge current with a low on-resistance (Jiang et al.; Lee and Koo).
Robustness: The failure current $I_{t 2}$ , measured with 100 $ns$ transmission-line pulses, sets the HBM rating, of the order of 6 to 7 $mA/ μ m$ for a silicided GGNMOS (Jiang et al.; computed).
Latch-up: SCRs and snapback devices hold at a low voltage once on, so a holding voltage below the supply risks latch-up unless the trigger current is high (Tseng et al.; Lee and Koo).

2. Working Principle

Diodes: Forward-biased diodes steer pad current to the supply rails, where the rail clamp completes the path, and reverse diodes break down only at high voltage (background knowledge; Yeh et al.).
GGNMOS snapback: The drain junction avalanches at $V_{t 1}$ , the hole current raises the local substrate potential and turns on the parasitic lateral NPN, and the voltage snaps back to $V_{h}$ while the device conducts amperes until thermal failure at $I_{t 2}$ (Jiang et al.; background knowledge for the mechanism).
SCR: The coupled parasitic PNP and NPN transistors regenerate once triggered, holding at a very low voltage, which gives the highest current per area but the highest latch-up risk; inserted NMOS or gate-coupled structures lower the trigger voltage (Tseng et al.; Lee and Koo).
RC-triggered clamp: An RC detector senses the fast rise of an ESD event and turns on a large MOSFET between the rails for about the RC time, while slow power-on ramps leave it off (Yeh et al.).

3. Applications

I/O pad protection: Diodes to both rails with a rail clamp, or GGNMOS and SCR devices at the pads, in every CMOS chip (Jiang et al.; Yeh et al.).
Power-rail clamps: RC-triggered BigFET clamps between VDD and VSS, which also complete the diode paths of pad discharges (Yeh et al.).
High-voltage and BCD products: SCR-based protection with raised holding voltage for 5 $V$ and higher supplies (Lee and Koo).
Qualification: Component ESD classes under JS-001 HBM and JS-002 CDM for data sheets and handling (Thermo Fisher).

ESD Stress Models

Name	Formula	Related Formulae	Variables/Constants
Human body model discharge	$I_{p} \approx \frac{V _{H B M}}{R _{H B M}}, τ_{H B M} = R_{H B M} C_{H B M}$	$E = \frac{1}{2} C_{H B M} V_{H B M}^{2}$	$I_{p} : p e ak d i sc ha r g e c u r r e n t in t o a s h or t$ $V_{H B M} : p r ec ha r g e v o l t a g e$ $R_{H B M} : 1500 Ω ser i es r es i s t an ce$ $C_{H B M} : 100 pF b o d y c a p a c i t an ce$ $τ_{H B M} : d ec a y t im e co n s t an t$ $E : s t or e d e n er g y (t im e co n s t an t an d e n er g y, ba c k g r o u n d k n o w l e d g e); T h er m o F i s h er : H B M p er A N S I / E S D A / J E D E C J S - 001 w i t h 1500 Ω an d 100 pF, a r i se t im e o f ab o u t 6 ns in t o a s h or t, an d an a v er a g e p e ak o f 0.67 A f or 1000 V; c l a sses f r o m 0 Z (b e l o w 50 V) t h r o ug h 1 C (1000 t o 2000 V) an d 2 (2000 t o 4000 V) t o 3 B (8000 V an d ab o v e); t h e ma c hin e m o d e l (200 pF, 0 Ω) ha s b ee n e l imina t e d a s a s t an d a r d t es t, l e a v in g H B M an d C D M$ $(co m p u t e d : 1, 2 an d 4 kV g i v e 0.67, 1.33 an d 2.67 A; τ_{H B M} = 150 ns; 2 kV s t or es 0.2 mJ)$
Charged device model and transmission line pulse	$I_{C D M} \approx 2 to 30 A, t_{C D M} < 1 ns$	$TLP: t_{w} = 100 ns, t_{r} = 10 ns, V_{H B M} \approx (1500 + R_{o n}) I_{t 2}$	$I_{C D M} : p e ak C D M c u r r e n t$ $t_{C D M} : C D M d i sc ha r g e d u r a t i o n$ $t_{w}, t_{r} : T L P p u l se w i d t h an d r i se t im e$ $R_{o n} : o n - r es i s t an ce o f t h e p r o t ec t i o n d e v i ce in s na p ba c k$ $I_{t 2} : seco n d - b r e ak d o w n (f ai l u r e) c u r r e n t f r o m T L P; T h er m o F i s h er : C D M p er J S - 002 w i t h 6.8 or 55 pF v er i f i c a t i o n m o d u l es, d i sc ha r g es s h or t er t han 1 ns an d p e ak s o f ab o u t 2 t o 30 A, c l a sses C 0 a (b e l o w 125 V) t o C 3 (1000 V an d ab o v e, t es t in g ab o v e 1000 V n o t r eco mm e n d e d), an d e a c h p a r t c l a ss i f i e d u n d er b o t h H B M an d C D M; T se n g e t a l ., J ian g e t a l . an d L ee an d K oo : T L P w i t h 100 ns p u l ses an d 10 ns r i se an d f a l l; J ian g e t a l . : t h e H B M l e v e l es t ima t e d f r o m I_{t 2} b y t h e e x p r ess i o n ab o v e$ $(n o co m p u t e d v a l u e)$

Design Window and Snapback Devices

Name	Formula	Related Formulae	Variables/Constants
ESD design window	$V_{D D} + Δ V < V_{h}, V_{t 1} < B V_{o x}$	$V_{t 2} > V_{t 1} (uniform multi-finger turn-on), B V_{o x} \approx E_{B D} t_{o x}$	$V_{D D} : s u ppl y v o l t a g e$ $Δ V : s a f e t y ma r g in$ $V_{h} : h o l d in g v o l t a g e in s na p ba c k$ $V_{t 1} : t r i g g er v o l t a g e$ $B V_{o x} : b r e ak d o w n v o l t a g e o f t h e g a t e o x i d e t o b e p r o t ec t e d$ $V_{t 2} : v o l t a g e a t seco n d b r e ak d o w n$ $E_{B D} : o x i d e b r e ak d o w n f i e l d$ $t_{o x} : o x i d e t hi c k n ess (B V_{o x} es t ima t e, ba c k g r o u n d k n o w l e d g e); J ian g e t a l . : V_{t 1} b e l o w B V_{o x} an d ab o v e V_{D D} w i t h ma r g in, V_{h} ab o v e V_{D D} a g ain s t l a t c h - u p b u t l o w t o l imi t d i ss i p a t i o n, R_{o n} minimi z e d, an d V_{t 2} ab o v e V_{t 1} f or m u l t i - f in g er d e v i ces; L ee an d K oo : V_{h} ab o v e t h e o p er a t in g v o l t a g e an d V_{T} b e l o w t h e b r e ak d o w n o f in t er na l e l e m e n t s an d t h e g a t e o x i d e; T se n g e t a l . : V_{h} t u n e d ab o v e V_{D D} f or l a t c h - u p imm u ni t y, w i t h J E S D 78 t r i g g er c u r r e n t o f 100 mA a s t h e s p ec i f i c a t i o n$ $(co m p u t e d : an a ss u m e d 11 MV/cm o n T se n g e t a l .^{'} s 7 nm o x i d e g i v es B V_{o x} o f ab o u t 7.7 V, b e l o w t h e 9.02 V t r i g g er o f t h e i r GGN M O S)$
Grounded-gate NMOS in snapback	$R_{o n} = \frac{\partial V _{D S}}{\partial I _{D S}}, V \approx V_{h} + I R_{o n}$	$\frac{I _{t 2}}{W}, R_{o n, l o n g} = \frac{R _{50}}{W /50} (ideal scaling, not achieved)$	$R_{o n} : d i f f er e n t ia l o n - r es i s t an ce$ $V_{D S}, I_{D S} : d r ain v o l t a g e an d c u r r e n t$ $V_{h} : h o l d in g v o l t a g e, I_{t 2} / W : f ai l u r e c u r r e n t p er w i d t h$ $W : t o t a l w i d t h in μ m$ $R_{50} : o n - r es i s t an ce o f a 50 μ m f in g er; J ian g e t a l . (0.13 μ m s i l i c i d e C M O S) : o pt im u m c hann e l l e n g t h ab o u t 0.5 μ m, o pt im u m so u r ce - t o - b u l k s p a c in g 5 μ m, s in g l e f in g er s w i d er t han 50 μ m t u r n o n n o n - u ni f or m l y (R_{o n} 4.11 Ω a t 50 μ m b u t 3.95 Ω a t 400 μ m), f o u r - f in g er 200 μ m l a y o u t s r e a c h R_{o n} o f 1.34 t o 1.87 Ω an d I_{t 2} o f 1.26 t o 1.48 A in 1221 t o 1765 μ m^{2}, V_{h} r i ses w i t h c hann e l l e n g t h an d V_{t 1} o n l y s l i g h tl y; T se n g e t a l . (0.32 μ m C M O S, 7 nm o x i d e, W / L = 200/0.35 μ m) : GGN M O S V_{t 1} o f 9.02 V an d 21.5 V/ μ m o f H B M p er w i d t h; s na p ba c k i s t h e t u r n - o n o f t h e p a r a s i t i c l a t er a l N P N a f t er a v a l an c h e a t t h e d r ain (ba c k g r o u n d k n o w l e d g e)$ $(co m p u t e d : 1.26 t o 1.48 A in 200 μ m i s 6.3 t o 7.4 mA/ μ m, an d (1500 + R_{o n}) I_{t 2} g i v es 1.9 t o 2.2 kV H B M; 21.5 V/ μ m x 200 μ m = 4.3 kV)$

SCRs, Diodes and Rail Clamps

Name	Formula	Related Formulae	Variables/Constants
Silicon-controlled rectifier and latch-up	$β_{n p n} β_{p n p} \geq 1 (regenerative latch), V_{h} < V_{D D} \Rightarrow latch-up risk$	$I_{t r i g} > I_{LU, s p ec} = 100 mA (JESD78)$	$β_{n p n}, β_{p n p} : c u r r e n t g ain s o f t h e co u pl e d p a r a s i t i c bi p o l a r t r an s i s t or s$ $V_{h} : h o l d in g v o l t a g e$ $I_{t r i g} : t r i g g er c u r r e n t$ $I_{LU, s p ec} : l a t c h - u p t es t c u r r e n t (r e g e n er a t i o n co n d i t i o n, ba c k g r o u n d k n o w l e d g e); T se n g e t a l . : a co n v e n t i o na l S C R h o l d s a t 1.3 V an d t r i g g er s a t ab o u t 7 mA, w hi l e t h e i r e mb e dd e d S C R in a g a t e - co u pl e d N M O S t r i g g er s a t 3.8 V, h o l d s a t 2.2 V an d n ee d s ab o u t 247 t o 250 mA t o t r i g g er, ab o v e t h e 100 mA J E S D 78 s p ec i f i c a t i o n, w i t h 32.5 V/ μ m o f H B M p er w i d t h; L ee an d K oo (0.18 μ m B C D, 5 V a ppl i c a t i o n) : a co n v e n t i o na l S C R w i t h V_{T} o f 21.88 V (ab o v e 11 V in t h e t e x t), V_{H} o f 3.6 V an d I_{t 2} o f 6.3 A, an d t h e i r N M O S - in ser t e d S C R w i t h V_{T} o f 9.4 t o 10.58 V, V_{H} o f 3.41 t o 7.24 V r i s in g w i t h t h e f l o a t in g N + l e n g t h, I_{t 2} o f 5.36 t o 6.95 A an d 6 kV H B M; a h o l d in g v o l t a g e o f ab o u t 2 V mak es a co n v e n t i o na l S C R p r o n e t o l a t c h - u p$ $(co m p u t e d : 32.5 V/ μ m x 200 μ m = 6.5 kV; t h e e mb e dd e d S C R^{'} s t r i g g er c u r r e n t i s 2.5 t im es t h e J E S D 78 t es t c u r r e n t, t h o ug h i t s 2.2 V h o l d in g v o l t a g e i s s t i l l b e l o w a 3.3 V s u ppl y)$
RC-triggered power-rail clamp and diodes	$t_{r, E S D} ≪ τ_{R C} ≪ t_{r, p o w er - o n}$	$V_{p a d} \approx V_{D} + I (R_{D} + R_{b u s}) + V_{c l am p} (pad to VDD diode, then rail clamp)$	$t_{r, E S D} : r i se t im e o f an E S D e v e n t (ab o u t 5 t o 10 ns)$ $τ_{R C} : t im e co n s t an t o f t h e c l am p^{'} s R C d e t ec t or$ $t_{r, p o w er - o n} : r i se t im e o f t h e n or ma l s u ppl y$ $V_{p a d} : p a d v o l t a g e d u r in g d i sc ha r g e$ $V_{D}, R_{D} : f or w a r d v o l t a g e an d ser i es r es i s t an ce o f t h e E S D d i o d e$ $R_{b u s} : b u s r es i s t an ce$ $V_{c l am p} : c l am p v o l t a g e (d i o d e - an d - c l am p p a t h, ba c k g r o u n d k n o w l e d g e; j u n c t i o n p h y s i cs o n t h e P N J u n c t i o n p a g e); Y e h e t a l . (0.13 μ m C M O S, B i g F E T w i t h L = 0.18 μ m an d W = 2000 μ m, r e a d in g t h e p r in t e d m p r e f i x es a s mi cr o) : R C co n s t an t s o f 0.1, 0.5 an d 1.0 μ s, a 1.2 V p o w er - o n w i t h 1 m/s r i se (ab o u t 18 mV o f g a t e r i ppl e) an d a 3.0 V, 5 ns E S D - l ik e p u l se; H B M l e v e l s o f 4.5 t o ab o v e 8.0 kV d e p e n d in g o n R C an d d r ain - t o - g a t e s p a c in g (0.22 t o 0.44 μ m), w i t h 0.5 μ s g i v in g t h e hi g h es t I_{t 2} an d l o w es t o n - r es i s t an ce; t h e H B M p u l se l a s t s ab o u t 100 ns (ha l f - e n er g y)$ $(co m p u t e d : 0.5 μ s i s ab o u t 3 t im es t h e 150 ns H B M d ec a y an d 2000 t im es s h or t er t han a 1 m/s p o w er - o n r am p)$

Important Questions

Ques: How large is the current in a human body model discharge?

The human body model of JS-001 discharges 100 $pF$ through 1500 $Ω$ , so the peak current into a short is about $V /1500$ : 0.67 A for 1 $kV$ , matching the average Thermo Fisher quotes, 1.33 A for 2 $kV$ and 2.67 A for 4 $kV$ (computed). The current rises in about 6 $ns$ and decays with a time constant of 150 $ns$ (computed), and 2 $kV$ stores 0.2 $mJ$ (computed). A protection device must therefore conduct amperes for about 100 $ns$ without failing, which is why 100 $ns$ transmission-line pulses with 10 $ns$ rise are used to measure the failure current $I_{t 2}$ . The charged device model is shorter and stronger, 2 to 30 A in less than 1 $ns$ , and the machine model has been dropped, so parts are now classified under HBM and CDM. Reference: Thermo Fisher Scientific, ‘ESD Semiconductor Qualification’ web page (HBM, MM, CDM models and JS-001/JS-002 classes) (fetch-tool summary); Jiang Y., Li J., Ran F., Cao J. and Yang D., ‘Influence of layout parameters on snapback characteristic for a gate-grounded NMOS device in 0.13-um silicide CMOS technology’, Journal of Semiconductors 30(8), 084007 (2009) (fetch-tool summary).

Ques: Does a protection device with It2 of 6.89 A pass about 10 kV HBM or 6 kV?

The two values come from different methods. Jiang et al. estimate the HBM level as $(1500 + R_{o n}) I_{t 2}$ , which for Lee and Koo’s NMOS-inserted SCR with $I_{t 2}$ of 6.89 A gives about 10.3 $kV$ , and for the 5.36 A variant about 8.0 $kV$ (computed). Lee and Koo measured 6 $kV$ HBM for all their variants. The estimate assumes that the 100 $ns$ TLP failure current applies to the HBM pulse, which decays over 150 $ns$ and so heats the device longer, and it ignores the tester’s own limits (my reading). It may also be that 6 $kV$ was the highest level tested (my reading). For the GGNMOS of Jiang et al., the same estimate gives 1.9 to 2.2 $kV$ for 1.26 to 1.48 A (computed). The measured 6 $kV$ is the more reliable rating, and the formula is an upper estimate. Reference: Jiang Y., Li J., Ran F., Cao J. and Yang D., ‘Influence of layout parameters on snapback characteristic for a gate-grounded NMOS device in 0.13-um silicide CMOS technology’, Journal of Semiconductors 30(8), 084007 (2009) (fetch-tool summary); B.-S. Lee and Y.-S. Koo, ‘SCR-based ESD Protection Circuit with Low Trigger Voltage and High Robustness by Inserting the NMOS Structure’, Journal of Semiconductor Technology and Science 19(3), 300-304 (2019), doi:10.5573/JSTS.2019.19.3.300 (fetch-tool summary).

Ques: Why does a GGNMOS need a lower trigger voltage in thin-oxide processes?

Because the trigger voltage must stay below the breakdown voltage of the oxides it protects. Tseng et al. measured a GGNMOS trigger of 9.02 $V$ in a 0.32 $μ m$ process with a 7 $nm$ gate oxide. With an assumed breakdown field of 11 $MV/cm$ , that oxide fails near 7.7 $V$ (computed), so a fast ESD event could break down an input gate before the GGNMOS turns on. Their embedded-SCR gate-coupled NMOS triggers at 3.8 $V$ , well inside the window, and Lee and Koo similarly lowered an SCR trigger from 21.88 $V$ to about 9.4 to 10.6 $V$ by inserting an NMOS. Jiang et al. list the full design window: trigger above the supply with margin but below oxide breakdown, holding voltage above the supply, low on-resistance, and second-breakdown voltage above the trigger so that all fingers turn on. Reference: J.-C. Tseng, C.-T. Hsu, C.-K. Tsai, Y.-C. Liao and M.-D. Ker, ‘ESD Protection Design for Low Trigger Voltage and High Latch-Up Immunity’, IPFA 2010 (Table 1 garbled in the text) (fetch-tool summary); B.-S. Lee and Y.-S. Koo, ‘SCR-based ESD Protection Circuit with Low Trigger Voltage and High Robustness by Inserting the NMOS Structure’, Journal of Semiconductor Technology and Science 19(3), 300-304 (2019), doi:10.5573/JSTS.2019.19.3.300 (fetch-tool summary); Jiang Y., Li J., Ran F., Cao J. and Yang D., ‘Influence of layout parameters on snapback characteristic for a gate-grounded NMOS device in 0.13-um silicide CMOS technology’, Journal of Semiconductors 30(8), 084007 (2009) (fetch-tool summary).

Ques: Why do multi-finger GGNMOS devices need careful layout?

Because snapback is a local, regenerative process, and the first finger to trigger can take all the current and fail before the others turn on. Jiang et al. found that single fingers wider than about 50 $μ m$ turn on non-uniformly: the on-resistance fell only from 4.11 to 3.95 $Ω$ from 50 to 400 $μ m$ , instead of eightfold. Splitting 200 $μ m$ into four 50 $μ m$ fingers gave 1.34 to 1.87 $Ω$ and failure currents of 1.26 to 1.48 A, 6.3 to 7.4 $mA/ μ m$ (computed), depending on how sources, drains and bulk contacts alternate, with layouts of 1221 to 1765 $μ m^{2}$ . They recommend a channel length of about 0.5 $μ m$ and a source-to-bulk spacing of 5 $μ m$ , and require the second-breakdown voltage to exceed the trigger voltage, so that a finger near failure forces the others on. Reference: Jiang Y., Li J., Ran F., Cao J. and Yang D., ‘Influence of layout parameters on snapback characteristic for a gate-grounded NMOS device in 0.13-um silicide CMOS technology’, Journal of Semiconductors 30(8), 084007 (2009) (fetch-tool summary).

Ques: Can an SCR with a holding voltage below the supply still be used safely?

Only with a high trigger current. A conventional SCR holds at about 1.3 $V$ and triggers at about 7 $mA$ in Tseng et al.’s 0.32 $μ m$ process, so a small disturbance could latch it across a 3.3 $V$ supply. Their embedded SCR raises the holding voltage to 2.2 $V$ , still below 3.3 $V$ , but needs about 250 $mA$ to trigger, 2.5 times the 100 $mA$ JESD78 latch-up test current (computed), so normal disturbances cannot latch it. Lee and Koo take the other route for 5 $V$ BCD products: lengthening a floating N+ region raised the holding voltage from 3.41 to 7.24 $V$ , above the supply, at a cost in failure current from 6.89 to 5.36 A. Both approaches keep the SCR’s high current per area while avoiding latch-up in normal operation. Reference: J.-C. Tseng, C.-T. Hsu, C.-K. Tsai, Y.-C. Liao and M.-D. Ker, ‘ESD Protection Design for Low Trigger Voltage and High Latch-Up Immunity’, IPFA 2010 (Table 1 garbled in the text) (fetch-tool summary); B.-S. Lee and Y.-S. Koo, ‘SCR-based ESD Protection Circuit with Low Trigger Voltage and High Robustness by Inserting the NMOS Structure’, Journal of Semiconductor Technology and Science 19(3), 300-304 (2019), doi:10.5573/JSTS.2019.19.3.300 (fetch-tool summary).

Ques: How is the RC time constant of a power-rail ESD clamp chosen?

It must be much longer than the rise of an ESD event, so that the clamp stays on for the whole discharge, but much shorter than the rise of the normal supply, so that power-on does not trigger it. Yeh et al. tested 0.1, 0.5 and 1.0 $μ s$ with a BigFET of 2000 $μ m$ width in 0.13 $μ m$ CMOS (reading the printed prefixes as micro), against a 5 $ns$ ESD-like pulse and a 1 $m/s$ power-on ramp, which left only about 18 $mV$ of gate ripple. The 0.5 $μ s$ design gave the highest failure current and HBM levels above 8 $kV$ with the widest drain-to-gate spacing. It is about three times the 150 $ns$ HBM decay and 2000 times shorter than the power-on ramp (computed). Narrower drain-to-gate spacing lowered the rating to 4.5 to 5.5 $kV$ . Reference: C.-T. Yeh, Y.-C. Liang and M.-D. Ker, ‘The Impact of BIGFET Clamp Device Layout on ESD Protection Circuit Robustness’, International ESD Workshop 2008 (micro prefixes rendered as m in the text) (fetch-tool summary); Thermo Fisher Scientific, ‘ESD Semiconductor Qualification’ web page (HBM, MM, CDM models and JS-001/JS-002 classes) (fetch-tool summary).

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On-Chip ESD Protection Devices