Electrical Stress

Electrical stress is the damage caused by voltage, current and power beyond what a device can take, and by long exposure to fields and energetic carriers that are within the ratings. This page covers breakdown of the gate dielectric, hot-carrier and bias-temperature degradation of transistors, overstress by electrostatic discharge and other events, latch-up, and the avalanche and short-circuit ruggedness of power devices. Heating by the dissipated power is on the Thermal Stress page, forces on joints and packages are on the Mechanical and Package Stress page, the wear-out of metal lines by current belongs to other pages of this folder, and the statistics of lifetime are on the Failure Rate and the Bathtub Curve page.

1. Why It Happens

• Trigger: A voltage, current or power above the limit of the device, called electrical overstress, whose causes are over-voltage, over-current or over-power and include ESD as one kind (Welsher); an input or output voltage above the supply or below ground, a fast rise of the supply, a supply high enough for transistor breakdown, and ionising radiation for latch-up (Haseloff); a strong field across the oxide in normal operation for breakdown and for degradation of transistors (arXiv review); an inductive load that forces avalanche, or a short circuit of the load (Nexperia; Wolfspeed).
• Mechanism, dielectric breakdown: Under strong fields, 5 to 10 $MV/cm$, defects and traps form in the oxide and shift the threshold voltage; a conductive percolation path then forms between the gate and the substrate (soft breakdown) and raises the leakage; the heating by the leakage ends in thermal runaway that breaks the layer (hard breakdown) (arXiv review). The time to breakdown is described by an exponential in the field (E model), an exponential in the inverse field (1/E model) or a power law in the voltage, and the sources disagree on which applies where (see the first question below). Breakdown at weak spots is extrinsic and the breakdown of good oxide is intrinsic (Verweij and Klootwijk).
• Mechanism, hot carriers: Carriers accelerated by the lateral field in the channel gain enough energy to create interface traps, with a threshold of 3.7 $\mathrm{eV}$ in the original model, and some also cause impact ionisation, which shows as substrate current (Triebl). The damage shifts the threshold voltage, the linear and saturation drain current and the transconductance (arXiv review).
• Mechanism, bias temperature instability: With a gate bias and a raised temperature the threshold voltage drifts as a power of time through interface states and oxide charge, $\Delta V_{th}=(\Delta Q_{it}+\Delta Q_{ox})/C_{ox}$, and part of it recovers when the stress ends. No reviewed model reproduces the stress phase and the recovery phase with the same parameters, so the microscopic origin, reaction-diffusion or charge trapping, is not settled (Grasser et al.).
• Mechanism, overstress and ESD: A pulse heats a small volume of junction, metal or dielectric. Between about 0.1 and 20 $\mu \mathrm{s}$ the power that causes failure falls as the inverse square root of the pulse width (Orvis et al.). High currents melt regions of the semiconductor (human-body model) and high fields rupture dielectrics (charged-device model) (Agarwal).
• Mechanism, latch-up: The n-p-n and p-n-p parasitic transistors of CMOS form a thyristor between the supply and ground; if the product of their gains exceeds one and a trigger turns it on, a low-impedance path stays after the trigger is removed (TU Graz page; Haseloff).
• Mechanism, power devices: In avalanche the junction heats until its temperature exceeds the maximum, with catastrophic failure at roughly 380 ${}^{\circ }\mathrm{C}$ (Nexperia). In a short circuit of a SiC MOSFET, high current at high voltage gives thermal runaway, reflowed top metal can reach the SiC and short the drain to the source, the expansion mismatch can crack the edges of the gate oxide so that the gate shorts to the source, and leakage through the base can turn on the parasitic bipolar transistor (Wolfspeed). In a survey of 40 failures, gate-oxide breakdown accounted for 62 per cent and thermal runaway for 38 per cent (Ceccarelli et al.).
• What sets the rate: For oxide breakdown the field and the temperature, and the area through the Weibull slope (Gurfinkel et al.); for hot carriers the channel length, the lateral and oxide fields, and the substrate current (arXiv review; Triebl); for bias temperature instability the gate voltage, the temperature, the duty cycle and the time exponent (arXiv review; Grasser et al.); for overstress the power and the width of the pulse (Orvis et al.); for latch-up the injected current, the temperature and the gains (Haseloff); for avalanche the energy $\frac{1}{2}L{I}^2$, the junction temperature and the thermal impedance (Nexperia); for a short circuit the bus voltage and the case temperature (Ceccarelli et al.).
• Failure criterion: Hard breakdown of the oxide, or a soft breakdown that the circuit cannot tolerate (arXiv review); a drift of the threshold voltage, the drain current or the transconductance beyond what the product accepts, a limit that the sources do not give; immediate damage, or latent damage that shortens the life in an unpredictable way (Welsher); a supply current that rises in the latch-up test (Haseloff); a junction temperature above the maximum in avalanche (Nexperia); and in a short-circuit test the last pulse after which the device can still be turned off without loss of function (Wolfspeed).

2. Where to Look

• Location: The gate oxide, which is the most common site of damage from ESD (Agarwal); the edges of the gate oxide in a SiC MOSFET (Wolfspeed); the input and output pins and the circuits behind them (Agarwal); metal lines that act as fuses, and junctions and contacts that suffer contact spikes or melting (Agarwal); the drain end of the channel for hot carriers, where the lateral field is highest (my reading from Triebl, who names the maximum lateral field); the top metal, the wire bonds and the active cells of a power device after a short circuit (Wolfspeed).
• Signature: Shorts, opens or leakage at the pins and a high supply current (Agarwal); a gate leakage that rises before breakdown, with a negative correlation between the gate leakage and the time to breakdown in constant-voltage tests (screening paper); a shifted threshold voltage with a lower drain current and transconductance for hot carriers and bias temperature instability (arXiv review); a supply current that rises and stays until the power is cycled for latch-up (Haseloff; TU Graz page); melted silicon, fused interconnect, damaged package material or fused bond wires for overstress, called electrically induced physical damage when the cause is not known (Welsher); and for a SiC MOSFET after a short circuit a device that still blocks voltage but cannot be turned on, which points to a gate-source short, or one with a drain-source short (Wolfspeed).
• Confirm with: Curve tracing and emission or OBIRCH microscopy to find the hot spot, then plasma or chemical etching, which in one example showed a pinhole, and decapsulation with SEM, which shows burnt metallisation even when the pins look normal (Agarwal). For a power device, parametric checks before and after the test, since a parametric failure is only seen that way (Wolfspeed). For latch-up, injection of current at each input and output at the maximum supply voltage while the supply current is watched (Haseloff).
• Look-alikes: Melting of metal is also seen after an ESD-HBM event, so melting alone does not prove overstress from another cause (Agarwal). Charred damage is often labelled EOS without knowing the electrical conditions (Welsher). A high ESD rating says nothing about the other causes of overstress (Welsher; Industry Council). A bias-temperature shift depends on the delay before the measurement because the shift recovers (Grasser et al.), and a shift of the threshold voltage can also come from hot carriers (arXiv review).

3. Prevention

• Design: Define realistic absolute maximum ratings and make sure that supplier and customer understand them (Welsher). Keep the oxide field low, since the life rises exponentially as the field falls (the first two rows). Use a longer channel and a lower drain voltage against hot carriers, since the shift scales as $L^{-n}$ (my reading of the empirical row). Put guard rings around critical parts, use an epitaxial layer, and place a resistor in series with the supply to keep the current below the holding current (Haseloff; TU Graz page). Choose a part rated for avalanche energy in inductive loads (Nexperia), and use desaturation turn-off in short-circuit protection, which stopped the event before 0.2 $\mathrm{J}$ in the example (Wolfspeed).
• Material and process: Keep the interface traps and oxide traps of the gate stack low, since they are the two intrinsic defect types that a review of SiC gate oxides names (Li et al., abstract only; that keeping them low helps is background knowledge); in SiC a thinner gate oxide for a low threshold voltage worsens the gate leakage at high temperature (Ceccarelli et al.). Screen the gate oxide by its leakage current to remove extrinsic failures (screening paper).
• Operation: Keep voltages and transients within the ratings, since ESD protection does not cover the other causes (Welsher). Stay within the repetitive avalanche limits, which are a rise of 30 $\mathrm{K}$ per event and a junction temperature below 175 ${}^{\circ }\mathrm{C}$ (Nexperia). A duty cycle of 0.5 reduces the bias-temperature shift to about 0.78 of the DC value (computed from the AC relation). Follow ESD control in handling, for which 500 $\mathrm{V}$ human-body model is stated to allow safe manufacturing (Texas Instruments).
• Screening and test: Constant-voltage breakdown tests with Weibull analysis and area scaling to project the life (Gurfinkel et al.); gate-leakage screening (screening paper); the latch-up injection test (Haseloff); short-circuit tests up to the last pass pulse, with the critical energy as the figure of merit (Wolfspeed); the avalanche rating by energy (Nexperia); and qualification to the human-body model (Texas Instruments).

Dielectric Breakdown

Name	Formula	Related Formulae	Variables/Constants
Time to breakdown, thermochemical E model	$t_{63}=A_E{e}^{-\gamma E_{ox}}{e}^{E_a/(k_{B}T)}$	$P_{eff}=k_{B}T\gamma$ $\frac{t_1}{t_2}=e^{\gamma (E_2-E_1)}$	$\begin{array}{r}{t}_{63}:timeatwhich63.2percentofthe\\ capacitorshavebrokendown\end{array}$ $A_E:pre-factor$ $\gamma :fieldaccelerationfactor$ $E_{ox}:fieldintheoxide$ $E_a:activationenergy$ $k_B:Boltzmannconstant8.617\times 10^{-5}eV/K$ $T:absolutetemperature$ $\begin{array}{r}{P}_{eff}:effectivedipolemomentofthebond\\ thatbreaks\end{array}$ $\begin{array}{r}{t}_{1}and{t}_2:timestobreakdownatthefields\\ E_{1}and{E}_{2}atthesametemperature(my\\ derivation),Gurfinkeletal.for\\ 4H-SiC/\mathrm{Si}{\mathrm{O}}_{2}capacitors:\gamma isabout4.6\\ cm/MVabove8.5MV/cmand2.07to3.22\\ cm/MVatlowfields,P_{eff}is11.3to14.0\\ \mathrm{e}\mathring{\mathrm{A}},E_{a}isabout1\mathrm{eV}and1.1\mathrm{eV}at7.0\\ MV/cm,thesourceprintsthetemperature\\ factoras\exp (-E_a/(k_{B}T)),whichwouldletthe\\ lifegrowwithtemperature,andItake\\ thatasasignslipandwrite\exp (+E_a/(k_{B}T))\\ (myreading),thearXivreview:theE\\ modelisbondbreakingdrivenbytheoxide\\ fieldandtemperatureandisapplied\\ mainlytothick\mathrm{Si}{\mathrm{O}}_2,Verweijand\\ Klootwijk:itdescribestheintrinsic\\ breakdown\end{array}$ $\begin{array}{r}(computed:for\gamma =4.6cm/MVat300\mathrm{K},P_{eff}\\ =11.9\mathrm{e}\mathring{\mathrm{A}},whichliesintherangethat\\ thesourcegivesforitslow-fieldvalues;\\ loweringthefieldfrom10to8MV/cm\\ lengthensthelifeby9.9\times 10^{3}timesfor\gamma =\\ 4.6,by626timesfor3.22andby63times\\ for2.07)\end{array}$
Time to breakdown, anode hole injection 1/E model	$t_{BD}={\tau }_0{e}^{G/E_{ox}}$	$t_{BD}=z_0{e}^{G{X}_{eff}/V_{ox}}$	$t_{BD}:timetobreakdown$ ${\tau }_0:pre-factor$ $G:fieldaccelerationfactorofthismodel$ $E_{ox}:fieldintheoxide$ $z_0:pre-factorofthethinningmodel$ $X_{eff}:effectivethicknessofaweakspot$ $\begin{array}{r}{V}_{ox}:voltageacrosstheoxide,Verweijand\\ Klootwijk:thesecondformisthethinning\\ modelofLee,ChenandHuforweakspots,\\ withextrinsicbreakdownanexponential\\ functionoftheinverseoxidefield,Gis\\ namedthefieldaccelerationfactorandno\\ valueisgiven,andtheequationis\\ garbledinthefetchsummaryandwritten\\ hereasread,Gofabout300to350MV/cm\\ forthin\mathrm{Si}{\mathrm{O}}_{2}isbackgroundknowledge,the\\ arXivreview:acurrent-drivenmodelin\\ whichthetimefallsexponentiallywith\\ theinversefieldandwhichisoften\\ appliedtohigh-kdielectrics\end{array}$ $\begin{array}{r}(computedwithanassumedG=320MV/cm:\\ loweringthefieldfrom10to8MV/cm\\ lengthensthelifeby2981timesagainst\\ 9897timesfortheEmodelwith\gamma =4.6,\\ andfrom8.5to6MV/cmby6.5\times 10^{6}times\\ against9.9\times 10^{4}times,soatlowfieldthe\\ 1/Emodelpromisesmuchmorelife)\end{array}$
Charge to breakdown and Fowler-Nordheim current	$t_{BD}=\frac{Q_{BD}}{J_{use}}$	$J=A_{FN}{E}_{ox}^2{e}^{-B_{FN}/E_{ox}}$	$t_{BD}:timetobreakdown$ $\begin{array}{r}{Q}_{BD}:chargeperareathattheoxidepasses\\ beforeitbreaksdown\end{array}$ $\begin{array}{r}{J}_{use}:currentdensitythroughtheoxidein\\ use\end{array}$ $J:tunnellingcurrentdensity$ $\begin{array}{r}{A}_{FN}and{B}_{FN}:constantsthatdonotdependon\\ thefield\end{array}$ $\begin{array}{r}{E}_{ox}:fieldintheoxide,Verweijand\\ Klootwijk:Q_{BD}isabout20C/c{\mathrm{m}}^{2}belowa\\ stresscurrentdensityof0.05(theunit\\ camethroughasA/cmandIreadA/c{m}^2)(my\\ reading),theirstresstestsused10.8to\\ 11.6MV/cminoxidesof10.7to11\mathrm{nm},\\ intrinsicbreakdownstartedfromabout13\\ MV/cm,andnovaluesaregivenfor{A}_{FN}and\\ B_{FN}\end{array}$ $\begin{array}{r}(computed:20C/c{\mathrm{m}}^{2}at0.05A/c{\mathrm{m}}^{2}lasts400\\ \mathrm{s},andif{Q}_{BD}stayedat20C/c{\mathrm{m}}^{2}atan\\ assumedusecurrentof1\times 10^{-9}A/c{\mathrm{m}}^{2}thetime\\ wouldbe2\times 10^{10}\mathrm{s},about630\mathrm{yr})\end{array}$
Weibull distribution of breakdown times with area and percentile scaling	$F(t)=1-e^{-(t/t_{63}{)}^{\beta }}$	$\frac{t_{BD1}}{t_{BD2}}={\left(\frac{A_2}{A_1}\right)}^{1/\beta }$ $\frac{t_F}{t_{63}}\approx {\left(\frac{F}{F_{63}}\right)}^{1/\beta }$	$\begin{array}{r}F(t):fractionofthecapacitorsthathave\\ failedbythetimet\end{array}$ $\begin{array}{r}{t}_{63}:characteristictimeatwhich63.2per\\ centhavefailed\end{array}$ $\beta :Weibullslope$ $A_{1}and{A}_2:oxideareasoftwocapacitors$ $\begin{array}{r}{t}_{BD1}and{t}_{BD2}:theirtimestobreakdownatthe\\ samefailurefraction\end{array}$ $t_F:timeatwhichthefractionFhasfailed$ $\begin{array}{r}{F}_{63}:0.632,Gurfinkeletal.:measured\\ slopesare3to10andforSiConlyhalf\\ thevalueforsilicon,thelifetime\\ projectionused\beta =3,andthepercentile\\ relationisgivenasanapproximation\end{array}$ $\begin{array}{r}(computed:for\beta =3acapacitorwith1000\\ timestheareabreaksdown10times\\ earlier,for\beta =6only3.2timesearlier\\ andfor\beta =10only2.0times;thetimeto\\ 1\mathrm{ppm}is1.2percentof{t}_{63}for\beta =3,\\ 10.8percentfor\beta =6and26percent\\ for\beta =10)\end{array}$

Hot Carriers and Bias Temperature Instability

Name	Formula	Related Formulae	Variables/Constants
Hot-carrier interface-trap growth and lifetime (lucky electron)	$\Delta N_{it}=C_2{\left[t\frac{I_D}{W}{e}^{-{\phi }_{it}/(q\lambda E_m)}\right]}^n$	$\tau =C_3\frac{W}{I_D}{\left(\frac{I_{sub}}{I_D}\right)}^{-m}$ $m=\frac{{\phi }_{it}}{{\phi }_i}$	$\begin{array}{r}\Delta N_{it}:increaseoftheinterface-trap\\ density\end{array}$ $C_{2}and{C}_3:fittingconstants$ $t:stresstime$ $I_D:draincurrent$ $W:channelwidth$ $\begin{array}{r}{\phi }_{it}:thresholdenergyforcreatingan\\ interfacetrap,3.7\mathrm{eV}intheoriginal\\ paper\end{array}$ $q:elementarycharge$ $\lambda :meanfreepathofthehotcarrier$ $\begin{array}{r}{E}_m:maximumlateralfieldinthechannel\\ (E_{m}axinthesource)\end{array}$ $n:timeexponent$ $\begin{array}{r}\tau :lifetimeuntil\Delta N_{it}reachesacritical\\ value\end{array}$ $I_{sub}:substratecurrent$ $\begin{array}{r}m:exponentoftheratioofsubstrate\\ currenttodraincurrent\end{array}$ $\begin{array}{r}{\phi }_i:thresholdenergyforimpactionisation\\ (E_{I}Tand{E}_{I}Iinthethesis),Triebl:Eq.6.1\\ to6.3ofthethesisarethe\\ lucky-electronmodelofHuetal.(1985)\\ andthesubstrate-currentform,only\\ fragmentsofthemcamethroughinthe\\ fetchsummary,sotheformsshownare\\ completedfrombackgroundknowledge,the\\ modelissimpleandoftenusedandfails\\ forhighlyscaleddevices,anditsworst\\ casecoincideswiththemaximumsubstrate\\ current\end{array}$ $\begin{array}{r}(computedwithanassumed{\phi }_i=1.3\mathrm{eV}\\ (backgroundknowledge):m=3.7/1.3=2.8,\\ soa10percentriseof{I}_{sub}/I_{D}shortensthe\\ lifeby24percent)\end{array}$
Empirical threshold-voltage shift from hot carriers	$\Delta V_{th}=C_{HCI}{\left(\frac{1}{L}\right)}^n(V_{GS}-V_{TH0}{)}^{1-n}{e}^{{\alpha }_1{E}_{ox}}{e}^{-{\alpha }_2/E_{lat}}{e}^{-E_a/(k_{B}T)}{t}^n$	$t_{life}={\left(\frac{\Delta V_{crit}}{X}\right)}^{1/n}$ $X=\frac{\Delta V_{th}}{t^n}$	$\Delta V_{th}:threshold-voltageshift,C_{HCI}$ ${\alpha }_{1}and{\alpha }_2:technology-dependentconstants$ $L:channellength$ $\begin{array}{r}{V}_{GS}and{V}_{TH0}:gate-sourcevoltageand\\ thresholdvoltageattimezero\end{array}$ $E_{ox}and{E}_{lat}:oxidefieldandlateralfield$ $E_a:activationenergy$ $k_B:Boltzmannconstant8.617\times 10^{-5}eV/K$ $T:absolutetemperature$ $t:stresstime$ $n:timeexponent$ $t_{life}:timeuntiltheshiftreaches\Delta V_{crit}$ $\Delta V_{crit}:shiftacceptedasfailure$ $\begin{array}{r}X:theshiftper{t}^{n}attheusecondition\\ (myconstruction),thearXivreview:the\\ modelisempiricalandbasedonthe\\ lucky-electronmodel,nistypically0.3\\ to0.7,hotcarriersmattermorewhenthe\\ gatevoltageexceedshalfofthedrain\\ voltage,andnovaluesaregivenforthe\\ constantsorfor{E}_a\end{array}$ $\begin{array}{r}(computedfromthestatedrange:forn=\\ 0.5a10percenterrorintheallowed\\ shiftbecomesa21percenterrorinthe\\ life,forn=0.3a37percenterror)\end{array}$
Bias temperature instability, power-law shift	$\Delta V_{th,DC}=B{V}_G^{\Gamma }{e}^{-E_a/(k_{B}T)}{t}^n$	$\Delta V_{th,AC}\approx \Delta V_{th,DC}{\alpha }^{0.35}$ $t_{life}={\left(\frac{\Delta V_{crit}}{B{V}_G^{\Gamma }{e}^{-E_a/(k_{B}T)}}\right)}^{1/n}$	$\begin{array}{r}\Delta V_{th,DC}and\Delta V_{th,AC}:threshold-voltageshift\\ afterDCandACstress\end{array}$ $B:process-dependentconstant$ $V_G:gatevoltage$ $\Gamma :voltageaccelerationexponent$ $E_a:activationenergy$ $k_B:Boltzmannconstant8.617\times 10^{-5}eV/K$ $T:absolutetemperature$ $t:stresstimeinseconds$ $n:timeexponent$ $\begin{array}{r}\alpha :dutycycle,0.5forACstressand1for\\ DCstress\end{array}$ $t_{life}:timeuntiltheshiftreaches\Delta V_{crit}$ $\begin{array}{r}\Delta V_{crit}:shiftacceptedasfailure(my\\ construction),thearXivreview:nis0.17\\ fromitsmeasurementdata,novaluesare\\ givenfor\Gamma or{E}_a,theACrelationis\\ garbledinthefetchsummary,which\\ repeats{t}^n,andiswrittenhereasIread\\ it(myreading),theshiftinthreshold\\ voltageisthemainparameterbecauseit\\ propagatestothecircuitdelay,forSRAM\\ thestaticnoisemarginisused\end{array}$ $\begin{array}{r}(computed:extrapolatingashiftmeasured\\ at1000\mathrm{s}to10\mathrm{yr}multipliesitby8.6\\ forn=0.17,6.7for0.15,2.4for0.07\\ and45for0.3;a10percentchangeof\\ thefailurecriterionchangesthelifeby\\ 1.75timesforn=0.17;ACstressata\\ dutycycleof0.5gives0.78oftheDC\\ shift)\end{array}$
Recovery of a bias temperature shift	$r(\xi )=\frac{1}{1+B_r{\xi }^{{\beta }_r}}$	$\xi =\frac{t_r}{t_s}$ $r_{RD}(\xi )=\frac{1}{1+{\xi }^{1/2}}$	$\begin{array}{r}r:fractionoftheshiftthatremains\\ aftertherelaxationtime{t}_r\end{array}$ $\begin{array}{r}\xi :ratiooftherelaxationtime{t}_{r}tothe\\ stresstime{t}_s\end{array}$ $B_{r}and{\beta }_r:fittedconstants$ $\begin{array}{r}{r}_{RD}:thesamefractionpredictedbythe\\ reaction-diffusionmodel,whichhas{B}_r=1\\ and{\beta }_r=1/2,Grasseretal.:B_{r}isabout\\ 0.3to3and{\beta }_{r}about0.15to0.2formost\\ data,afitofdataat125{}^{\circ }Cgives{B}_r=\\ 2.96and{\beta }_r=0.187,therelaxationdata\\ showtailsofmorethan12decadesintime\\ against3to4decadesforthestandard\\ reaction-diffusionmodel,andadelayed\\ measurementfollowsthestresslawdivided\\ by1+B(t_M/t{)}^{\beta }\end{array}$ $\begin{array}{r}(computed:withthefittedvalues25per\\ centoftheshiftremainswhenthe\\ relaxationtimeequalsthestresstime,\\ andonly55percentremainsafteradelay\\ ofonethousandthofthestresstime,so\\ 45percentislostbeforeaslow\\ measurementstarts,whereasthe\\ reaction-diffusionformleaves97per\\ cent)\end{array}$

Overstress Events and Latch-Up

Name	Formula	Related Formulae	Variables/Constants
Human-body model discharge	$I_{pk}\approx \frac{V_{HBM}}{R_{HBM}}$	$\tau =R_{HBM}{C}_{HBM}$ $E_{HBM}=\frac{1}{2}{C}_{HBM}{V}_{HBM}^2$	$\begin{array}{r}{I}_{pk}:peakcurrentoftheidealised\\ discharge\end{array}$ $V_{HBM}:chargevoltage$ $R_{HBM}:seriesresistance,1.5\mathrm{k\Omega }$ $C_{HBM}:capacitance,100\mathrm{pF}$ $\tau :timeconstantofthedischarge$ $\begin{array}{r}{E}_{HBM}:energystoredinthecapacitor,Texas\\ Instruments:thehuman-bodymodelisa100\\ \mathrm{pF}capacitordischargedthrougha1.5\mathrm{k\Omega }\\ resistortoeachpin,theratingis2000\mathrm{V}\\ underANSI/ESDA/JEDECJS-001,andJEDEC\\ documentJEP155statesthat500\mathrm{V}allows\\ safemanufacturingwithastandardESD\\ controlprocess,thepeakcurrentofan\\ idealRCdischargeignorestheresistance\\ ofthedeviceandtherealwaveformofthe\\ standardandismyconstruction\end{array}$ $\begin{array}{r}(computed:2000\mathrm{V}gives1.33\mathrm{A},150\mathrm{ns}and\\ 0.2\mathrm{mJ};500\mathrm{V}gives0.33\mathrm{A}and12.5\mu \mathrm{J})\end{array}$
Wunsch-Bell power to failure	$\frac{P_f}{A}=K_d{t}^{-1/2}$	$K_d=\sqrt{\pi \kappa \rho c}(T_m-T_0)$ $E_f=P_{f}t\propto t^{1/2}$	$P_f:powerthatcausesfailure$ $A:areaoftheheatedjunction$ $K_d:damageconstantofthematerial$ $t:pulsewidth$ $\kappa :thermalconductivity(Kinthereport)$ $\rho :density$ $c:specificheat$ $T_m:meltingtemperatureofsilicon$ $T_0:startingtemperature$ $\begin{array}{r}{E}_f:energythatcausesfailure(my\\ derivation),Orvisetal.:therelationis\\ usedforpulsesofabout0.1to20\mu \mathrm{s},\\ belowthatwithoutheatflowthethreshold\\ goesas1/t,WunschandBelluse{T}_m=1688\\ \mathrm{K}andDaviesandGentry948\mathrm{K},thereport\\ gives\kappa =1.57and0.33at300and994\mathrm{K}\\ andc=0.69and1.0kJ/(\mathrm{kg}\mathrm{K}),theunitof\\ \kappa camethroughaskW/(mK)inthefetch\\ summary,whichcannotberightfor\\ silicon,andIreadW/(cmK),thatis157\\ and33W/(\mathrm{m}\mathrm{K})(myreading),themeasured\\ slopeofthefailurepoweragainstpulse\\ widthis-0.47againstthetheoretical\\ -0.50,foraluminiummetallisationthe\\ failurecurrentgoesas{t}^{-1/2}below1\mu \mathrm{s},as\\ t^{-1/4}from1to100\mu \mathrm{s}andapproachesa\\ constantforlongpulses,andthe\\ equationsinthereportarereconstructed\\ fromagarbledscan\end{array}$ $\begin{array}{r}(computedwithassumedroundvaluesfor\\ silicon,\kappa =100W/(\mathrm{m}\mathrm{K})betweenthetwo\\ readings,\rho =2330kg/{\mathrm{m}}^3,c=700\\ J/(\mathrm{kg}\mathrm{K}),T_m=1688\mathrm{K}and{T}_0=300\mathrm{K}:K_d=\\ 3.1\times 10^7\mathrm{W}{\mathrm{s}}^{1/2}/{\mathrm{m}}^2,so{P}_f/A=3.1MW/c{\mathrm{m}}^{2}at1\mu \mathrm{s}\\ and9.9MW/c{\mathrm{m}}^{2}at0.1\mu \mathrm{s};ajunctionof10\mu \mathrm{m}\\ by10\mu \mathrm{m}thenfailsat3.1\mathrm{W},thatis3.1\\ \mu \mathrm{J},forapulseof1\mu \mathrm{s})\end{array}$
Latch-up condition and trigger	${\beta }_{npn}{\beta }_{pnp}>1$	$I_{inj}{R}_p\ge V_{BE,on}\approx 0.7\mathrm{V}$	$\begin{array}{r}{\beta }_{npn}and{\beta }_{pnp}:currentgainsofthetwo\\ parasiticbipolartransistorsthatform\\ thethyristor\end{array}$ $\begin{array}{r}{I}_{inj}:currentthatflowsthroughthewellor\\ substrateresistance\end{array}$ $R_p:thatresistance$ $\begin{array}{r}{V}_{BE,on}:turn-onvoltageofthebase-emitter\\ junction,TUGrazpage:latch-upis\\ possibleonlyiftheproductofthegains\\ isgreaterthanone,thetriggerisa\\ currentthroughtheresistanceofthewell\\ thatturnsonthenpntransistor,andonce\\ triggeredthelow-impedancepathstays\\ afterthetriggerisremovedandapower\\ cycleisusuallyneeded,Texas\\ Instruments:triggersareaninputor\\ outputvoltageabovethesupplyorbelow\\ ground,ESD,arapidriseofthesupply\\ voltage,asupplyvoltagehighenoughfor\\ transistorbreakdownandionising\\ radiation,thetransitfrequencyofthe\\ parasitictransistorsisonlyabout1\mathrm{MHz},\\ soovervoltagesofafewnanoseconds\\ usuallydonottriggerthethyristor,and\\ intheinjectiontestofthereport300to\\ 500\mathrm{mA}for10\mu \mathrm{s}at125{}^{\circ }Careusedfor\\ SN54/74logic,1to2\mathrm{A}aretypically\\ neededatroomtemperature,and100\mathrm{mA}in\\ theLinCMOSfinaltest\end{array}$ $\begin{array}{r}(computedwithanassumed{R}_p=500\Omega :a\\ triggercurrentof1.4\mathrm{mA}throughthewell\\ resistance,whereastheinjectiontestsof\\ thereportuse100\mathrm{mA}to2\mathrm{A}atthepin;I\\ readthedifferenceasmostofthe\\ injectedcurrentnotpassingthrough{R}_p(my\\ reading))\end{array}$

Avalanche and Short-Circuit Ruggedness

Name	Formula	Related Formulae	Variables/Constants
Single-pulse avalanche energy	$E_{AS}=\frac{1}{2}L{I}_{AS}^2\frac{V_{BR}}{V_{BR}-V_{DD}}$	$t_{AL}=\frac{L{I}_{AS}}{V_{BR}-V_{DD}}$ $V_{BR}\approx 1.3V_{(BR)DSS}$ $E_{AS}=\frac{1}{2}{P}_{AL,pk}{t}_{AL}$	$E_{AS}:energyofthesingleavalanchepulse$ $L:loadinductance$ $I_{AS}:peakavalanchecurrent$ $V_{BR}:voltageduringtheavalanche$ $V_{DD}:supplyvoltage$ $t_{AL}:durationoftheavalanche$ $\begin{array}{r}{V}_{(BR)DSS}:ratedbreakdownvoltageofthe\\ drain-sourcejunction\end{array}$ $\begin{array}{r}{P}_{AL,pk}:peakpowerintheavalanche,Nexperia:\\ thevoltageduringtheavalancheistaken\\ as1.3timestheratedvalue,theenergy\\ formisreconstructedinthesource\\ summaryfromitsgarbledEq.4,the\\ single-shotfailureisattributedtothe\\ junctiontemperatureexceedingits\\ maximum,catastrophicfailureoccursat\\ roughly380{}^{\circ }C,thesafecurveassumesa\\ startat25{}^{\circ }Candamaximumof175{}^{\circ }C,\\ andthe175{}^{\circ }Cisderatedfromthereal\\ maximumforreliability\end{array}$ $\begin{array}{r}(computedfromtheexampleofthesource:\\ L=30\mu \mathrm{H},I_{AS}=18\mathrm{A},V_{(BR)DSS}=60\mathrm{V}and{V}_{DD}=0\\ give{V}_{BR}=78\mathrm{V},E_{AS}=4.9\mathrm{mJ}and{t}_{AL}=6.9\mu \mathrm{s},\\ andthesourcesaysabout7\mu \mathrm{s})\end{array}$
Repetitive avalanche heating	$P_{AR}=E_{AS}f$	$\Delta T_j=P_{AR}{R}_{th(j-a)}$ $T_{j(AV)}=T_{j(init)}+\Delta T_j$	$\begin{array}{r}{P}_{AR}:averagepoweroftherepeated\\ avalanche\end{array}$ $E_{AS}:energyofonepulse$ $f:repetitionfrequency$ $\begin{array}{r}\Delta T_j:averageriseofthejunction\\ temperature\end{array}$ $\begin{array}{r}{R}_{th(j-a)}:thermalresistancefromjunctionto\\ ambient\end{array}$ $T_{j(AV)}:averagejunctiontemperature$ $\begin{array}{r}{T}_{j(init)}:startingtemperature,the\\ mounting-basetemperatureplustherise\\ fromtheon-state(T_{m}band\Delta T_{o}ninthe\\ source),Nexperia:theriseofeachevent\\ islimitedto30\mathrm{K}fortherepetitive\\ curve,threeconditionsmusthold,the\\ currentiswithintherepetitivesafe\\ area,thejunctiontemperaturestaysbelow\\ 175{}^{\circ }Candthenumberofeventsiswithin\\ thecyclelimit,andthesourcesaysthat\\ morethanonewear-outmechanismactsand\\ thattemperatureisnottheonlylimit\end{array}$ $\begin{array}{r}(computedfromtherepetitiveexampleof\\ thesource,L=30\mu \mathrm{H},10\mathrm{A},3\mathrm{kHz},5K/W:\\ E_{AS}=1.56\mathrm{mJ}(whichneeds{V}_{DD}ofabout3\mathrm{V}),\\ P_{AR}=4.68\mathrm{W}and\Delta T_j=23.4\mathrm{K};thesource\\ prints123.4and153,whichIreadas100\\ +23.4and123.4+30,seethequestionon\\ thisexample)\end{array}$
Short-circuit energy	$E_{SC}={\int }_{t_0}^{t_1}{v}_{DS}{i}_{D}dt$	$V_{DS}=V_{bus}-L_{par}\frac{d{i}_D}{dt}$ $E_{SC}\approx V_{bus}{\bar{I}}_D{t}_{SC}$	$\begin{array}{r}{E}_{SC}:energydissipatedinthetransistor\\ duringtheshortcircuit\end{array}$ $\begin{array}{r}{t}_{0}and{t}_1:instantsatwhichthegate\\ voltagepasses50percentatturn-onand\\ atturn-off\end{array}$ $\begin{array}{r}{v}_{DS}and{i}_D:drain-sourcevoltageanddrain\\ current\end{array}$ $V_{bus}:busvoltage$ $L_{par}:parasiticinductanceoftheloop$ ${\bar{I}}_D:meandraincurrent(myconstruction)$ $\begin{array}{r}{t}_{SC}:durationoftheshortcircuit,\\ Wolfspeed:thelastpasspulseisthelast\\ pulsethattheMOSFETcouldturnoff\\ safelywithoutlossoffunction,the\\ exampleisa1200\mathrm{V}moduleat800\mathrm{V},175\\ {}^{\circ }C,15\mathrm{V}gatedriveand4\Omega externalgate\\ resistance,withalastpasspulseof2.9\\ \mu \mathrm{s}andasaturationcurrentofabout1050\\ \mathrm{A},thecriticalenergyisaround1.4\mathrm{J}on\\ averageandstaysconstantwiththebus\\ voltagewhilethewithstandtimefallsas\\ thebusvoltagerises,andadesaturation\\ turn-offstopstheeventbefore0.2\mathrm{J}\\ afterslightlymorethan300\mathrm{ns}\end{array}$ $\begin{array}{r}(computed,ifthe1.4\mathrm{J}belongstothe2.9\\ \mu \mathrm{s}case:themeancurrentis603\mathrm{A},which\\ is57percentof1050\mathrm{A};ataconstant\\ energyandmeancurrentthewithstandtime\\ wouldbe5.8\mu \mathrm{s}at400\mathrm{V}and3.9\mu \mathrm{s}at600\\ \mathrm{V};800\mathrm{V}times1050\mathrm{A}times0.3\mu \mathrm{s}is0.25\\ \mathrm{J},anupperboundforthedesaturation\\ case)\end{array}$

Important Questions

Ques: Which voltage-acceleration model should be used to extrapolate gate-oxide life: E, 1/E or power law?

The sources disagree on where each belongs. The arXiv review assigns the E model to thick SiO${}_2$, the 1/E model to high-k dielectrics and the voltage power law to ultrathin ones, whereas Verweij and Klootwijk tie the E form to intrinsic breakdown and the 1/E form to extrinsic breakdown at weak spots. Padovani et al. call the E model too conservative and the 1/E model overly relaxed, and find the E dependence at 3.6 $\mathrm{V}$ and above and a power law below. With an assumed G of 320 $MV/cm$, lowering the field from 10 to 8 $MV/cm$ gives 2981 times more life for 1/E against 9897 times for E, and from 8.5 to 6 $MV/cm$ it gives $6.5\times 10^6$ against $9.9\times 10^4$ times (computed). The truth at use fields most likely lies between the two (my reading), so E is the safe bound and 1/E the optimistic one. Reference: arXiv:2503.21165, ‘Extending Silicon Lifetime: A Review of Design Techniques for Reliable Integrated Circuits’ (authors and date not read) (fetch-tool summary; it gives equations for BTI and HCI and only names the TDDB models); Verweij and Klootwijk, ‘Dielectric breakdown I: A review of oxide breakdown’, Microelectronics Journal 27 (1996) 611-622 (fetch-tool summary; equations garbled); Padovani, La Torraca, Strand, Shluger, Milo and Larcher, ‘Towards a Universal Model of Dielectric Breakdown’ (file name says IRPS 2023, venue not stated in the text) (fetch-tool summary; Eq. 1 not legible).

Ques: Is the field acceleration factor of the E model one number?

No. Gurfinkel et al. find for 4H-SiC capacitors a $\gamma$ of about 4.6 $cm/MV$ above 8.5 $MV/cm$ and 2.07 to 3.22 $cm/MV$ at lower fields, with $P_{eff}=k_{B}T\gamma$ of 11.3 to 14.0 $\mathrm{e}\mathring{\mathrm{A}}$ and an activation energy of about 1 $\mathrm{eV}$, 1.1 $\mathrm{eV}$ at 7.0 $MV/cm$. For 4.6 at 300 $\mathrm{K}$ I get 11.9 $\mathrm{e}\mathring{\mathrm{A}}$, inside that range (computed). A step from 8.5 to 6 $MV/cm$ then gives $9.9\times 10^4$ times more life with 4.6, 3100 with 3.22 and 177 with 2.07 (computed). The low-field values are more likely to apply near use, because they come from data nearer to it, so the high-field value overstates the life (my reading). The source also prints the temperature factor as $\exp (-E_a/(k_{B}T))$, which would make life grow with temperature; I take that as a sign slip (my reading). Reference: Gurfinkel, Horst, Suehle, Bernstein, Shapira, Matocha, Dunne and Beaupre, ‘Time-Dependent Dielectric Breakdown of 4H-SiC/SiO${}_2$ MOS Capacitors’, IEEE Transactions on Device and Materials Reliability, vol. 8, no. 4, December 2008 (fetch-tool summary; equations transcribed from the PDF text).

Ques: How much does the Weibull slope change the projected life of a large oxide area?

Gurfinkel et al. measured slopes of 3 to 10, for SiC only half the value for silicon, and projected lifetimes with a slope of 3. With the scaling in the table, 1000 times more area shortens the time to a given failure fraction by 10 times for a slope of 3, by 3.2 times for 6 and by 2.0 times for 10, and the time to reach 1 $\mathrm{ppm}$ is 1.2, 10.8 and 26 per cent of the time to 63.2 per cent failed (computed). A low slope is thus the cautious choice for a large area and a small failure budget. For SiC the measured value near 3 is the more likely one to use, and 10 is the upper end of the range that they measured. Reference: Gurfinkel, Horst, Suehle, Bernstein, Shapira, Matocha, Dunne and Beaupre, ‘Time-Dependent Dielectric Breakdown of 4H-SiC/SiO${}_2$ MOS Capacitors’, IEEE Transactions on Device and Materials Reliability, vol. 8, no. 4, December 2008 (fetch-tool summary; equations transcribed from the PDF text).

Ques: Which time exponent should be used for bias temperature instability?

The arXiv review states a time exponent of 0.17 from measurement data. Grasser et al. report that some groups find a temperature-independent value of about 0.15, that delayed measurements give 0.2 to 0.3 rising linearly with temperature, and that delay-free measurements give 0.07 to 0.2. Extrapolating a shift from 1000 $\mathrm{s}$ to 10 $\mathrm{yr}$ multiplies it by 8.6 for 0.17, 6.7 for 0.15, 2.4 for 0.07, 12.6 for 0.2 and 45 for 0.3, and a 10 per cent change in the failure criterion changes the life by 1.75 times for 0.17 (computed). The delay-free values are more likely correct, because a delay lets part of the shift recover and changes the slope (my reading from the recovery model of the same source), so 0.07 to 0.2 should be used and 0.17 lies in its upper part. Reference: arXiv:2503.21165, ‘Extending Silicon Lifetime: A Review of Design Techniques for Reliable Integrated Circuits’ (authors and date not read) (fetch-tool summary; it gives equations for BTI and HCI and only names the TDDB models); Grasser, Goes and Kaczer, ‘Toward Engineering Modeling of Negative Bias Temperature Instability’, chapter 14 of an edited volume (Taylor and Francis, 2008), file BC2009_Grasser_1.pdf on the TU Wien IUE site (fetch-tool summary; the excerpt is truncated).

Ques: How fast does a bias temperature shift recover, and which recovery model is right?

Grasser et al. describe the remaining fraction by $1/(1+B{\xi }^{\beta })$ with $B$ about 0.3 to 3 and $\beta$ about 0.15 to 0.2, and a fit of data at 125 ${}^{\circ }\mathrm{C}$ gives $B$ = 2.96 and $\beta$ = 0.187. The reaction-diffusion model predicts $B$ = 1 and $\beta$ = 1/2. At a delay of one thousandth of the stress time the fit leaves 55 per cent of the shift, so 45 per cent is lost before the measurement, while the reaction-diffusion form leaves 97 per cent (computed). The paper states that the reaction-diffusion model does not match the measurements, which show tails of more than 12 decades against 3 to 4 for it, so the fitted values are more likely. It also concludes that no reviewed model fits stress and relaxation with the same parameters, so the fit is empirical. Reference: Grasser, Goes and Kaczer, ‘Toward Engineering Modeling of Negative Bias Temperature Instability’, chapter 14 of an edited volume (Taylor and Francis, 2008), file BC2009_Grasser_1.pdf on the TU Wien IUE site (fetch-tool summary; the excerpt is truncated).

Ques: At which bias is hot-carrier damage worst, and what time exponent does it follow?

Triebl’s thesis says that the worst case coincides with the maximum substrate current. The arXiv review says that hot carriers become more significant when the gate voltage exceeds half of the drain voltage. For a long-channel n-channel device the substrate current peaks near a gate voltage of half the drain voltage (background knowledge), so the two statements describe different things, the worst point of a stress sweep and the region where hot carriers matter. For choosing the stress bias the thesis is more likely right (my reading). The exponent also differs: the review gives 0.3 to 0.7 for the threshold shift and the thesis derives $t^{0.5}$ for one mode, which lies inside that range. For 0.5 a 10 per cent error in the allowed shift is a 21 per cent error in life, and for 0.3 it is 37 per cent (computed). Reference: O. Triebl, ‘Reliability Issues in High-Voltage Semiconductor Devices’, thesis, TU Wien, chapter 6.2 ‘Review of Modeling Approaches’ (year not stated) (fetch-tool summary; the equations are images and only fragments came through); arXiv:2503.21165, ‘Extending Silicon Lifetime: A Review of Design Techniques for Reliable Integrated Circuits’ (authors and date not read) (fetch-tool summary; it gives equations for BTI and HCI and only names the TDDB models).

Ques: Does a high ESD rating protect against electrical overstress?

No. Welsher states that ESD protection gives no predictable protection against EOS root causes other than ESD, and that over-voltage, over-current and over-power causes are more prevalent than ESD by a wide margin. Industry Council White Paper 4 reports a survey with more than 20 per cent of total failures being EOS-related and, in another statement, 30 per cent of total electrical failures. The two have different bases, total failures against electrical failures, so I do not read them as a conflict (my reading). The model itself is small: 100 $\mathrm{pF}$ through 1.5 $\mathrm{k\Omega }$ gives 1.33 $\mathrm{A}$ and 0.2 $\mathrm{mJ}$ at 2000 $\mathrm{V}$ and 0.33 $\mathrm{A}$ and 12.5 $\mu \mathrm{J}$ at 500 $\mathrm{V}$ (computed), and a supply fault can deliver far more energy (background knowledge). JEP155 states that 500 $\mathrm{V}$ allows safe manufacturing with a standard ESD control process. Reference: Welsher, ‘Rethinking Electrical Overstress’, Dangelmayer Associates (date not stated, about 2015 to 2016) (fetch-tool summary); Industry Council on ESD Target Levels, White Paper 4 ‘Understanding Electrical Overstress - EOS’, August 2016, revision 1.2 (fetch-tool summary); Texas Instruments LM21212-1 datasheet, ESD ratings table (fetch-tool summary).

Ques: Which melting temperature and slope should be used in the Wunsch-Bell relation?

Orvis et al. quote a melting temperature of 1688 $\mathrm{K}$ for Wunsch and Bell and 948 $\mathrm{K}$ for Davies and Gentry, which differ by a factor of 0.47 in the damage constant (computed). The measured slope of the failure power against pulse width is $-0.47$ (Alexander et al.) against the theoretical $-0.50$, with an average of $-0.56$ over combinations. Over two decades of pulse width these slopes change the failure power by 8.7, 10 and 13 times (computed). The melting point of silicon is the more likely limit for a junction, but where aluminium contacts alloy with silicon below that temperature the lower value can apply (my reading, background knowledge), so the relation should be used as an order-of-magnitude guide within its stated range of about 0.1 to 20 $\mu \mathrm{s}$. The report’s own scan is garbled, so I did not use its constants for aluminium. Reference: Orvis, Khanaka and Yee, ‘A Review of the Physics and Response Models for Burnout of Semiconductor Devices’, Lawrence Livermore National Laboratory report UCRL-53573, December 1984 (DTIC ADA155031) (fetch-tool summary; the scan is garbled and the equations were reconstructed there).

Ques: What triggers latch-up: a fraction of a milliampere or amperes?

The TU Graz page gives the trigger as a current through the well or substrate resistance that produces more than 0.7 $\mathrm{V}$, and a gain product above one; with an assumed 500 $\Omega$ this is 1.4 $\mathrm{mA}$ (computed). Haseloff’s report gives injection currents of 300 to 500 $\mathrm{mA}$ for 10 $\mu \mathrm{s}$ at 125 ${}^{\circ }\mathrm{C}$ for SN54/74 logic, 1 to 2 $\mathrm{A}$ typically at room temperature, and 100 $\mathrm{mA}$ in the LinCMOS final test. These are not the same quantity: 0.7 $\mathrm{V}$ is the local turn-on condition, whereas the test currents are injected at a pin and only part of that current reaches the well resistance (my reading). The temperature trend shows that the trigger current falls as the part gets hot. The report adds that overvoltages of a few nanoseconds usually do not trigger, because the transit frequency of the parasitic transistors is only about 1 $\mathrm{MHz}$. Reference: ‘Latch Up’ lecture page on power semiconductor devices, TU Graz, by Michael Pinter, 12 July 2016 (fetch-tool summary; one sentence on spacing is unclear there); Haseloff, ‘Latch-Up, ESD, and Other Phenomena’, Texas Instruments application report SLYA014A, May 2000 (fetch-tool summary).

Ques: Is the short-circuit failure of SiC MOSFETs mainly gate-oxide failure or thermal runaway?

The sources disagree. Wolfspeed names thermal runaway as the most common cause, with gate-oxide failure mainly at a bus voltage that is low relative to the rating. Ceccarelli et al. count gate-oxide breakdown in 62 per cent of 40 failures, about 25, and thermal runaway in 38 per cent, with the gate-oxide failures mostly in tests above 50 per cent of the rated voltage. The withstand values differ too: Wolfspeed gives 2.9 $\mu \mathrm{s}$ and about 1.4 $\mathrm{J}$ on average at 800 $\mathrm{V}$ and 175 ${}^{\circ }\mathrm{C}$, whereas Ceccarelli et al. list modules at 800 $\mathrm{V}$ with 5.0 to 6.2 $\mu \mathrm{s}$ and 4.29 to 7.29 $\mathrm{J}$. The survey covers several makers, so its split is more likely to describe the population, and the note describes one maker’s devices (my reading). Wolfspeed argues for comparing the energy, since it stays constant while the time falls with bus voltage. Reference: Wolfspeed, ‘SiC MOSFET Short Circuit Application Note’, PRD-08296 (uploaded January 2024) (fetch-tool summary); Ceccarelli, Reigosa, Iannuzzo and Blaabjerg, ‘A survey of SiC power MOSFETs short-circuit robustness and failure mode analysis’, Microelectronics Reliability 76-77 (2017) 272-276 (fetch-tool summary).

Ques: Do the numbers of the Nexperia repetitive-avalanche example add up?

In the repetitive example (30 $\mu \mathrm{H}$, 10 $\mathrm{A}$, 3 $\mathrm{kHz}$, 5 $K/W$) the note gives 1.56 $\mathrm{mJ}$ per event and 4.68 $\mathrm{W}$, which I reproduce for a supply of about 3 $\mathrm{V}$ (computed), but it prints a temperature rise of 123.4 and an average junction temperature of 153. With 5 $K/W$ the rise is 23.4 $\mathrm{K}$ (computed), so 123.4 can only be the 100 ${}^{\circ }\mathrm{C}$ of the mounting base plus 23.4 $\mathrm{K}$, and 153 is that value plus the 30 $\mathrm{K}$ allowed per event, 153.4 (my reading). That reading is more likely than an error in the power because the first two numbers agree. It also means that the 153 is a bound on the peak and not an average, although the note calls it the average. Reference: Nexperia, ‘Power MOSFET single-shot and repetitive avalanche ruggedness rating’, application note AN10273, revision 5.0, 20 June 2022 (fetch-tool summary; Eq. 4 was garbled and reconstructed there).

Related pages in this vault: Thermal Stress, Mechanical and Package Stress, Radiation, Failure Rate and the Bathtub Curve, Metal and Interconnect, Silicon Power MOSFET, IGBT and Thyristors, On-Chip ESD Protection Devices, Weibull Distribution, Emission Microscope, OBIRCH and Lock-In Thermography.