1. Theory
- Definition: Joule heating is the temperature rise of an interconnect line from its own dissipation, which must flow out through the surrounding dielectric to the substrate; the line temperature then sets its resistance and its electromigration lifetime (Banerjee and Mehrotra).
- Thermal resistance: The rise is , with set by the dielectric thickness and thermal conductivity under the line and by lateral spreading (Banerjee and Mehrotra).
- Low-k penalty: Porous low-k dielectrics conduct heat poorly, 0.1 to 0.7 against about 1.4 for SiO2, so the same current heats lines several times more (Alam et al.; background knowledge for SiO2).
- Current-density limits: The rms current density sets the heating and the average density the electromigration, and the two must be solved together because electromigration accelerates with the heated metal temperature (Banerjee and Mehrotra).
- Upper layers: Global lines sit on the thickest dielectric stack, far from the substrate, so they heat the most (Banerjee and Mehrotra).
2. Working Principle
- Heat path: Heat generated in the line flows down through the dielectric to the silicon and package, spreading laterally by about 0.88 times the dielectric thickness on each line, and along the line toward vias over a characteristic length of micrometres to tens of micrometres (Banerjee and Mehrotra).
- Positive feedback: Resistivity rises with temperature, so a hotter line dissipates more, which the self-consistent analysis includes (Banerjee and Mehrotra).
- Duty cycle: Signal lines carry pulses, so their rms density is times the peak while their average density is times the peak; at low duty cycle, heating rather than electromigration limits the peak current (Banerjee and Mehrotra).
- Short pulses: Under ESD-like pulses there is no time for heat to escape, so the line heats adiabatically into its own and the nearby dielectric’s heat capacity until it melts and opens (Banerjee and Mehrotra).
3. Applications
- Electromigration and self-heating sign-off: Setting rms, average and peak current-density limits for signal, clock and power lines (Banerjee and Mehrotra; Metal and Interconnect page).
- Via sizing: Minimum via areas and redundant vias for high-current nets (Banerjee and Mehrotra).
- Dielectric selection: Weighing the capacitance benefit of porous low-k films against their poorer heat conduction (Alam et al.; Wire Capacitance page).
- ESD and fuse design: Line widths that survive ESD pulses, and conversely deliberate heating in electrical fuses (Banerjee and Mehrotra; On-Chip ESD Protection Devices page).
Self-Heating
| Name | Formula | Related Formulae | Variables/Constants |
|---|---|---|---|
| Self-heating temperature rise of a line | |||
| Thermal characteristic length | |||
| Temperature dependence of resistance |
Current-Density Limits
| Name | Formula | Related Formulae | Variables/Constants |
|---|---|---|---|
| Peak, average and rms current density | |||
| Self-consistent current-density limits |
Dielectrics, Vias and Pulses
| Name | Formula | Related Formulae | Variables/Constants |
|---|---|---|---|
| Thermal conductivity of low-k dielectrics | |||
| Via current limits and high-current failure |
Important Questions
Ques: How much does a current-carrying line heat itself?
Using Banerjee and Mehrotra’s quasi-2D model, with and an effective width of , an assumed 1 wide, 1 thick, 1 long Cu line on 1 of dielectric of 0.2 has of about 2660 (computed). Carrying 2 rms, 20 through 22 , it dissipates 8.8 and heats by about 23 above the chip, which is itself typically at 100 to 120 (computed). On SiO2 of an assumed 1.4 the same line would heat only 3.3 . This is why rms current limits fell as low-k dielectrics were introduced. Reference: K. Banerjee and A. Mehrotra, ‘Global (Interconnect) Warming’, IEEE Circuits and Devices Magazine (September 2001) (UCSB course copy; several equations reconstructed from a garbled extract) (fetch-tool summary).
Ques: Is the thermal conductivity of porous low-k films about 0.1 or about 0.2 W/(m K)?
It depends on porosity, and the sources compare different things. Banerjee and Mehrotra used roadmap projections of 1.05, 0.54, 0.19, 0.12 and 0.07 for dielectrics of permittivity 3.75 down to 1.25 at the 180 to 50 nodes. Alam et al. measured real SiOC:H and SiC:H films: 0.7 when dense and as low as 0.1 at 30 per cent porosity, a nonlinear fall. Production ultra-low-k films stopped at a permittivity of about 2.4 to 2.5, well above the projected 1.25 to 1.9 (Wire Capacitance page), so their conductivity lies between the measured dense and porous values. A value of about 0.1 to 0.3 is therefore the more likely range for porous production films, and the projected 0.07 was never reached (my reading). Reference: K. Banerjee and A. Mehrotra, ‘Global (Interconnect) Warming’, IEEE Circuits and Devices Magazine (September 2001) (UCSB course copy; several equations reconstructed from a garbled extract) (fetch-tool summary); M. T. Alam, R. A. Pulavarthy, J. Bielefeld, S. W. King and M. A. Haque, ‘Thermal conductivity measurement of low-k dielectric films: Effect of porosity and density’, Journal of Electronic Materials 43(3), 746-754 (2014), doi:10.1007/s11664-013-2949-5 (abstract only); Wire Capacitance and Low-k Dielectrics page of this vault.
Ques: Why do both rms and average current densities have to be limited?
Because they control different failures. The average density drives electromigration through Black’s equation, with about 2 and about 0.5 for narrow Cu, while the rms density sets the Joule heating that raises . For unipolar pulses of duty cycle , and , so at the rms value is 1.83 times the average (computed). At low duty cycle the heating limit dominates: Banerjee and Mehrotra find that at the self-consistent peak density is only about half the electromigration-only value. Bipolar signal lines, whose electromigration damage partly recovers, allow about 3 times the unipolar rms density at . Reference: K. Banerjee and A. Mehrotra, ‘Global (Interconnect) Warming’, IEEE Circuits and Devices Magazine (September 2001) (UCSB course copy; several equations reconstructed from a garbled extract) (fetch-tool summary); Metal and Interconnect page of this vault (Reliability and Degradation, Stress Types).
Ques: How do size effects change the allowed current density in narrow lines?
They lower it, because a more resistive line dissipates more for the same current. Banerjee and Mehrotra estimate resistivity ratios rising from 1.07 at the 180 node to 1.28 at 50 from thin-film scattering and barriers, with the temperature coefficient falling to 0.83 of bulk. Including these effects, the allowed rms density for optimally buffered global Cu lines at 120 falls from 0.46 to 0.40 at 50 , 13 per cent lower (computed). They also show that the dielectric alone would lower the limit 2.25 times from 180 to 50 for an unscaled top metal, but only 16.8 per cent with roadmap-scaled geometry, since thinner dielectrics shorten the heat path. Present-day size effects are much larger, as the Wire Resistance page shows, so the penalty is now greater (my reading). Reference: K. Banerjee and A. Mehrotra, ‘Global (Interconnect) Warming’, IEEE Circuits and Devices Magazine (September 2001) (UCSB course copy; several equations reconstructed from a garbled extract) (fetch-tool summary); Wire Resistance and Size Effects page of this vault.
Ques: How large must vias be to carry the current of a global line?
Vias are short and lose heat into the lines they join, so they tolerate higher densities, but their small area concentrates the current. Banerjee and Mehrotra give maximum via rms densities falling from 4.18 to 3.50 from the 180 to the 50 node, with minimum via areas from about 0.092 to 0.0063 . For optimally buffered global lines, the vias at the local tier must be at least about 3 times the minimum via size at that tier, which in practice means several vias in parallel. Because each via adds resistance and occupies routing tracks on the layers it passes, this current-carrying requirement competes with wiring density, which is why high-current nets are given via arrays (background knowledge). The same reasoning applies to the power grid, where vias carry the largest steady currents. Reference: K. Banerjee and A. Mehrotra, ‘Global (Interconnect) Warming’, IEEE Circuits and Devices Magazine (September 2001) (UCSB course copy; several equations reconstructed from a garbled extract) (fetch-tool summary).
Ques: What happens to an interconnect line during a high-current ESD pulse?
The pulse is too short for heat to escape, so the line heats almost adiabatically. Banerjee and Mehrotra write the rise as , where the pulse energy is about and the thermal capacity includes a dielectric sheath whose share grows as the square root of time. AlCu lines fail open at about 60 with a critical rise of about 1000 , and Cu, which melts at about 1100 against about 660 for AlCu, carries a higher critical current. The critical current scales with the square root of the thermal capacity times the critical temperature rise, divided by the resistance, so wider and thicker lines survive larger pulses. Lines in ESD current paths are therefore sized for pulse current rather than for normal operation. Reference: K. Banerjee and A. Mehrotra, ‘Global (Interconnect) Warming’, IEEE Circuits and Devices Magazine (September 2001) (UCSB course copy; several equations reconstructed from a garbled extract) (fetch-tool summary); On-Chip ESD Protection Devices page of this vault.
Related pages in this vault: Scanning Thermal Microscope (SThM), Metal and Interconnect, Wire Capacitance and Low-k Dielectrics, Wire Resistance and Size Effects, Power Delivery Networks, Contacts and Vias, RC Delay and Repeater Insertion, On-Chip ESD Protection Devices, Electrical Stress.