Magnetoresistive Random Access Memory (Toggle and STT-MRAM)

This page covers the degradation of magnetoresistive random access memory: field-switched toggle MRAM and spin-transfer-torque MRAM (STT-MRAM) with perpendicular magnetic tunnel junctions (pMTJ) and an MgO tunnel barrier. It covers thermally activated loss of the stored state, the temperature limits including solder reflow, read disturb and write errors, breakdown of the tunnel barrier, and immunity to external magnetic fields. The device physics is on the MRAM device pages, the dielectric breakdown statistics on the CMOS Logic Transistors page and the lifetime statistics on the Failure Rate page; spin-orbit-torque MRAM is still in development and is not covered.

1. Why It Happens

• Trigger: Temperature, which lowers the energy barrier of the free layer relative to $k_{B}T$ (Wang et al.; Avalanche); solder reflow at about 260 ${}^{\circ }\mathrm{C}$ (Wang et al.); the current through the junction during writes and reads in STT-MRAM (Avalanche; Wang et al.); external magnetic fields (Everspin; Avalanche).
• Mechanism, retention: The free layer reverses by thermal activation over its barrier with a rate set by the stability factor $\Delta$; the weakest bits of the distribution set the chip retention (Wang et al.; background knowledge for the Neel-Brown form).
• Mechanism, read disturb and write errors: The read current lowers the barrier and can switch a bit, and a write pulse can fail to switch it, both with a probability that depends exponentially on $\Delta$ and on the current (background knowledge; Avalanche).
• Mechanism, barrier breakdown: Each STT write passes current through the thin MgO barrier, which wears out by time-dependent dielectric breakdown, hard or soft (Avalanche; Wang et al.; Di Carlo et al.). Toggle MRAM writes with field lines and has unlimited endurance (Everspin).
• What sets the rate: $\Delta$ and its spread, set by the anisotropy and the free-layer volume (Wang et al.); the temperature through the anisotropy (Avalanche); the write voltage across the barrier (Avalanche; Wang et al.); the field compared with the coercivity (Wang et al.).
• Failure criterion: A bit-flip probability above the target, such as 1 ppm in 10 years (Wang et al.); a barrier breakdown at a defined failed-bit fraction (Wang et al.); a raw error rate beyond sub-ppm in a field test (Avalanche).

2. Where to Look

• Location: The free layer and the MgO barrier of the MTJ (Wang et al.); the smallest or weakest bits of the array, which have the lowest barrier (Wang et al.).
• Signature: Retention errors that rise steeply with temperature (Avalanche); a sudden short of the junction (hard breakdown) or a gradual resistance change (soft breakdown) (Di Carlo et al.); errors after exposure to a magnet (Everspin; Avalanche).
• Confirm with: Retention bakes at several temperatures with extrapolation of ${\Delta }_{eff}$ (Wang et al.); voltage-ramp TDDB at several ramp rates with Weibull analysis, and chip-level cycling (Wang et al.); write-error-rate tests against pulse width and voltage (Wang et al.; Avalanche); field exposure in operation and standby (Avalanche).
• Look-alikes: Write errors from a too-low write voltage, which look like retention loss but appear immediately (Avalanche); field-induced errors, which depend on the magnet rather than on time (Avalanche).

3. Prevention

• Design: Choose ${\Delta }_{eff}$ for the retention target at the highest temperature, about 54 for 1 ppm in 10 years (Wang et al.); set the write voltage well above the mean switching voltage while keeping it low enough for the barrier (Avalanche); use ECC against the probabilistic errors (Di Carlo et al.).
• Material and process: A free layer with high anisotropy and a narrow barrier distribution; a stack that survives the 400 ${}^{\circ }\mathrm{C}$ back-end anneal and 260 ${}^{\circ }\mathrm{C}$ reflow (Wang et al.); a robust pinned layer against back-hopping (Wang et al.).
• Operation: Keep read currents well below the critical current (background knowledge); keep external fields below the rated maximum, about 151 $\mathrm{Oe}$ for the toggle MRAM (Everspin, computed) and 700 $\mathrm{Oe}$ in operation for the pMTJ part (Avalanche); stay within the rated temperature grade (Everspin).
• Screening and test: Chip-level retention and endurance tests on many chips projected to ppm levels (Wang et al.); field-immunity tests in operation and standby (Avalanche).

Retention and Thermal Stability

Name	Formula	Related Formulae	Variables/Constants
Thermally activated loss of the stored state	$P_{flip}(t)=1-\exp \left[-\frac{t}{{\tau }_0}{e}^{-\Delta }\right],\Delta =\frac{E_B}{k_{B}T}\approx \frac{K_{u}V}{k_{B}T}$	${\Delta }_{req}=\ln \frac{t}{{\tau }_0{P}_{flip}}(P_{flip}\ll 1)$	$\begin{array}{r}{P}_{flip}:probabilitythatabithasreversed\\ aftertimet\end{array}$ $\begin{array}{r}{\tau }_0:attempttime(about1\mathrm{ns},background\\ knowledge)\end{array}$ $\Delta :thermalstabilityfactor$ $E_B:energybarrierofthefreelayer$ $k_B:Boltzmannconstant(8.617\times 10^{-5}\mathrm{eV}/K)$ $T:absolutetemperature$ $K_u:effectiveanisotropyenergydensity$ $V:free-layervolume$ $\begin{array}{r}{\Delta }_{req}:stabilityneededforatarget{P}_{flip}\\ (Neel-Brownform,backgroundknowledge);\\ Wangetal.:\Delta =54gives1ppmfailure\\ after10years,\Delta =80correspondsto\\ 1\times 10^{12}yearsand\Delta =100to1\times 10^{20}years,and\\ E_{B}scalesroughlyasthesizetothepower\\ 0.67\end{array}$ $\begin{array}{r}(computedwith{\tau }_0=1\mathrm{ns}:{\Delta }_{req}=54.1for1\\ ppmand61.0for1ppbin10years;\Delta =80\\ and100reach1ppmafter1.8\times 10^{12}and\\ 8.5\times 10^{20}years,matchingWangetal.;\\ halvingthesizelowers{E}_{B}to63percent)\end{array}$
Chip-level stability and its temperature dependence	${\Delta }_{eff}={\Delta }_m-\frac{{\sigma }_{\Delta }^2}{2}$	$\Delta (T)=\frac{E_B(T)}{k_{B}T},\frac{\Delta (T_1)}{\Delta (T_2)}=\frac{T_2}{T_1}(E_B\text{constant})$	${\Delta }_{eff}:effectivestabilityofachip$ $\begin{array}{r}{\Delta }_m:meanstabilityofthebits,{\sigma }_{\Delta }:spread\\ of\Delta acrossbits(Gaussian),\Delta (T):\\ stabilityatabsolutetemperatureT,E_B(T):\\ energybarrier,whichalsofallswithT\\ throughtheanisotropyandthe\\ magnetization\end{array}$ $\begin{array}{r}{k}_B:Boltzmannconstant(8.617\times 10^{-5}\mathrm{eV}/K);\\ Wangetal.:{\Delta }_{eff}isusedforlow-error-rate\\ retention,thetemperaturedependenceis\\ roughlylinearovertherangeofinterest,\\ theirstackreaches1ppmafter10years\\ at142{}^{\circ }Catchiplevelandwasprojected\\ to1ppmin10yearsat225{}^{\circ }Cfora\\ reflow-capablestack;Avalanche:morethan\\ 10yearsat125{}^{\circ }Cfora64MbitpMTJ\\ device,productratingsof10to20years,\\ andretentionfallsathightemperature\\ throughthetemperaturedependenceofthe\\ anisotropy;Everspin:toggleMRAM20years\\ at125{}^{\circ }C(2013note)andmorethan20\\ yearsintheMR25H40datasheet,AEC-Q100\\ Grade1to125{}^{\circ }C\end{array}$ $\begin{array}{r}(computed:{\Delta }_m=60with{\sigma }_{\Delta }=4(assumed)\\ gives{\Delta }_{eff}=52;\Delta =54at142{}^{\circ }Cisat\\ least75at25{}^{\circ }Cand56at125{}^{\circ }Cif{E}_B\\ wereconstant,sothereal\\ room-temperaturevalueishigher)\end{array}$
Survival of solder reflow	${\Delta }_{req}(T_{rf})=\ln \frac{t_{rf}}{{\tau }_0{P}_{flip}}$	$\Delta (25^{\circ }C)\ge {\Delta }_{req}(T_{rf})\frac{T_{rf}}{298\mathrm{K}}$	$\begin{array}{r}{\Delta }_{req}(T_{rf}):stabilityneededatthereflow\\ temperature{T}_{rf}(absolute)foraflip\\ probability{P}_{flip}duringthereflowtime{t}_{rf}\end{array}$ $\begin{array}{r}{\tau }_0:attempttime(1\mathrm{ns},assumed),\Delta (25C):\\ room-temperaturestabilitythatgivesit\\ if{E}_{B}staysconstant(alowerbound);Wang\\ etal.:theMTJstackwasdevelopedto\\ survive260{}^{\circ }Cfor90\mathrm{s},andtheprocess\\ includesa400{}^{\circ }Cannealfor2.5\mathrm{h}after\\ theMTJetch,witharesistanceratioof\\ 175percent,RA=8.5\Omega \mu {\mathrm{m}}^{2}and{H}_c=3300\\ \mathrm{Oe};Avalanche:theembeddedNVMgrade\\ survivesamuchhighertemperatureprofile\\ (reflow)thantheSRAM-replacementgrade\end{array}$ $\begin{array}{r}(computed:90\mathrm{s}at260{}^{\circ }Cwith1ppmneeds\\ {\Delta }_{req}=39.0at533\mathrm{K},andatleast70at25\\ {}^{\circ }Cif{E}_{B}wereconstant)\end{array}$

Read Disturb and Write Errors

Name	Formula	Related Formulae	Variables/Constants
Read disturb	$P_{RD}=1-\exp \left[-\frac{t_{rd}}{{\tau }_0}\exp \left(-\Delta \left(1-\frac{I_{rd}}{I_{c0}}\right)\right)\right]$	$P_{RD,N}=1-{\left(1-P_{RD}\right)}^{N_{rd}}$	$\begin{array}{r}{P}_{RD}:probabilitythatonereadofduration\\ t_{rd}switchesthebit\end{array}$ ${\tau }_0:attempttime$ $\Delta :thermalstabilityfactor$ $I_{rd}:readcurrent$ $I_{c0}:criticalswitchingcurrent$ $\begin{array}{r}{P}_{RD,N}:probabilityafter{N}_{rd}reads(thermally\\ assistedspin-torqueswitching,background\\ knowledge);Wangetal.:writecurrent\\ scaleswiththeMTJareaatconstant\\ currentdensityandinverselywithpulse\\ widthatnanosecondspeed,withtargets\\ above100\mu \mathrm{A}forNVMandbelow50\mu \mathrm{A}for\\ last-levelcache;Everspin:MRAMreadsdo\\ notdisturbthestoredstate,unlikethe\\ destructiveFRAMread(toggleMRAMreads\\ withoutspin-torqueswitchingcurrent,\\ backgroundknowledge)\end{array}$ $\begin{array}{r}(computedwith{\tau }_0=1\mathrm{ns}and{t}_{rd}=10\mathrm{ns}\\ (assumed):\Delta =60and{I}_{rd}/I_{c0}=0.3give\\ 5.7\times 10^{-18}perreadand0.6percentafter\\ 1\times 10^{15}reads;at{I}_{rd}/I_{c0}=0.5thebitis\\ certaintoflipwithin1\times 10^{15}reads,and\Delta \\ =80bringsitbackto4percent)\end{array}$
Write error rate	$WER=\exp \left[-\frac{t_p}{{\tau }_0}\exp \left(-\Delta \left(1-\frac{I_w}{I_{c0}}\right)\right)\right](I_w<I_{c0})$	$I_c(t_p)\propto \frac{1}{t_p}(\text{precessional, ns pulses})$	$\begin{array}{r}WER:probabilitythatawritepulsefails\\ toswitchthebit\end{array}$ $t_p:pulsewidth$ ${\tau }_0:attempttime$ $\Delta :thermalstabilityfactor$ $I_w:writecurrent$ $\begin{array}{r}{I}_{c0}:criticalcurrent,I_c(t_p):switching\\ currentatshortpulses(thermaland\\ precessionalforms,backgroundknowledge);\\ Avalanche:thewritevoltagemustbeset\\ wellabovethemeanswitchingvoltageto\\ keeptheWERlow;Wangetal.:writingis\\ probabilistic,an8\mathrm{Mb}chipwrotewithout\\ errorsandwithoutECCdownto6\mathrm{ns}pulses\\ andwitha1.5\mathrm{ns}pulseinonetest,\\ operationto4.5\mathrm{ns}from-25to125{}^{\circ }C,\\ andnoback-hoppingwasseen,whichthey\\ attributetothepinnedlayer;DiCarloet\\ al.:blockreliabilitytargetsof1\times 10^{-18}\\ forworkingmemoryand1\times 10^{-13}forstorage\\ memory\end{array}$ $\begin{array}{r}(computed:alarger\Delta thatimproves\\ retentionalsoraises{I}_{c0},since{I}_{c0}is\\ proportionalto{E}_{B}inthestandardmodel\\ (backgroundknowledge))\end{array}$

Barrier Breakdown and Field Immunity

Name	Formula	Related Formulae	Variables/Constants
Tunnel barrier breakdown and endurance	$F(N)=1-\exp \left[-{\left(\frac{N}{\eta }\right)}^{\beta }\right],\ln \left[-\ln (1-F)\right]=\beta \ln V+c$	$N_F=\eta {\left[-\ln (1-F)\right]}^{1/\beta }\approx \eta F^{1/\beta }$	$F:fractionoffailedbits$ $N:writecycles$ $\eta :characteristiclife$ $\beta :Weibullshape$ $V:writevoltageacrosstheMgObarrier$ $c:constant$ $\begin{array}{r}{N}_F:cyclestoafailedfractionF;Wanget\\ al.:deviceTDDBbyvoltagerampsfrom0\\ to2\mathrm{V}in8\mathrm{mV}stepsatfourramprates,\\ cleanbreakdown,Weibullshape1.7,chips\\ stressedto1\times 10^{12}cycleson5kbperchip\\ inupto400chips,consistentwiththe\\ deviceprojection,nochangeinsurvivors\\ after1\times 10^{11}cycles,and1\times 10^{13}cyclesof10\\ \mathrm{ns}pulseson64bitswithnoerrorsor\\ resistancedrift;Avalanche:enduranceis\\ limitedbyTDDBofthethintunnel\\ barrier,1\times 10^{14}cyclesata500\mathrm{mV}write\\ pulseona64Mbitdevice,productsrated\\ at1\times 10^{12};Everspin:toggleMRAMhas\\ unlimitedendurance;DiCarloetal.:hard\\ breakdownissuddenandsoftbreakdown\\ gradual\end{array}$ $\begin{array}{r}(computed:if\beta =1.7appliestocycles\\ (myreading),1ppmfailsat3.0\times 10^{-4}\eta ,so\\ a1\times 10^{12}cycletargetneeds\eta ofabout\\ 3.4\times 10^{15})\end{array}$
Immunity to external magnetic fields	$H[\mathrm{Oe}]=\frac{4\pi }{1000}H[A/m]$	$H_{ext}<H_{max}\ll H_c$	$H:magneticfield$ $H_{ext}:externalfield$ $H_{max}:ratedmaximumfield$ $\begin{array}{r}{H}_c:coercivityofthefreelayer;Everspin\\ MR25H40(toggleMRAM):12000A/mmaximum\\ duringwriteandduringreadorstandby;\\ Avalanche(pMTJSTT-MRAM):upto700\mathrm{Oe}in\\ operationand1000\mathrm{Oe}instandbyforone\\ hourwithsub-ppmrawerrorimpact;Wang\\ etal.:mean{H}_{c}above3000\mathrm{Oe},compared\\ withabout300\mathrm{Oe}forabrownand2750\mathrm{Oe}\\ forablackmagneticstripecard\end{array}$ $\begin{array}{r}(computed:12000A/m=151\mathrm{Oe},sotheSTT\\ ratingsare4.6timeshigherinoperation\\ andtheTDK-Headwaycoercivityof3300\mathrm{Oe}\\ is22timeshigher)\end{array}$

Important Questions

Ques: Why does an STT-MRAM bit need a thermal stability factor of about 54 to 60?

Because the free layer reverses by thermal activation, with a probability $1-\exp [-(t/{\tau }_0)e^{-\Delta }]$. With an attempt time of 1 $\mathrm{ns}$, 1 ppm of flips in 10 years requires $\Delta =\ln [t/({\tau }_{0}P)]=54.1$, and 1 ppb requires 61.0 (computed), in agreement with Wang et al., who give 54 for 1 ppm after 10 years. Their further values, $1\times 10^{12}$ years for $\Delta =80$ and $1\times 10^{20}$ years for 100, also match the formula, $1.8\times 10^{12}$ and $8.5\times 10^{20}$ years (computed). The chip value must be met by the weakest bits: Wang et al. use ${\Delta }_{eff}={\Delta }_m-{\sigma }^2/2$, so a mean of 60 with a spread of 4 gives only 52 (computed, assumed spread). Since $\Delta$ falls with temperature, the target must hold at the highest operating temperature. Reference: P. Wang, G. Jan, L. Thomas et al., TDK-Headway Technologies, ‘Development of STT-MRAM for embedded memory applications’, CEA-Leti Memory Workshop, Grenoble, June 2017 (slides; some symbols garbled, fetch-tool summary).

Ques: Is MRAM endurance unlimited or about $1\times 10^{12}$ cycles?

Both are correct for different MRAM types. Everspin rates its toggle MRAM with unlimited write endurance, since the bits are written by the magnetic field of current lines and no current passes through the tunnel barrier. In STT-MRAM, every write drives current through the thin MgO barrier, which wears out by time-dependent dielectric breakdown: Avalanche reports $1\times 10^{14}$ cycles with a 500 $\mathrm{mV}$ write pulse on a 64 Mbit device but rates products at $1\times 10^{12}$, and Wang et al. stressed chips to $1\times 10^{12}$ cycles and devices to $1\times 10^{13}$ cycles without failures. For an STT design, $1\times 10^{12}$ is the more likely rated value and well above flash. The margin depends strongly on the write voltage, which must still be well above the switching voltage to avoid write errors. Reference: Everspin Technologies, ‘MR20H40 / MR25H40 4Mb SPI MRAM’ data sheet, Rev. 12.6 (August 2020) (fetch-tool summary); Avalanche Technology, ‘Data Endurance, Retention and Field Immunity in STT-MRAM’, Application Note AN000002, Rev. C (June 2021) (fetch-tool summary); P. Wang, G. Jan, L. Thomas et al., TDK-Headway Technologies, ‘Development of STT-MRAM for embedded memory applications’, CEA-Leti Memory Workshop, Grenoble, June 2017 (slides; some symbols garbled, fetch-tool summary).

Ques: How hot can MRAM run before it loses data?

It depends on the stack. Everspin rates its toggle MRAM at 20 years at 125 ${}^{\circ }\mathrm{C}$ in its 2013 comparison and to AEC-Q100 Grade 1 (125 ${}^{\circ }\mathrm{C}$) in the MR25H40 data sheet. Avalanche reports more than 10 years at 125 ${}^{\circ }\mathrm{C}$ for a 64 Mbit pMTJ device, and Wang et al. reached 1 ppm in 10 years at 142 ${}^{\circ }\mathrm{C}$ at chip level. The limit comes from the stability factor, which falls with temperature both through $k_{B}T$ and through the anisotropy, as Avalanche notes. If the barrier stayed constant, $\Delta =54$ at 142 ${}^{\circ }\mathrm{C}$ would correspond to at least 75 at 25 ${}^{\circ }\mathrm{C}$ (computed), so a stack designed for 125 ${}^{\circ }\mathrm{C}$ has a large margin at room temperature, and the hot specification is the one to check. Reference: C. Bohac, Everspin Technologies, ‘Comparing Technologies: MRAM vs. FRAM’, Application Note 02130 (March 2013) (fetch-tool summary); Everspin Technologies, ‘MR20H40 / MR25H40 4Mb SPI MRAM’ data sheet, Rev. 12.6 (August 2020) (fetch-tool summary); Avalanche Technology, ‘Data Endurance, Retention and Field Immunity in STT-MRAM’, Application Note AN000002, Rev. C (June 2021) (fetch-tool summary); P. Wang, G. Jan, L. Thomas et al., TDK-Headway Technologies, ‘Development of STT-MRAM for embedded memory applications’, CEA-Leti Memory Workshop, Grenoble, June 2017 (slides; some symbols garbled, fetch-tool summary).

Ques: Can embedded STT-MRAM keep its data through solder reflow?

Only if its stability is designed for it. A reflow peak of 260 ${}^{\circ }\mathrm{C}$ for 90 $\mathrm{s}$, the condition Wang et al. designed their stack for, requires $\Delta \ge 39$ at 533 $\mathrm{K}$ for at most 1 ppm of flips with a 1 $\mathrm{ns}$ attempt time (computed). With a constant barrier, this means at least 70 at 25 ${}^{\circ }\mathrm{C}$ (computed), well above the 54 needed for ten years at room temperature, and the anisotropy also falls at high temperature, so the real requirement is higher. Wang et al. projected 1 ppm in 10 years at 225 ${}^{\circ }\mathrm{C}$ for such a stack, which also survives a 400 ${}^{\circ }\mathrm{C}$ anneal for 2.5 $\mathrm{h}$ after the junction etch. Avalanche distinguishes a reflow-capable embedded NVM grade from an SRAM-replacement grade with lower stability. Reference: P. Wang, G. Jan, L. Thomas et al., TDK-Headway Technologies, ‘Development of STT-MRAM for embedded memory applications’, CEA-Leti Memory Workshop, Grenoble, June 2017 (slides; some symbols garbled, fetch-tool summary); Avalanche Technology, ‘Data Endurance, Retention and Field Immunity in STT-MRAM’, Application Note AN000002, Rev. C (June 2021) (fetch-tool summary).

Ques: How strong a magnetic field can MRAM tolerate?

Toggle MRAM is far more sensitive than modern perpendicular STT-MRAM. Everspin’s MR25H40 allows at most 12 000 $A/m$ during write, read or standby, which is 151 $\mathrm{Oe}$ (computed). Avalanche reports immunity up to 700 $\mathrm{Oe}$ in operation and 1000 $\mathrm{Oe}$ in standby for one hour, with sub-ppm impact on the raw error rate, 4.6 times the toggle rating in operation (computed). Wang et al. give a mean coercivity above 3000 $\mathrm{Oe}$ for their pMTJ, compared with about 300 $\mathrm{Oe}$ for a brown and 2750 $\mathrm{Oe}$ for a black magnetic stripe card. A small permanent magnet near the package can exceed the toggle rating, so toggle parts may need magnetic shielding or spacing, while pMTJ parts are robust against everyday fields (my reading). Reference: Everspin Technologies, ‘MR20H40 / MR25H40 4Mb SPI MRAM’ data sheet, Rev. 12.6 (August 2020) (fetch-tool summary); Avalanche Technology, ‘Data Endurance, Retention and Field Immunity in STT-MRAM’, Application Note AN000002, Rev. C (June 2021) (fetch-tool summary); P. Wang, G. Jan, L. Thomas et al., TDK-Headway Technologies, ‘Development of STT-MRAM for embedded memory applications’, CEA-Leti Memory Workshop, Grenoble, June 2017 (slides; some symbols garbled, fetch-tool summary).

Ques: Why must the STT-MRAM read current be much smaller than the write current?

Because the read current also exerts spin torque and lowers the effective barrier. In the thermally assisted model the switching probability of one read is about $(t_{rd}/{\tau }_0)\exp [-\Delta (1-I_{rd}/I_{c0})]$ (background knowledge). For $\Delta =60$, a 10 $\mathrm{ns}$ read and a read current of 30 per cent of the critical current, this is $5.7\times 10^{-18}$ per read, or 0.6 per cent after $1\times 10^{15}$ reads of one bit; at 50 per cent the bit would certainly flip, and $\Delta =80$ brings it back to 4 per cent (computed, assumed read time). Read disturb therefore ties the read current, the sensing speed and the stability together. Everspin notes that MRAM reads leave the state intact, unlike the destructive FRAM read, which holds as long as this margin is kept. Reference: C. Bohac, Everspin Technologies, ‘Comparing Technologies: MRAM vs. FRAM’, Application Note 02130 (March 2013) (fetch-tool summary); P. Wang, G. Jan, L. Thomas et al., TDK-Headway Technologies, ‘Development of STT-MRAM for embedded memory applications’, CEA-Leti Memory Workshop, Grenoble, June 2017 (slides; some symbols garbled, fetch-tool summary).

Ques: What does the Weibull shape of 1.7 imply for STT-MRAM barrier endurance?

Wang et al. fitted the breakdown of their MgO barriers with a Weibull shape of 1.7 and used it to project endurance to the ppm level. If the shape applies to the cycle count (my reading), the cycles to a failed fraction $F$ scale as $\eta F^{1/\beta }$, so 1 ppm fails at $3.0\times 10^{-4}$ of the characteristic life, and a $1\times 10^{12}$ cycle target needs a characteristic life of about $3.4\times 10^{15}$ cycles (computed). A low shape means an early-failure tail, which is why the chip-level test on up to 400 chips, consistent with the device projection, matters more than the device average. Their fit also uses the logarithm of the voltage, so a small reduction of the write voltage gains much endurance, which is consistent with Avalanche’s $1\times 10^{14}$ cycles at a low 500 $\mathrm{mV}$ write pulse (my reading). Reference: P. Wang, G. Jan, L. Thomas et al., TDK-Headway Technologies, ‘Development of STT-MRAM for embedded memory applications’, CEA-Leti Memory Workshop, Grenoble, June 2017 (slides; some symbols garbled, fetch-tool summary); Avalanche Technology, ‘Data Endurance, Retention and Field Immunity in STT-MRAM’, Application Note AN000002, Rev. C (June 2021) (fetch-tool summary); Failure Rate and the Bathtub Curve page of this vault.

Related pages in this vault: Static and Dynamic Random Access Memory (SRAM and DRAM), Spin-Transfer Torque Magnetic Random Access Memory (STT-MRAM), Magnetic Force Microscope (MFM), Toggle Magnetic Random Access Memory (Toggle MRAM), Ferroelectric Random Access Memory (FeRAM, PZT and HfO2), Floating Gate and Charge-Trap Flash Memory (NOR, NAND and 3D NAND), Voltage-Controlled Magnetic Anisotropy MRAM (VCMA-MRAM), Static Random Access Memory (SRAM), Spin-Orbit Torque Magnetic Random Access Memory (SOT-MRAM).