This page covers the wear-out and the data loss of floating-gate flash (NOR and planar NAND) and charge-trap flash (SONOS, TANOS and 3D NAND): oxide damage and charge trapping from program/erase cycling, stress-induced leakage, retention loss including the early retention loss of 3D NAND, read disturb, cell-to-cell interference and layer-to-layer variation. The cell physics is on the Floating Gate Flash and Charge Trap Flash device pages, the oxide breakdown and trap models on the CMOS Logic Transistors page and the lifetime statistics on the Failure Rate page; controller algorithms are outside the scope of the vault and are named only where they set the device requirement.

1. Why It Happens

Trigger: Program and erase pulses that drive Fowler-Nordheim tunnelling through the tunnel oxide (Cai et al.); storage time, especially at high temperature (Viking; Swissbit); reads of other pages in the same block (Cai et al. DSN 2015); programming of neighbouring cells (Cai et al.).
Mechanism, wear-out: Cycling traps electrons in the tunnel oxide, which shifts and widens the threshold distributions, and at high cycle counts trapped charge forms percolation paths; the trapped charge grows about as the square root of the cycles (Cai et al.; Swissbit).
Mechanism, retention: Stored electrons leak by trap-assisted tunnelling and stress-induced leakage current (SILC) through the damaged oxide, high states move down and the erased state moves up (Cai et al.); trapped oxide charge detraps with a logarithmic time dependence (Swissbit); in charge-trap cells charge also moves vertically to the substrate and laterally along the continuous trap layer to neighbours at different levels (Saikia and Mahapatra).
Mechanism, disturb and interference: The pass voltage on unread word lines weakly programs their cells, the lower states most (Cai et al. DSN 2015); capacitive coupling shifts a cell when its neighbours are programmed (Cai et al.).
What sets the rate: The number of cycles and the cycling rate, since damage partly recovers between cycles (Viking; Swissbit); the temperature, with 1.1 $eV$ for detrapping but a negative activation energy for SILC (Viking); the read count and the pass voltage (Cai et al. DSN 2015); the cell size, with only about 100 electrons per 1x-nm cell (Cai et al.); the layer position in 3D NAND (Luo et al.).
Failure criterion: A raw bit error rate beyond the ECC limit, about $1 \times 1 0^{- 3}$ to $1 \times 1 0^{- 2}$ , which leaves an uncorrectable rate above the $1 \times 1 0^{- 15}$ target (Cai et al.); retention shorter than 10 years at below 10 per cent of the rated cycles or 1 year at the rated cycles (Viking; Swissbit).

2. Where to Look

Location: The tunnel oxide under the storage node (Cai et al.); the gaps between cells along the bit line of 3D NAND, where lateral migration occurs (Saikia and Mahapatra); the middle and lower layers of a 3D NAND string, which have the highest error rates (Luo et al.); the most-significant-bit pages (Luo et al.).
Signature: Threshold distributions that shift right and widen with cycling (Cai et al.); high states that move down and erased cells that move up with retention time (Cai et al.); an error rate that rises by an order of magnitude within hours after programming in 3D NAND (Luo et al.); errors that grow with the read count in the lower states (Cai et al. DSN 2015).
Confirm with: Threshold-distribution measurements by read-voltage sweeps (Cai et al.); retention bakes for detrapping plus a 25 $^{\circ} C$ test for SILC after cycling (Viking); read-disturb tests with reads of a neighbouring word line (Cai et al. DSN 2015).
Look-alikes: Early failures caused by a qualification test that cycles too fast for the oxide to recover, which does not represent use (Viking; Swissbit); program interference, which appears at programming of the neighbours rather than with time (Cai et al.); temporary early retention loss in 3D NAND, which looks like a weak block (Luo et al.).

3. Prevention

Design: Leave ECC margin above the end-of-life raw error rate, since the codeword failure rate rises steeply near the limit (Cai et al.); use the rated retention at the rated cycles, 1 year, not the 10 years of a fresh device (Viking).
Material and process: Reduce cell-to-cell coupling, which nearly doubled from 2y-nm to 1x-nm (Cai et al.); limit lateral migration in the continuous trap layer of 3D NAND (Saikia and Mahapatra; background knowledge).
Operation: Keep the P/E count below the rating and store devices at room temperature or cooler (Viking); lower the pass voltage where the ECC margin allows (Cai et al. DSN 2015); adapt read voltages to retention age and layer (Luo et al.).
Screening and test: Spread cycling in qualification so that the oxide recovers, for example by reaching the rated cycles at +85 $^{\circ} C$ in about 1000 $h$ rather than in a few days (Swissbit; Viking); test retention after cycling both with a bake and at 25 $^{\circ} C$ (Viking).

Endurance and Error Correction

Name	Formula	Related Formulae	Variables/Constants
Endurance and charge build-up with cycling	$Δ V_{T H, t r a p} (N) = A_{t r} N$	$N_{ma x} : 1.5 \times 1 0^{5} (SLC), 1 0^{4} (5 x MLC), 3 \times 1 0^{3} (1 x MLC), 1 0^{3} (1 x TLC)$	$Δ V_{T H, t r a p} : t h r es h o l d s hi f t f r o m c ha r g e t r a pp e d in t h e t u nn e l o x i d e$ $A_{t r} : t ec hn o l o g y co n s t an t$ $N : p r o g r am / er a se (P / E) cy c l es$ $N_{ma x} : r a t e d e n d u r an ce; S w i ss bi t : c ha r g e t r a pp in g g r o w s w i t h t h e s q u a r e r oo t o f t h e P / E cy c l es an d d e t r a pp in g w i t h t h e l o g a r i t hm o f t im e; C ai e t a l . : o l d er S L C w i t h s t oo d ab o u t 150000 cy c l es p er ce l l, 5 x - nm M L C ab o u t 10000 p er b l oc k, 1 x - nm M L C an d T L C ab o u t 3000 an d 1000, w e a r - o u t i s e l ec t r o n t r a pp in g in t h e t u nn e l o x i d e, an d a f t er 3000 cy c l es e a c h T L C s t a t e s hi f t s r i g h t an d w i d e n s, t h e l o w er s t a t es m or e; a t hi g h cy c l e co u n t s t r a pp e d c ha r g e c an f or m p er co l a t i o n p a t h s t h r o ug h t h e o x i d e$ $(co m p u t e d : f r o m 1000 t o 3000 cy c l es t h e t r a pp e d s hi f t g r o w s b y 3 = 1.73 t im es; S L C t o 1 x - nm M L C i s a 50 - f o l d l oss o f e n d u r an ce)$
Threshold step per stored electron	$Δ V_{T H, 1 e} = \frac{q}{C _{C G}} \approx \frac{Δ V _{w in}}{n _{e}}$	$Δ V_{T H} = \frac{q Δ n _{e}}{C _{C G}}$	$Δ V_{T H, 1 e} : t h r es h o l d s hi f t f or o n e e l ec t r o n$ $q : e l e m e n t a r y c ha r g e$ $C_{C G} : co n t r o l - g a t e t o s t or a g e - n o d e c a p a c i t an ce$ $Δ V_{w in} : p r o g r amm e d t h r es h o l d w in d o w$ $n_{e} : e l ec t r o n s t ha t s p an t h e w in d o w$ $Δ n_{e} : e l ec t r o n s l os t (ba c k g r o u n d k n o w l e d g e; ce l l p h y s i cs o n t h e F l o a t in g G a t e F l a s h p a g e); C ai e t a l . : a m o d er n 1 x - nm M L C ce l l s t or es o n l y ab o u t 100 e l ec t r o n s$ $(co m p u t e d : a 3 V w in d o w (a ss u m e d) an d 100 e l ec t r o n s g i v e 30 mV p er e l ec t r o n, so a l oss o f t e n e l ec t r o n s s hi f t s t h e ce l l b y 0.3 V, ab o u t o n e M L C s t a t e s p a c in g)$
Codeword failure probability with ECC	$P_{E C F R} = \sum_{k = t + 1}^{l} (k l) R B E R^{k} (1 - R B E R)^{l - k}$	$R B E R_{ma x} \approx 1 0^{- 3} to 1 0^{- 2}, U B E R_{t a r g e t} = 1 0^{- 15}$	$P_{E C F R} : p r o babi l i t y t ha t a co d e w or d ha s m or e er r or s t han t h e co d e c an cor r ec t$ $l : co d e w or d l e n g t h in bi t s$ $t : cor r ec t ab l e bi t s$ $R B E R : r a w bi t er r or r a t e (er r or s a ss u m e d in d e p e n d e n t)$ $U B E R : u n cor r ec t ab l e bi t er r or r a t e a f t er cor r ec t i o n; C ai e t a l . : E C C e n g in es han d l e r a w er r or r a t es o f ab o u t 1 \times 1 0^{- 3} t o 1 \times 1 0^{- 2} an d t h e J E D E C t a r g e t a f t er cor r ec t i o n i s 1 \times 1 0^{- 15}; C ai e t a l . (D S N 2015) : t h e i r E C C t o l er a t es u p t o 1 \times 1 0^{- 3}; Lu o e t a l . : E C C l imi t 3 \times 1 0^{- 3} an d a ba se l in e B C H o v er h e a d o f 12.8 p er ce n t$ $(co m p u t e d : f or l = 9000 an d t = 40 (a ss u m e d), P_{E C F R} = 5.9 \times 1 0^{- 15} a t R B E R 1 \times 1 0^{- 3}, 2.2 \times 1 0^{- 6} a t 2 \times 1 0^{- 3}, 7.1 \times 1 0^{- 3} a t 3 \times 1 0^{- 3} an d 0.22 a t 4 \times 1 0^{- 3}, so t h e ma r g in c l oses w i t hin a f a c t or o f tw o t o t h r ee in r a w er r or r a t e)$

Retention

Name	Formula	Related Formulae	Variables/Constants
Arrhenius acceleration of a retention bake	$A F = exp [\frac{E _{a}}{k _{B}} (\frac{1}{T _{u se}} - \frac{1}{T _{bak e}})], t_{bak e} = \frac{t _{u se}}{A F}$	$t_{r e t} \propto e^{E_{a} / (k_{B} T)}, E_{a} < 0 (SILC)$	$A F : a cce l er a t i o n f a c t or$ $E_{a} : a c t i v a t i o n e n er g y (1.1 eV f or d e t r a pp in g, V ik in g)$ $k_{B} : B o l t z mann co n s t an t (8.617 \times 1 0^{- 5} eV / K)$ $T_{u se} an d T_{bak e} : ab so l u t e u se an d bak e t e m p er a t u r es$ $t_{bak e} an d t_{u se} : e q u i v a l e n t t im es$ $t_{r e t} : r e t e n t i o n t im e; V ik in g : bak es a r e c h ose n f or 1.1 eV, S I L C ha s an a c t i v a t i o n e n er g y b e l o w 0 eV an d c an o n l y b e ma r g ina l l y a cce l er a t e d or i s e v e n r e d u ce d a t hi g h t e m p er a t u r e, so a 25^{\circ} C t es t f o l l o w s t h e cy c l in g; J E D E C r e q u i r e m e n t (V ik in g, S w i ss bi t) : 10 y e a r s a t b e l o w 10 p er ce n t o f t h e r a t e d cy c l es an d 1 y e a r a t t h e r a t e d cy c l es; S w i ss bi t : a g in g a t + 85^{\circ} C c an r e a c h t h e r a t e d cy c l es w i t hin 1000 h, an d t h e r e t e n t i o n a t e n d o f l i f e a t + 85^{\circ} C i s o n l y a f e w d a y s$ $(co m p u t e d : A F t o 85^{\circ} C i s 1303 f r o m 25^{\circ} C, 643 f r o m 30^{\circ} C, 168 f r o m 40^{\circ} C an d 26 f r o m 55^{\circ} C, so o n e y e a r o f u se e q u a l s 6.7, 13.6, 52 an d 337 h a t 85^{\circ} C)$
Early retention loss of 3D NAND	$ln R B E R = A ln t + B, A = α N_{P E} + β, B = γ N_{P E} + δ$	$R B E R (t) = e^{B} t^{A}$	$R B E R : r a w bi t er r or r a t e$ $t : r e t e n t i o n t im e in seco n d s$ $A an d B : f i t p a r am e t er s$ $N_{P E} : P / E cy c l es$ $α, β, γ, δ : f i t co n s t an t s (Lu o e t a l ., na t u r a l l o g a r i t hm a ss u m e d, s in ce ba se 10 g i v es er r or r a t es n e a r 1 \times 1 0^{- 12}); Lu o e t a l . (3 D M L C c hi p s w i t h 30 t o 40 l a y er s a t 20^{\circ} C, 7 min u t es t o 24 d a y s) : f or M S B p a g es α = 5.49 \times 1 0^{- 6}, β = 0.16, γ = 1.33 \times 1 0^{- 4}, δ = - 13.11 (a d j u s t e d R^{2} 97.2 p er ce n t), t h e r e t e n t i o n er r or r a t e r i ses b y an or d er o f ma g ni t u d e w i t hin ab o u t 3 h o u r s an d a g ain b y ab o u t 1 \times 1 0^{6} s, a t 10000 cy c l es 3 D N A N D e x cee d s pl ana r N A N D a f t er ab o u t 7 \times 1 0^{3} s, t h e o pt ima l r e a d v o l t a g e V_{c} m o v es ab o u t f i v e s t e p s in 3 h o u r s an d f i v e m or e b y d a y 11, an d a ce l l l oses c ha r g e m or e s l o w l y w h e n i t s v er t i c a l n e i g hb o u r i s a t a hi g h er s t a t e$ $(co m p u t e d : a t 10000 cy c l es A = 0.215 an d B = - 11.78, so R B E R = 2.8 \times 1 0^{- 5} a t 7 min u t es, 5.6 \times 1 0^{- 5} a t 3 h o u r s an d 1.5 \times 1 0^{- 4} a t 11.6 d a y s, c l ose t o t h e p a p e r^{'} s a v er a g e o f 1.6 \times 1 0^{- 4}; t h e f i t r i ses o n l y 2.0 t im es f r o m 7 min u t es t o 3 h o u r s)$
Field-assisted detrapping from the charge-trap layer	$τ_{d t} = ν^{- 1} exp [\frac{E _{B} - γ E _{o x}}{k _{B} T}]$	$E_{B, e f f} = k_{B} T ln (ν τ_{d t})$	$τ_{d t} : d e t r a pp in g t im e$ $ν : a tt e m pt - t o - esc a p e f r e q u e n cy (1 \times 1 0^{13} s^{- 1})$ $E_{B} : t r a p ba r r i er (m e an 2.8 eV, s p r e a d 0.3 eV)$ $γ : f i e l d a cce l er a t i o n f a c t or$ $E_{o x} : f i e l d a cr oss t h e t u nn e l o x i d e$ $k_{B} : B o l t z mann co n s t an t (8.617 \times 1 0^{- 5} eV / K)$ $T : ab so l u t e t e m p er a t u r e$ $E_{B, e f f} : e f f ec t i v e ba r r i er t ha t g i v es τ_{d t} (t h e A r r h e ni u s f or m i s m y r e a d in g o f S aik ia an d M aha p a t r a, w h ose r a t e e q u a t i o n s a r e o n l y in a f i g u r e); S aik ia an d M aha p a t r a : v er t i c a l d e t r a pp in g t h r o ug h t h e t u nn e l o x i d e g r o w s w i t h t h e p r o g r am l e v e l, l a t er a l mi g r a t i o n a l o n g t h e co n t in u o u s t r a p l a y er g r o w s w i t h t h e t h r es h o l d d i f f er e n ce t o t h e n e i g hb o u r in g ce l l s, t r a p - a ss i s t e d t u nn e l l in g a f f ec t s t h e d i s t r ib u t i o n t ai l s, bak es a t 85, 90 an d 200^{\circ} C a f t er 300 cy c l es, N_{0} = 2 \times 1 0^{13} t o 4 \times 1 0^{13} c m^{- 2}$ $(co m p u t e d : a d e t r a pp in g t im e o f 1 h a t 85^{\circ} C cor r es p o n d s t o E_{B, e f f} = 1.18 eV, so t h e o x i d e f i e l d an d t h e ba r r i er s p r e a d m u s t l o w er t h e 2.8 eV m e an ba r r i er s t r o n g l y f or l oss w i t hin h o u r s (m y r e a d in g))$

Disturb, Interference and Layer Variation

Name	Formula	Related Formulae	Variables/Constants
Read disturb against read count and pass voltage	$R B E R (N_{r d}) \approx R B E R_{0} + s (N_{P E}) N_{r d}$	$N_{r d, t o l} \propto e^{- c V_{p a ss}}, M = (1 - 0.2) C - M E E$	$R B E R : r a w bi t er r or r a t e$ $R B E R_{0} : r a t e w i t h o u t d i s t u r b$ $s : s l o p e t ha t g r o w s w i t h t h e P / E cy c l es N_{P E}$ $N_{r d} : r e a d s o f o t h er p a g es o f t h e b l oc k$ $N_{r d, t o l} : r e a d s t o l er ab l e a t a f i x e d R B E R$ $c : co n s t an t$ $V_{p a ss} : p a ss - t h r o ug h v o l t a g e o n t h e u n r e a d w or d l in es$ $M : E C C ma r g in l e f t f or l o w er in g V_{p a ss}$ $C : ma x im u m cor r ec t ab l e bi t s$ $M E E : ma x im u m es t ima t e d er r or (C ai e t a l . D S N 2015, l in e a r an d e x p o n e n t ia l f or m s a s d escr ib e d t h er e); C ai e t a l . : ab o u t + 6 V p a ss v o l t a g e a g ain s t ab o u t + 15 V f or p r o g r ammin g, r e a d d i s t u r b o n se t a t ab o u t 1 \times 1 0^{6} r e a d s f or S L C, 1 \times 1 0^{5} f or e a r l y M L C an d 2 \times 1 0^{4} f or 2 Y - nm M L C, t h e l o w er s t a t es s hi f t m os t, l o w er in g V_{p a ss} b y 2 p er ce n t a t 1 \times 1 0^{5} r e a d s c u t s R B E R b y u p t o 50 p er ce n t, a 4 p er ce n t r e d u c t i o n i s s a f e a t 8000 cy c l es b e l o w 4 d a y s o f r e t e n t i o n a g e, t oo l o w a V_{p a ss} l e a v es u n r e a d ce l l s o f f, V p a ss T u nin g g i v es 21.0 p er ce n t m or e e n d u r an ce, an d R e a d D i s t u r b R eco v er y r e m o v es u p t o 36 p er ce n t o f er r or s a t 1 \times 1 0^{6} d i s t u r b s$ $(co m p u t e d : t h e o n se t f e l l 50 t im es f r o m S L C t o 2 Y - nm M L C)$
Cell-to-cell program interference	$Δ V_{v i c t im} = \sum_{X} K_{X} Δ V_{X}$	$K_{W L} > K_{B L} > K_{d ia g}$	$Δ V_{v i c t im} : t h r es h o l d s hi f t o f t h e v i c t im ce l l$ $K_{X} : co u pl in g coe f f i c i e n t t o n e i g hb o u r X$ $Δ V_{X} : t h r es h o l d c han g e o f t ha t n e i g hb o u r d u r in g i t s p r o g r ammin g$ $K_{W L}, K_{B L}, K_{d ia g} : w or d - l in e, bi t - l in e an d d ia g o na l coe f f i c i e n t s; C ai e t a l . (T ab l e 2) : 0.060, 0.032 an d 0.012 f or 2 y - nm an d 0.110, 0.055 an d 0.020 f or 1 x - nm, t h e w or d - l in e n e i g hb o u r c a u ses t h e l a r g es t in t er f er e n ce, tw o - s t e p p r o g r ammin g er r or s m os tl y m o v e ce l l s f r o m l o w er t o hi g h er s t a t es, an d n e i g hb o u r - ce l l - a ss i s t e d cor r ec t i o n e x t e n d s t h e l i f e t im e b y 33 p er ce n t$ $(co m p u t e d : a 2 V c han g e o f t h e w or d - l in e n e i g hb o u r s hi f t s t h e v i c t im b y 0.12 V a t 2 y - nm an d 0.22 V a t 1 x - nm; o n e w or d - l in e an d o n e bi t - l in e n e i g hb o u r an d tw o d ia g o na l n e i g hb o u r s, a l l a t 2 V, g i v e 0.41 V a t 1 x - nm (a ss u m e d p a tt er n))$
Layer-to-layer variation in 3D NAND	$R B E R_{p a g e} \sim Γ (k, θ), r_{l a y er} = \frac{R B E R _{w or s t}}{R B E R _{b es t}}$	$N_{l i f e} \propto [R B E R^{- 1}]_{w or s t p a g e}$	$R B E R_{p a g e} : r a w er r or r a t e o f o n e p a g e, Γ (k, θ) : g amma d i s t r ib u t i o n w i t h s ha p e k an d sc a l e θ$ $r_{l a y er} : r a t i o b e tw ee n t h e w or s t an d t h e b es t l a y er$ $N_{l i f e} : P / E l i f e t im e, se t b y t h e w or s t p a g e t ha t r e a c h es t h e E C C l imi t (m y r e a d in g); Lu o e t a l . : t h e M S B p a g e in t h e mi dd l e l a y er ha s 21 t im es t h e R B E R o f l a y er 0 (S ec t i o n 4.2), t h e in t r o d u c t i o n s t a t es 6 t im es a g ain s t t h e t o p l a y er, M S B p a g es a v er a g e 2.4 t im es L S B p a g es, t h e u pp er ha l f o f t h e l a y er s i s b e tt er t han t h e l o w er ha l f, v a r ia t i o n - a w a r e r e a d v o l t a g es l o w er t h e a v er a g e R B E R f r o m 1.6 \times 1 0^{- 4} t o 1.4 \times 1 0^{- 4}, L I - R A I D l o w er s t h e w or s t c a se f r o m 4.8 \times 1 0^{- 4} t o 1.6 \times 1 0^{- 4}, an d a l l t h e i r t ec hni q u es t o g e t h er g i v e 85.0 p er ce n t m or e l i f e t im e a t an E C C l imi t o f 3 \times 1 0^{- 3}, w hi l e f l a s h cor r ec t - an d - r e f r es h g i v es 2.7 t im es in 3 D a g ain s t 50 t im es in pl ana r N A N D$ $(co m p u t e d : L I - R A I D r e d u ces t h e w or s t p a g e b y 3.0 t im es, c l ose t o t h e 2.4 t im es M S B t o L S B r a t i o)$

Important Questions

Ques: Why did flash endurance fall from 150 000 cycles to about 1000?

Because the cells shrank and store more levels. Cai et al. give about 150 000 cycles for older SLC, about 10 000 per block for 5x-nm MLC and about 3000 and 1000 for 1x-nm MLC and TLC, a 50-fold loss from SLC to 1x-nm MLC (computed). Each cycle traps electrons in the tunnel oxide, which shifts and widens the threshold distributions, and Swissbit states that the trapped charge grows about as the square root of the cycles. A 1x-nm MLC cell stores only about 100 electrons, so with an assumed 3 $V$ window each electron moves the threshold by about 30 $mV$ , and a few lost or trapped charges are enough to cross a state boundary (computed). TLC packs eight states into the same window, so its margins are even smaller. Reference: Y. Cai, S. Ghose, E. F. Haratsch, Y. Luo and O. Mutlu, ‘Error Characterization, Mitigation, and Recovery in Flash-Memory-Based Solid-State Drives’, Proceedings of the IEEE (September 2017), arXiv:1706.08642v3, with the companion survey arXiv:1711.11427 (fetch-tool summaries); Swissbit, ‘NAND flash endurance testing’, Application Note AN2107en, Rev. 1.0 (2022) (fetch-tool summary).

Ques: How many hours at 85 degrees Celsius equal one year of retention, and is that consistent with ‘a few days’ at end of life?

With the 1.1 $eV$ activation energy that Viking gives for detrapping, the acceleration factor to 85 $^{\circ} C$ is 643 from 30 $^{\circ} C$ and 168 from 40 $^{\circ} C$ , so one year of storage equals 13.6 $h$ or 52 $h$ at 85 $^{\circ} C$ (computed). Swissbit states that at end of life the retention at +85 $^{\circ} C$ is only a few days, while the JEDEC requirement quoted by both notes is one year at the rated cycles. The two agree if the one year applies at about 40 $^{\circ} C$ , where it equals 2.2 days at 85 $^{\circ} C$ (computed, my reading). The calculation holds only for detrapping, since SILC does not accelerate with temperature, so a bake alone cannot confirm the year. Reference: Viking Technology, ‘Flash Data Retention’, Application Note AN0011, Rev. B (2011, revised 2017) (fetch-tool summary); Swissbit, ‘NAND flash endurance testing’, Application Note AN2107en, Rev. 1.0 (2022) (fetch-tool summary).

Ques: Why can a high-temperature bake not prove the retention of a cycled flash cell?

Because the two charge-loss mechanisms respond to temperature in opposite ways. Viking states that bake conditions are chosen for an activation energy of 1.1 $eV$ , which accelerates the detrapping of oxide charge strongly, but that stress-induced leakage current has an activation energy below 0 $eV$ . SILC can therefore only be marginally accelerated, or is even reduced, at high temperature, and a cycled cell that passes a bake can still lose charge through a leaky oxide at room temperature. The qualification flow therefore adds a 25 $^{\circ} C$ retention test after the cycling. Cai et al. describe how trapped charge forms a path that strengthens SILC, so the leak grows with the cycle count, and the test must be done at the rated cycles, not on fresh devices. Reference: Viking Technology, ‘Flash Data Retention’, Application Note AN0011, Rev. B (2011, revised 2017) (fetch-tool summary); Y. Cai, S. Ghose, E. F. Haratsch, Y. Luo and O. Mutlu, ‘Error Characterization, Mitigation, and Recovery in Flash-Memory-Based Solid-State Drives’, Proceedings of the IEEE (September 2017), arXiv:1706.08642v3, with the companion survey arXiv:1711.11427 (fetch-tool summaries).

Ques: Does the speed of cycling during a test change the measured endurance?

Yes, and a fast test is pessimistic. Viking states that retention is inversely related to the rate of P/E cycling, because the damage partly recovers between cycles, and that a qualification that reaches the rated count in a few days builds up trapped charge that can cause failures during cycling or in the following retention test. Swissbit adds that in use the cycles are spread over at least three years, so a stress test must leave time for recovery through breaks, a lower write speed or a higher temperature. As an example it reaches the rated cycles at +85 $^{\circ} C$ within 1000 $h$ , and it warns against stress that reaches the specified life in only a few days. Both cite the JEDEC EEPROM and flash stress test methods. Reference: Viking Technology, ‘Flash Data Retention’, Application Note AN0011, Rev. B (2011, revised 2017) (fetch-tool summary); Swissbit, ‘NAND flash endurance testing’, Application Note AN2107en, Rev. 1.0 (2022) (fetch-tool summary).

Ques: Does the 3D NAND error rate rise tenfold in three hours, or twofold as the fitted model gives?

Luo et al. write that the retention error rate of a 3D NAND block rises by an order of magnitude within about 3 hours, and they fit $ln R B E R = A ln t + B$ to measurements from 7 minutes to 24 days. With their MSB parameters at 10 000 cycles, $A = 0.215$ , the fit rises only 2.0 times from 7 minutes to 3 hours (computed). The fit reproduces the long-term level well, $1.5 \times 1 0^{- 4}$ at 11.6 days against an average of $1.6 \times 1 0^{- 4}$ (computed). The likely explanation is that the order of magnitude is counted from the moment after programming, before the first 7 minute point, when most of the fast detrapping happens (my reading). For refresh planning the measured statement is the more relevant one, and for later times the fit. Reference: Y. Luo, S. Ghose, Y. Cai, E. F. Haratsch and O. Mutlu, ‘Improving 3D NAND Flash Memory Lifetime by Tolerating Early Retention Loss and Process Variation’, Proc. ACM Meas. Anal. Comput. Syst. (SIGMETRICS) 2018, arXiv:1807.05140v2 (fetch-tool summary).

Ques: Is the middle layer of a 3D NAND string 21 or 6 times worse than the best layer?

Luo et al. give both numbers. Section 4.2 reports that the MSB page in the middle layer, at normalized layer 55, has 21 times the raw error rate of layer 0, while the introduction says the middle layer can be 6 times worse than the top layer. Both can be true if layer 0 is the best layer and the top layer is not, since the paper also reports that the upper half of the layers has lower error rates than the lower half (my reading). The 21 times value, from the detailed measurement against the best layer, is the more likely worst case. The variation matters because the lifetime is set by the worst page: LI-RAID cut the worst-case RBER from $4.8 \times 1 0^{- 4}$ to $1.6 \times 1 0^{- 4}$ and all their techniques together gave 85 per cent more lifetime. Reference: Y. Luo, S. Ghose, Y. Cai, E. F. Haratsch and O. Mutlu, ‘Improving 3D NAND Flash Memory Lifetime by Tolerating Early Retention Loss and Process Variation’, Proc. ACM Meas. Anal. Comput. Syst. (SIGMETRICS) 2018, arXiv:1807.05140v2 (fetch-tool summary).

Ques: How does reading a NAND block damage data that is not being read?

Every read applies a pass voltage of about +6 $V$ to the unread word lines of the block, against about +15 $V$ for programming, which weakly programs their cells and shifts the lower states up most. Cai et al. found that the raw error rate rises about linearly with the read count, faster in worn blocks, and that the onset fell from about $1 \times 1 0^{6}$ reads for SLC to $1 \times 1 0^{5}$ for early MLC and $2 \times 1 0^{4}$ for 2Y-nm MLC, a 50-fold drop (computed). Lowering the pass voltage by 2 per cent cut the error rate at $1 \times 1 0^{5}$ reads by up to half, and the tolerable reads grow exponentially as it falls, but too low a value leaves unread cells off. Their Vpass Tuning gained 21 per cent endurance, and Read Disturb Recovery removed up to 36 per cent of errors. Reference: Y. Cai, Y. Luo, S. Ghose, E. F. Haratsch, K. Mai and O. Mutlu, ‘Read Disturb Errors in MLC NAND Flash Memory: Characterization, Mitigation, and Recovery’, Proc. DSN 2015 (summary version arXiv:1805.03283, fetch-tool summary); Y. Cai, S. Ghose, E. F. Haratsch, Y. Luo and O. Mutlu, ‘Error Characterization, Mitigation, and Recovery in Flash-Memory-Based Solid-State Drives’, Proceedings of the IEEE (September 2017), arXiv:1706.08642v3, with the companion survey arXiv:1711.11427 (fetch-tool summaries).

Ques: Why does program interference grow as NAND cells shrink?

Because the coupling between the storage nodes of neighbouring cells grows as the spacing falls. Cai et al. give coupling coefficients of 0.060 to the word-line neighbour, 0.032 to the bit-line neighbour and 0.012 diagonally for 2y-nm cells, and 0.110, 0.055 and 0.020 for 1x-nm cells. The victim shift is the sum of the coefficients times the neighbours’ threshold changes, so a 2 $V$ change of the word-line neighbour moves the victim by 0.12 $V$ at 2y-nm and 0.22 $V$ at 1x-nm (computed). With several neighbours programmed, the shift reaches about 0.4 $V$ (computed, assumed pattern), comparable to the state spacing of MLC. Programming order and neighbour-cell-assisted correction, which extended the lifetime by 33 per cent, limit the effect. Reference: Y. Cai, S. Ghose, E. F. Haratsch, Y. Luo and O. Mutlu, ‘Error Characterization, Mitigation, and Recovery in Flash-Memory-Based Solid-State Drives’, Proceedings of the IEEE (September 2017), arXiv:1706.08642v3, with the companion survey arXiv:1711.11427 (fetch-tool summaries).

Ques: How close to the ECC limit can the raw error rate get?

Not very close, because the codeword failure probability is a binomial tail that rises steeply. For an assumed 9000 bit codeword that corrects 40 errors, the probability of an uncorrectable codeword is $5.9 \times 1 0^{- 15}$ at a raw error rate of $1 \times 1 0^{- 3}$ , $2.2 \times 1 0^{- 6}$ at $2 \times 1 0^{- 3}$ , $7.1 \times 1 0^{- 3}$ at $3 \times 1 0^{- 3}$ and 0.22 at $4 \times 1 0^{- 3}$ (computed). The margin therefore closes within a factor of two to three in raw error rate. Cai et al. state that ECC engines handle raw rates of about $1 \times 1 0^{- 3}$ to $1 \times 1 0^{- 2}$ against a JEDEC target of $1 \times 1 0^{- 15}$ after correction, and Luo et al. use a limit of $3 \times 1 0^{- 3}$ . Since cycling, retention and read disturb all raise the raw rate together, the end-of-life raw rate must include all three. Reference: Y. Cai, S. Ghose, E. F. Haratsch, Y. Luo and O. Mutlu, ‘Error Characterization, Mitigation, and Recovery in Flash-Memory-Based Solid-State Drives’, Proceedings of the IEEE (September 2017), arXiv:1706.08642v3, with the companion survey arXiv:1711.11427 (fetch-tool summaries); Y. Luo, S. Ghose, Y. Cai, E. F. Haratsch and O. Mutlu, ‘Improving 3D NAND Flash Memory Lifetime by Tolerating Early Retention Loss and Process Variation’, Proc. ACM Meas. Anal. Comput. Syst. (SIGMETRICS) 2018, arXiv:1807.05140v2 (fetch-tool summary); Failure Rate and the Bathtub Curve page of this vault.

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Floating Gate and Charge-Trap Flash Memory (NOR, NAND and 3D NAND)