This page covers the degradation of volatile memory cells: the retention loss, variable retention time and read disturbance (RowHammer) of one-transistor one-capacitor DRAM, and the loss of read stability of six-transistor SRAM cells through bias temperature instability. Soft errors from particles are on the Radiation page, the BTI and hot-carrier kinetics of the transistors on the CMOS Logic Transistors page, and the cell physics on the DRAM and SRAM device pages; array, sense-amplifier and controller circuits are outside the scope of the vault, so mitigations are named only where they set the device requirement.

1. Why It Happens

Trigger: The time between refreshes and the temperature for DRAM retention (Liu et al.); repeated activation of a neighbouring row, or a row kept open for long, for read disturbance (Kim et al.; Luo et al.); long DC stress of the cross-coupled inverters at high temperature for SRAM (Duan et al.; Asenov et al.).
Mechanism, retention: The stored charge leaks through the junction of the access transistor, by gate-induced drain leakage at traps, by subthreshold leakage and through the dielectric; the cells in the retention tail are dominated by GIDL at traps (Weber et al.; background knowledge).
Mechanism, variable retention time: A cell switches at random between a high- and a low-retention state with exponentially distributed dwell times, often attributed to a trap that changes its charge state near the junction (Liu et al.; the trap attribution is background knowledge).
Mechanism, read disturbance: Device studies attribute RowHammer to trap-assisted electron migration from a neighbouring word line and to the passing-gate effect, and RowPress to the long open time of an aggressor row; measurements on real chips disagree with some of these predictions (Luo et al.).
Mechanism, SRAM: NBTI raises the pMOSFET threshold and PBTI the high-k nMOSFET threshold, which lowers the read static noise margin (SNM) and widens its spread; the discrete number of traps per small transistor gives a long tail of shifts (Asenov et al.; Duan et al.).
What sets the rate: The temperature, with the retention halving every 11 to 14 $K$ (Liu et al.); the cell scaling, with the minimum hammer count down by more than ten times from DDR3 to LPDDR4 (Kim et al.); the trap density and the transistor area for SRAM (Asenov et al.).
Failure criterion: A cell whose retention falls below the refresh interval (Liu et al.); the first bit flip at a hammer count within one refresh window (Kim et al.); a read SNM below zero or below a target such as 180 $mV$ (Asenov et al.; Duan et al.).

2. Where to Look

Location: The storage-node junction and the access-transistor drain under the word line for retention (Weber et al.); rows adjacent to frequently activated rows, at both true and anti cells (Luo et al.); the pull-up pMOSFETs and the pull-down nMOSFETs of the SRAM cell (Asenov et al.).
Signature: Retention fails that appear and disappear between identical tests (VRT, Liu et al.); bit flips that depend on the data pattern and on the hammer count, with both 1-to-0 and 0-to-1 flips in the same victim row (Kim et al.; Luo et al.); a shift of the SNM distribution and a wider tail after stress (Asenov et al.).
Confirm with: Repeated retention tests with several data patterns and long profiling times (Liu et al.); hammer-count sweeps within the refresh window at fixed temperature (Kim et al.); fast measurements of the threshold shift within microseconds of the end of the stress, since BTI recovers (Duan et al.).
Look-alikes: A single retention test with a fixed pattern, which can miss most weak cells (Liu et al.); particle-induced soft errors, which are random in place and time and do not need an aggressor row (see the Radiation page); a slow BTI measurement that misses the upper envelope and underestimates the SRAM loss (Duan et al.).

3. Prevention

Design: Keep the refresh interval with a guard band for the hot worst case, at least two times at 85 $^{\circ} C$ in the chips of Liu et al.; size SRAM transistors and the supply for the aged worst-case SNM, which needed 1.38 instead of 0.9 $V$ in the Duan et al. example.
Material and process: Passivate traps at the storage-node junction, for example with a fluorine implant (Weber et al.); reduce the trap density of the gate stack against NBTI and PBTI (Asenov et al.; Duan et al.).
Operation: Refresh faster at high temperature (Liu et al.); use error correction, which raised the first-flip hammer count by up to 2.78 times but cannot stop multi-bit flips in one word (Kim et al.); limit row activations per refresh window (Kim et al.).
Screening and test: Profile retention online and with several patterns, since VRT cells can hide for hours (Liu et al.; Mutlu); characterize read disturbance per chip generation, since the minimum hammer count differs by manufacturer and node (Kim et al.).

DRAM Retention

Name	Formula	Related Formulae	Variables/Constants
Retention time of a DRAM cell	$t_{r e t} = \frac{C _{S} Δ V _{cr i t}}{I _{L}}$	$I_{L} = I_{J} + I_{G I D L} + I_{s u b} + I_{d i e l}$	$t_{r e t} : r e t e n t i o n t im e$ $C_{S} : s t or a g e c a p a c i t an ce$ $Δ V_{cr i t} : l oss o f t h e s t or e d v o l t a g e t ha t t h e se n se am pl i f i er c an s t i l l r eso l v e$ $I_{L} : t o t a l l e ak a g e o f t h e s t or a g e n o d e$ $I_{J} : j u n c t i o n (g e n er a t i o n) l e ak a g e$ $I_{G I D L} : g a t e - in d u ce d d r ain l e ak a g e$ $I_{s u b} : s u b t h r es h o l d l e ak a g e o f t h e a ccess t r an s i s t or$ $I_{d i e l} : l e ak a g e t h r o ug h t h e c a p a c i t or d i e l ec t r i c (ba c k g r o u n d k n o w l e d g e; d e v i ce p a g e o n t h e D R A M p a g e); W e b er e t a l . : G I D L i s t h e d o minan t l e ak a g e o f t h e ce l l s in t h e r e t e n t i o n t ai l, an d a f l u or in e im pl an t in t o so u r ce an d d r ain t ha t p a ss i v a t es t r a p s c u t t h e f ai l co u n t b y u p t o 40 p er ce n t in 110 nm 512 Mbit an d 1 G bi t D R A M s; L ee an d L ee (2002, ab s t r a c t r e a d) : t h e se n se - am pl i f i er se n s i t i v i t y s t r o n g l y s ha p es t h e t ai l o f t h e r e t e n t i o n d i s t r ib u t i o n$ $(co m p u t e d : f or C_{S} = 10 fF an d Δ V_{cr i t} = 0.5 V (a ss u m e d), a 64 ms r e f r es h t o l er a t es 78 fA an d t h e 1.5 s minim u m r e t e n t i o n o f L i u e t a l . cor r es p o n d s t o 3.3 fA)$
Temperature scaling of the retention time	$t_{r e t} (T) = A e^{- b T} + C$	$\frac{t _{r e t} ( T + Δ T )}{t _{r e t} ( T )} \approx e^{- b Δ T}, Δ T_{1/2} = \frac{l n 2}{b}$	$t_{r e t} : r e t e n t i o n t im e$ $T : t e m p er a t u r e in^{\circ} C, A$ $C : f i t co n s t an t s$ $b : t e m p er a t u r e coe f f i c i e n t$ $Δ T_{1/2} : t e m p er a t u r e r i se t ha t ha l v es t h e r e t e n t i o n; L i u e t a l . (248 D D R 3 c hi p s o f f i v e v e n d or s, 50 t o 70^{\circ} C f i t) : b = 0.0498 K^{- 1} f or t h e co mm o n ce l l s an d 0.0625 K^{- 1} f or t h e w or s t - c a se t ai l, a l oss o f 39.2 an d 46.5 p er ce n t p er 10 K, n o ce l l b e l o w 1.5 s a t 45^{\circ} C, an d 1.5 s cor r es p o n d s t o ab o u t 126 ms a t 85^{\circ} C, a g u a r d ban d o f a t l e a s t tw o a g ain s t 64 ms$ $(co m p u t e d : Δ T_{1/2} = 13.9 an d 11.1 K; f r o m 45 t o 85^{\circ} C t h e t ai l f a c t or e^{- 2.5} = 0.082 g i v es 123 ms f or 1.5 s, c l ose t o t h e p a p e r^{'} s 126 ms, an d 0.50 s f or 6.1 s)$
Equivalent activation energy of the retention	$E_{a} \approx b k_{B} T^{2}$	$t_{r e t} \propto e^{E_{a} / (k_{B} T)} \Rightarrow - \frac{d l n t _{r e t}}{d T} = \frac{E _{a}}{k _{B} T ^{2}}$	$E_{a} : a pp a r e n t a c t i v a t i o n e n er g y o f t h e l e ak a g e$ $b : t e m p er a t u r e coe f f i c i e n t o f t h e e x p o n e n t ia l f i t$ $k_{B} : B o l t z mann co n s t an t (8.617 \times 1 0^{- 5} eV / K)$ $T : ab so l u t e t e m p er a t u r e; t h e co n v er s i o n i s m y d er i v a t i o n f r o m t h e A r r h e ni u s f or m an d h o l d s n e a r t h e f i t t e m p er a t u r e; W e b er e t a l . u se d a c t i v a t i o n e n er g i es o f s in g l e ce l l s t o co n f i r m t ha t t ai l ce l l s a r e G I D L (t r a p) d o mina t e d (v a l u es n o t in t h e ab s t r a c t)$ $(co m p u t e d : a t 60^{\circ} C (333 K) b = 0.0498 g i v es 0.48 eV an d b = 0.0625 g i v es 0.60 eV; a t 45^{\circ} C 0.43 an d 0.55 eV)$
Variable retention time and profiling coverage	$P_{mi ss} = e^{- T_{p} / τ_{H}}$	$f_{L} = \frac{τ _{L}}{τ _{L} + τ _{H}}$	$P_{mi ss} : p r o babi l i t y t ha t a V R T ce l l t ha t s t a r t s in i t s hi g h - r e t e n t i o n s t a t e d oes n o t s h o w i t s l o w s t a t e d u r in g a p r o f i l in g t im e T_{p}$ $τ_{H} an d τ_{L} : m e an d w e l l t im es in t h e hi g h an d l o w s t a t es (e x p o n e n t ia l l y d i s t r ib u t e d, L i u e t a l .)$ $f_{L} : l o n g - r u n f r a c t i o n o f t im e in t h e l o w s t a t e; L i u e t a l . : V R T i s u bi q u i t o u s, 87 p er ce n t o f t h e f ai l in g ce l l s o n a v er a g e (ab o v e 75 p er ce n t in e v er y d e v i ce) a l so p a sse d a t l e a s t o n e r o u n d a t 6.2 s, so m e ce l l s m o v e d f r o m ab o u t 1.5 s t o ab o v e 6.1 s, m or e t han f o u r t im es, d w e l l t im es r e a c h e d ab o u t 15000 s an d so m e ce l l s s t a y e d c l ose t o t h e o n e - d a y t es t l e n g t h; a s in g l e s t a t i c d a t a p a tt er n mi sse d u p t o ab o u t 90 p er ce n t o f f ai l u r es in o n e f ami l y an d n o s t a t i c p a tt er n e x cee d e d 30 p er ce n t co v er a g e in tw o f ami l i es; M u tl u : r e t e n t i o n b e ha v i o u r i s g e tt in g w or se w i t h sc a l in g, an d E C C an d o n l in e p r o f i l in g a r e t h e r e m e d i es$ $(co m p u t e d : f or τ_{H} = 15000 s (a ss u m e d f r o m t h e d w e l l t im es), P_{mi ss} = 0.79 f or o n e h o u r, 0.38 f or f o u r h o u r s an d 0.003 f or o n e d a y o f p r o f i l in g)$

DRAM Read Disturbance (RowHammer)

Name	Formula	Related Formulae	Variables/Constants
Activations available within a refresh window	$N_{a c t, ma x} = \frac{t _{R E F W}}{t _{R C}}$	$t_{hamm er} = 2 H C_{f i r s t} t_{R C} (double-sided)$	$N_{a c t, ma x} : a c t i v a t i o n s t ha t o n e bank c an p er f or m in a r e f r es h w in d o w$ $t_{R E F W} : r e f r es h w in d o w (64 ms)$ $t_{R C} : r o w cy c l e t im e (52.5 ns D D R 3, 50 ns D D R 4, 60 ns L P D D R 4, K im e t a l .)$ $t_{hamm er} : t im e t o r e a c h t h e f i r s t f l i p$ $H C_{f i r s t} : hamm er co u n t p er a g g r essor r o w a t t h e f i r s t bi t f l i p; K im e t a l . (1580 c hi p s) : H C_{f i r s t} p er man u f a c t u r er o f 69.2 t o 157 k f or D D R 3 - o l d, 22.4 t o 85 k f or D D R 3 - n e w, 17.5 t o 87 k f or D D R 4 - o l d, 10 t o 40 k f or D D R 4 - n e w, 16.8 t o 43.2 k f or L P D D R 4 - 1 x an d 4.8 t o 9.6 k f or L P D D R 4 - 1 y, a t 50^{\circ} C; t h e f i r s t R o w H amm er s t u d y (K im e t a l ., 2014) r e p or t e d 139 k (ba c k g r o u n d k n o w l e d g e)$ $(co m p u t e d : 1.28 \times 1 0^{6} a c t i v a t i o n s p er 64 ms a t 50 ns an d 1.07 \times 1 0^{6} a t 60 ns; t h e 4.8 k L P D D R 4 - 1 y c hi p f l i p s a f t er 0.58 ms o f d o u b l e - s i d e d hamm er in g, u n d er 1 p er ce n t o f t h e w in d o w; t h e l o w es t H C_{f i r s t} f e l l b y 14 t im es f r o m t h e D D R 3 - o l d minim u m o f 69.2 k)$
Bit-flip count against hammer count	$lo g N_{f l i p} = lo g a + m lo g H C$	$H C_{f i r s t, E C C} = k_{E C C} H C_{f i r s t}$	$N_{f l i p} : n u mb er o f bi t f l i p s$ $a : p r e f a c t or$ $m : s l o p e o n l o g - l o g a x es$ $H C : hamm er co u n t$ $H C_{f i r s t, E C C} : f i r s t u n cor r ec t ab l e f l i p w i t h er r or cor r ec t i o n$ $k_{E C C} : im p r o v e m e n t f a c t or; K im e t a l . : l o g N_{f l i p} g r o w s l in e a r l y w i t h l o g H C (O b ser v a t i o n 4), n e w er D D R 4 n o d es f l i p m or e a t t h e s am e H C, s in g l e - er r or - cor r ec t in g E C C r ai ses H C_{f i r s t} b y u p t o 2.78 t im es in D D R 4 an d 1.65 t im es in D D R 3 - n e w, a t a f l i p r a t e o f 1 \times 1 0^{- 6} o n e 64 - bi t w or d c an h o l d u p t o f o u r f l i p s, an d L P D D R 4 ha s o n - d i e E C C t ha t c ann o t b e d i s ab l e d$ $(co m p u t e d : 2.78 x 10 k = 27.8 k f or t h e w e ak es t D D R 4 - n e w man u f a c t u r er, s t i l l f a r b e l o w t h e 1.28 \times 1 0^{6} a c t i v a t i o n s o f o n e w in d o w)$

SRAM Stability under BTI

Name	Formula	Related Formulae	Variables/Constants
Threshold shift from interface traps	$Δ V_{T H} = \frac{q Δ N _{i t}}{C _{o x}}, C_{o x} = \frac{ε _{o x}}{t _{o x}}$	$\overset{n}{ˉ}_{t r} = N_{i t} W L$	$Δ V_{T H} : m e an t h r es h o l d s hi f t$ $q : e l e m e n t a r y c ha r g e$ $Δ N_{i t} : a dd e d in t er f a ce - t r a p d e n s i t y$ $C_{o x} : o x i d e c a p a c i t an ce p er a r e a$ $ε_{o x} : o x i d e p er mi tt i v i t y (3.9 ε_{0} f or S i O 2)$ $t_{o x} : o x i d e t hi c k n ess$ $\overset{n}{ˉ}_{t r} : m e an n u mb er o f t r a p s in o n e t r an s i s t or (P o i sso n d i s t r ib u t e d)$ $W L : g a t e a r e a (ba c k g r o u n d k n o w l e d g e; B T I k in e t i cs o n t h e C M O S L o g i c T r an s i s t or s p a g e); A se n o v e t a l . (45 nm L P, 42 x 42 nm d e v i ces, 1.7 nm S i O 2) : t r a p d e n s i t i es o f 1 \times 1 0^{11}, 5 \times 1 0^{11} an d 1 \times 1 0^{12} c m^{- 2} g i v e 4.5, 22.5 an d 45 t r a p s in 4500 n m^{2}, t h e pM O S F E T ∣ V_{T H} ∣ r i ses f r o m 0.23 t o 0.32 V an d i t s s p r e a d f r o m 55 t o 68 mV a t 1 \times 1 0^{12} c m^{- 2}, t h e n M O S F E T f r o m 0.22 t o 0.30 V an d f r o m 57 t o 65 mV, an d o n e pM O S F E T s hi f t e d b y ab o u t 140 mV a g ain s t an a v er a g e o f ab o u t 40 mV$ $(co m p u t e d : C_{o x} = 2.03 \times 1 0^{- 6} F/c m^{2} f or 1.7 nm, so 1 \times 1 0^{12} c m^{- 2} g i v es 79 mV, 5 \times 1 0^{11} c m^{- 2} 39 mV an d 1 \times 1 0^{11} c m^{- 2} 7.9 mV; t h e s im u l a t e d m e an s hi f t s o f 80 t o 90 mV ma t c h)$
Read-failure probability of an SRAM cell	$P_{f} = Φ (- \frac{μ _{S N M}}{σ _{S N M}})$	$N_{f ai l} = P_{f} N_{bi t s}$	$P_{f} : p r o babi l i t y t ha t a ce l l ha s a n e g a t i v e s t a t i c n o i se ma r g in (r e a d u p se t)$ $Φ : s t an d a r d n or ma l c u m u l a t i v e d i s t r ib u t i o n$ $μ_{S N M} an d σ_{S N M} : m e an an d s p r e a d o f t h e r e a d S N M$ $N_{f ai l} : e x p ec t e d f ai l in g ce l l s$ $N_{bi t s} : a r r a y s i z e (G a u ss ian t ai l a ss u m e d, ba c k g r o u n d k n o w l e d g e); A se n o v e t a l . (6 T ce l l, ce l l r a t i o 2, 1000 M o n t e C a r l o ce l l s) : f r es h S N M 0.116 V w i t h 24 mV s p r e a d, 0.093 V an d 25 mV a f t er N B T I a l o n e (ab o u t 20 p er ce n t l o w er), an d 0.114 V an d 30 mV a f t er N B T I an d P B T I t o g e t h er, b ec a u se P B T I o f t h e n M O S F E T s r es t or es t h e n / p ba l an ce b u t a dd s s p r e a d (m y r e a d in g); N B T I h e l p s t h e w r i t e an d h u r t s t h e r e a d$ $(co m p u t e d : μ / σ = 4.83, 3.72 an d 3.80, so P_{f} = 6.7 \times 1 0^{- 7}, 1.0 \times 1 0^{- 4} an d 7.2 \times 1 0^{- 5}, t ha t i s 0.7, 104 an d 76 f ai l in g ce l l s p er 1 Mbit (2^{2} 0 bi t s))$
Supply voltage needed to keep the SNM after BTI	$V_{D D, r e q} (t) = V_{D D, r e q} (0) + Δ V_{N B T I} (t) + Δ V_{P B T I} (t)$	$\frac{Δ V _{P B T I}}{Δ V _{N B T I} + Δ V _{P B T I}}$	$V_{D D, r e q} : s u ppl y a t w hi c h t h e ce l l k ee p s a t a r g e t S N M$ $Δ V_{N B T I} an d Δ V_{P B T I} : in cr e a ses c a u se d b y t h e u pp er - e n v e l o p e (w or s t) B T I s hi f t s o f t h e pM O S F E T s an d n M O S F E T s; D u an e t a l . (H f O 2/ A l 2 O 3, E O T 1.45 nm, 50 x 90 nm d e v i ces, \pm 1.4 V a t 125^{\circ} C f or 1000 s, 56 pM O S F E T s an d 45 n M O S F E T s) : f or S N M = 180 mV in a s im u l a t e d 45 nm ce l l, ab o u t 0.9 V f r es h, 1.2 V w i t h t h e N B T I u pp er e n v e l o p e an d 1.38 V w i t h b o t h, t h e N B T I m e an u pp er - e n v e l o p e s hi f t i s ab o u t f i v e t im es t h e P B T I o n e a t 1000 s, P B T I ha s t h e l a r g er r e l a t i v e s p r e a d an d g i v es a l a r g er S N M l oss f or t h e s am e s hi f t, P B T I i s r o ug h l y a q u a r t er o f t h e co mbin e d S N M r e d u c t i o n, an d t h e u pp er e n v e l o p e i s m or e t han tw i ce t h e l o w er e n v e l o p e, so t h e w or s t - c a se (c ha r g in g) v a l u e m u s t b e m e a s u r e d, w i t h a 3 μ s se n s in g r am p$ $(co m p u t e d : t h e s u ppl y m u s t r i se b y 0.30 V f or N B T I an d 0.48 V f or b o t h, o f w hi c h P B T I i s 37.5 p er ce n t o f t h e s u ppl y in cr e a se)$

Important Questions

Ques: How fast does DRAM retention fall with temperature, and is a 64 ms refresh enough at 85 degrees Celsius?

Liu et al. measured 248 DDR3 chips from five vendors and fitted the retention as $A e^{- b T} + C$ , with $b = 0.0498$ per kelvin for the common cells and 0.0625 for the worst-case tail. The retention therefore halves every 13.9 and 11.1 $K$ (computed). No cell failed below 1.5 $s$ at 45 $^{\circ} C$ , and scaling the tail to 85 $^{\circ} C$ gives about 126 $ms$ in the paper and 123 $ms$ with $e^{- 2.5}$ (computed), a guard band of about two over 64 $ms$ . Above 85 $^{\circ} C$ this margin is lost, which is why DRAM refreshes twice as fast in the extended range (background knowledge). Lee and Lee show that the sense amplifier also shapes the tail, so the margin is a property of the chip, not of the cell alone. Reference: J. Liu, B. Jaiyen, Y. Kim, C. Wilkerson and O. Mutlu, ‘An Experimental Study of Data Retention Behavior in Modern DRAM Devices: Implications for Retention Time Profiling Mechanisms’, Proc. ISCA 2013 (fetch-tool summary); G.-H. Lee and G.-Y. Lee, ‘Distribution Characteristics of Data Retention Time Considering the Probability Distribution of Cell Parameters in DRAM’, Journal of the Institute of Electronics Engineers of Korea SD 39(4), 1-9 (2002) (abstract only).

Ques: Do the tail cells of a DRAM have a lower or a higher activation energy than the main cells?

The sources point in different directions. Converting Liu et al.’s fits with $E_{a} \approx b k_{B} T^{2}$ gives 0.48 $eV$ for the common cells and 0.60 $eV$ for the tail at 60 $^{\circ} C$ (computed, my conversion), so the tail is more temperature sensitive. Weber et al. state that tail cells are dominated by GIDL at traps, and field-assisted tunnelling through traps is usually described with a lower activation energy than generation in the depletion region (background knowledge). The two can be reconciled if the worst cells at 50 to 70 $^{\circ} C$ are not the same cells as at low temperature (my reading). For a refresh design the measured worst-case coefficient of Liu et al. is the more reliable value, since it comes from real chips. Reference: J. Liu, B. Jaiyen, Y. Kim, C. Wilkerson and O. Mutlu, ‘An Experimental Study of Data Retention Behavior in Modern DRAM Devices: Implications for Retention Time Profiling Mechanisms’, Proc. ISCA 2013 (fetch-tool summary); A. Weber, A. Birner and W. Krautschneider, ‘Retention tail improvement for Gbit DRAMs through trap passivation confirmed by activation energy analysis’, Proc. ESSDERC 2006, 250-253 (abstract only).

Ques: Why can a single retention test not find all weak DRAM cells?

Because of variable retention time and data-pattern dependence. Liu et al. found that VRT is ubiquitous: on average 87 per cent of the failing cells, and over 75 per cent in every device, also passed at least one test round at 6.2 $s$ , and some cells moved by more than four times between states. The dwell times are exponential and reached about 15 000 $s$ , so a cell in its high state for that mean time escapes one hour of profiling with probability 0.79 and one day with 0.003 (computed). In addition, all-0 and all-1 patterns missed about 90 per cent of failures in one family, and no static pattern covered more than 30 per cent in two families, because neighbouring cells change the leakage. Mutlu therefore recommends ECC with online profiling. Reference: J. Liu, B. Jaiyen, Y. Kim, C. Wilkerson and O. Mutlu, ‘An Experimental Study of Data Retention Behavior in Modern DRAM Devices: Implications for Retention Time Profiling Mechanisms’, Proc. ISCA 2013 (fetch-tool summary); O. Mutlu, ‘Retrospective: An Experimental Study of Data Retention Behavior in Modern DRAM Devices’, arXiv:2306.16037 (2023) (fetch-tool summary).

Ques: How few activations can cause a RowHammer bit flip in modern DRAM?

Kim et al. tested 1580 DDR3, DDR4 and LPDDR4 chips at 50 $^{\circ} C$ . The minimum hammer count per aggressor row fell from 69.2 to 157 k in old DDR3, by manufacturer, to 4.8 to 9.6 k in LPDDR4-1y, a drop of 14 times for the weakest chip from the old DDR3 minimum (computed). The first RowHammer study of 2014 reported 139 k (background knowledge). With a 60 $ns$ row cycle, 4.8 k double-sided hammers take 0.58 $ms$ , while a 64 $ms$ window allows about $1.07 \times 1 0^{6}$ activations (computed), so the refresh alone cannot protect the cell. The number of flips grows linearly on log-log axes with the hammer count, and newer nodes flip more at the same count, so the problem worsens as cells shrink and couple more strongly. Reference: J. S. Kim, M. Patel, A. G. Yaglikci, H. Hassan, R. Azizi, L. Orosa and O. Mutlu, ‘Revisiting RowHammer: An Experimental Analysis of Modern DRAM Devices and Mitigation Techniques’, Proc. ISCA 2020 (arXiv:2005.13121, fetch-tool summary).

Ques: Do device simulations explain the direction of RowHammer bit flips?

Not fully. Device-level studies attribute double-sided RowHammer to trap-assisted electron migration helped by the passing gate, which predicts only 1-to-0 flips, and single-sided RowPress to the long open time of the aggressor, which predicts flips in both directions. Luo et al. tested 96 DDR4 chips from three manufacturers and found the opposite pattern: both directions appear in the same victim row under double-sided RowHammer, and 0-to-1 flips appear first, at a hammer count 24.7 per cent lower on average, while single-sided RowPress at 80 $^{\circ} C$ and 7.8 $μ s$ open time gave almost only 1-to-0 flips. The authors leave open whether the device models miss a leakage path or whether the usual true-cell and anti-cell mapping is wrong. The measured chip data are the safer basis for a design (my reading). Reference: H. Luo, I. E. Yueksel, A. Olgun, A. G. Yaglikci and O. Mutlu, ‘Revisiting DRAM Read Disturbance: Identifying Inconsistencies Between Experimental Characterization and Device-Level Studies’, arXiv:2503.16749v2 (2025) (fetch-tool summary).

Ques: Does error correction solve RowHammer?

It helps but does not solve it. Kim et al. found that single-error-correcting ECC raises the first uncorrectable hammer count by up to 2.78 times in DDR4 and 1.65 times in DDR3-new chips, with diminishing returns for stronger codes in DDR4. At a flip rate of $1 \times 1 0^{- 6}$ , however, one 64-bit word can hold up to four flips, beyond any single-error code. For the weakest DDR4-new manufacturer, 2.78 times 10 k is 27.8 k (computed), still far below the roughly $1.28 \times 1 0^{6}$ activations possible in one 64 $ms$ window at 50 $ns$ (computed). LPDDR4 has on-die ECC that cannot be disabled, so its measured hammer counts already include it. ECC must therefore be combined with limits on the activations of a row between refreshes. Reference: J. S. Kim, M. Patel, A. G. Yaglikci, H. Hassan, R. Azizi, L. Orosa and O. Mutlu, ‘Revisiting RowHammer: An Experimental Analysis of Modern DRAM Devices and Mitigation Techniques’, Proc. ISCA 2020 (arXiv:2005.13121, fetch-tool summary).

Ques: How do interface traps from BTI reduce the read stability of an SRAM cell?

Asenov et al. simulated 45 $nm$ cells with 42 by 42 $nm$ transistors and 1.7 $nm$ SiO2. A trap density of $1 \times 1 0^{12}$ $c m^{- 2}$ means only about 45 traps per transistor, Poisson distributed, so the shifts are discrete and vary strongly: the pMOSFET threshold rose on average from 0.23 to 0.32 $V$ , its spread from 55 to 68 $mV$ , and one device shifted by 140 $mV$ against an average of 40 $mV$ . The simple estimate $q Δ N_{i t} / C_{o x}$ gives 79 $mV$ (computed), consistent with the mean shift. With NBTI alone the mean read SNM fell by about 20 per cent, from 0.116 to 0.093 $V$ , because the weaker pull-up worsens the n/p balance. NBTI helps the write and hurts the read. Reference: A. Asenov, A. R. Brown and B. Cheng, ‘Statistical aspects of NBTI/PBTI and impact on SRAM yield’, Proc. DATE 2011 (fetch-tool summary); CMOS Logic Transistors page of this vault.

Ques: Is the SRAM hurt more by the mean SNM loss or by its spread?

By both, and PBTI changes the balance. In Asenov et al. NBTI alone lowered the mean SNM from 0.116 to 0.093 $V$ , while NBTI and PBTI together left the mean at 0.114 $V$ but widened the spread from 24 to 30 $mV$ . With a Gaussian tail, the read-failure probabilities are $6.7 \times 1 0^{- 7}$ fresh, $1.0 \times 1 0^{- 4}$ after NBTI and $7.2 \times 1 0^{- 5}$ after both, or about 0.7, 104 and 76 failing cells per megabit (computed). The spread therefore matters almost as much as the mean shift. Duan et al. add that PBTI has the larger relative device-to-device variation and gives a larger SNM loss for the same shift, and that it accounts for roughly a quarter of the combined SNM reduction. A yield model must therefore use the full distribution, not the average shift. Reference: A. Asenov, A. R. Brown and B. Cheng, ‘Statistical aspects of NBTI/PBTI and impact on SRAM yield’, Proc. DATE 2011 (fetch-tool summary); M. Duan, J. F. Zhang, Z. Ji, W. Zhang, B. Kaczer, T. Schram, R. Ritzenthaler, G. Groeseneken and A. Asenov, ‘Development of a technique for characterizing bias temperature instability-induced device-to-device variation at SRAM-relevant conditions’, IEEE Transactions on Electron Devices (2014 accepted manuscript, LJMU repository; journal details not in the copy read, fetch-tool summary).

Ques: How much extra supply voltage does an aged SRAM cell need?

In Duan et al.’s simulated 45 $nm$ cell, keeping an SNM of 180 $mV$ needed about 0.9 $V$ fresh, 1.2 $V$ with the worst-case NBTI shifts and 1.38 $V$ with NBTI and PBTI together, an increase of 0.48 $V$ (computed). These shifts came from 1000 $s$ of stress at $\pm 1.4$ $V$ and 125 $^{\circ} C$ on HfO2 devices. The key point of the paper is the measurement: the upper envelope of the shift, captured by a fast trip-point method with a 3 $μ s$ ramp and sampling of at least 1 MS/s, was more than twice the lower envelope. A slow measurement lets the traps discharge and underestimates the loss, so the required supply would be set too low. Real products limit this with guard bands on $V_{min}$ and with aging-aware design (background knowledge). Reference: M. Duan, J. F. Zhang, Z. Ji, W. Zhang, B. Kaczer, T. Schram, R. Ritzenthaler, G. Groeseneken and A. Asenov, ‘Development of a technique for characterizing bias temperature instability-induced device-to-device variation at SRAM-relevant conditions’, IEEE Transactions on Electron Devices (2014 accepted manuscript, LJMU repository; journal details not in the copy read, fetch-tool summary).

Quartz 5

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Static and Dynamic Random Access Memory (SRAM and DRAM)