Static Random Access Memory (SRAM)

1. Theory

Definition: Static random access memory (SRAM) stores each bit in a bistable latch that holds its state as long as power is applied, with no refresh.
6T cell: Two cross-coupled CMOS inverters (PMOS pull-ups and NMOS pull-downs) form the latch, and two NMOS access transistors connect the storage nodes to the bitlines.
Bistability: The latch has two stable states only while the loop gain exceeds one.
Cell ratio ( $β$ ): The pull-down to access transistor strength ratio; a large $β$ keeps a read from flipping the cell.
Pull-up ratio ( $γ$ ): The pull-up to access transistor strength ratio; a small $γ$ lets the bitline overpower the cell during a write.
Static noise margin (SNM): The side of the largest square that fits in the smaller lobe of the butterfly curve, i.e. the largest DC noise the cell tolerates.
8T and 10T cells: Extra transistors add a separate read port so reads do not disturb the storage nodes.

2. Working Principle

Hold: With the wordline low, the cross-coupled inverters regenerate the stored value, drawing only leakage current.
Read: Both bitlines are precharged high; the wordline opens the access transistors and the 0-node side pulls its bitline down, while the 0 node rises slightly (read disturb).
Write: The bitlines are driven to opposite values and the access transistor pulls the 1 node below the opposite inverter’s trip point, flipping the latch.
Read-write conflict: Sizing trades read stability (large $β$ ) against writability (small $γ$ ), typically $β \approx 1.5$ to $2$ and $γ < 1$ .
Minimum supply voltage: Threshold mismatch between the six transistors raises the practical retention and operating voltage to a few hundred millivolts.
FinFET sizing: Fin quantization removes continuous sizing, so assist circuits or 8T cells recover margin.
Soft errors: Particle strikes can flip the cell when the collected charge exceeds the critical charge $Q_{cr i t} \approx C_{n o d e} V_{D D}$ .

3. Applications

CPU and GPU caches: L1, L2 and L3 caches and register files, where the fastest access is needed.
On-chip buffers in SoCs and accelerators: Scratchpad memory in AI accelerators, network switches and DSPs.
FPGA configuration and block RAM: Configuration bits and embedded memory blocks.

Name	Formula	Related Formulae	Variables/Constants
Inverter switching threshold (trip point)	$V_{M} = \frac{V _{T n} + r ( V _{D D} + V _{T p} )}{1 + r}$	$r = \frac{k _{p}}{k _{n}} = \frac{μ _{p} C _{o x} ( W / L ) _{p}}{μ _{n} C _{o x} ( W / L ) _{n}}$	$V_{M} : in p u t v o l t a g e a t w hi c h V_{o u t} = V_{in} (b o t h t r an s i s t or s in s a t u r a t i o n)$ $V_{T n}, V_{T p} : t h r es h o l d v o l t a g es o f t h e N M O S an d P M O S (V_{T p} < 0)$ $V_{D D} : s u ppl y v o l t a g e$ $k_{n}, k_{p} : t r an sco n d u c t an ce p a r am e t er s o f t h e N M O S an d P M O S$ $(l o n g - c hann e l s q u a r e - l a w m o d e l; v e l oc i t y s a t u r a t i o n s hi f t s t h e r es u l t)$
Bistability condition	$∣ A_{v} ∣ = \frac{g _{mn} + g _{m p}}{g _{d s n} + g _{d s p}} > 1$	$(small-signal gain of one inverter at V_{M})$	$A_{v} : s ma l l - s i g na l v o l t a g e g ain o f o n e in v er t er a t i t s t r i p p o in t$ $g_{mn}, g_{m p} : t r an sco n d u c t an ces o f t h e N M O S an d P M O S$ $g_{d s n}, g_{d s p} : o u tp u t co n d u c t an ces o f t h e N M O S an d P M O S$ $(t h e cr oss - co u pl e d p ai r ha s tw o s t ab l e s t a t es o n l y i f t h e l oo p g ain A_{v}^{2} e x cee d s 1)$
Cell ratio and pull-up ratio	$β = \frac{( W / L ) _{P D}}{( W / L ) _{A X}}$ $γ = \frac{( W / L ) _{P U}}{( W / L ) _{A X}}$	$β = \frac{N _{f in, P D}}{N _{f in, A X}} (FinFET cell)$	$β : ce l l (b e t a) r a t i o, w hi c h se t s r e a d s t abi l i t y$ $γ : p u l l - u p r a t i o, w hi c h se t s w r i t abi l i t y$ $(W / L)_{P D}, (W / L)_{P U}, (W / L)_{A X} : a s p ec t r a t i os o f t h e p u l l - d o w n N M O S, p u l l - u p P M O S an d a ccess N M O S$ $N_{f in} : n u mb er o f f in s p er t r an s i s t or, s in ce t h e w i d t h o f a F in F E T co m es in w h o l e f in s$
Read disturb voltage on the stored 0 node	$V_{R} = (V_{D D} - V_{T H}) [1 - \frac{β}{β + 1}]$	$\frac{( W / L ) _{A X}}{2} (V_{D D} - V_{R} - V_{T H})^{2} = (W / L)_{P D} [(V_{D D} - V_{T H}) V_{R} - \frac{V _{R}^{2}}{2}]$	$V_{R} : v o l t a g e t ha t r i ses o n t h e in t er na l n o d e s t or in g 0 w h e n b o t h bi tl in es a r e p r ec ha r g e d t o V_{D D} an d t h e w or d l in e i s hi g h$ $V_{T H} : t h r es h o l d v o l t a g e, t ak e n e q u a l f or t h e a ccess an d p u l l - d o w n N M O S$ $(a ccess N M O S in s a t u r a t i o n, p u l l - d o w n N M O S in t h e l in e a r r e g i o n, an d b o d y e f f ec t n e g l ec t e d)$ $(s t abi l i t y r e q u i r es V_{R} < V_{M} o f t h e o pp os i t e in v er t er, w hi c h m e an s β m u s t b e l a r g er t han 1)$
Read current	$I_{r e a d} = \frac{μ _{n} C _{o x}}{2} (\frac{W}{L})_{A X} (V_{D D} - V_{R} - V_{T H})^{2}$	$I_{r e a d} \approx \frac{μ _{n} C _{o x}}{2} (\frac{W}{L})_{A X} (V_{D D} - V_{T H})^{2} (for β ≫ 1)$	$I_{r e a d} : c u r r e n t d r a w n f r o m t h e p r ec ha r g e d bi tl in e t h r o ug h t h e a ccess an d p u l l - d o w n t r an s i s t or s in ser i es$ $V_{R} : r e a d d i s t u r b v o l t a g e f r o m t h e r o w ab o v e$ $(a l a r g er β r e d u ces V_{R} an d r ai ses I_{r e a d})$
Write node voltage	$V_{Q} = (V_{D D} - V_{T H}) [1 - 1 - \frac{μ _{p} ( W / L ) _{P U} ( V _{D D} - ∣ V _{T p} ∣ ) ^{2}}{μ _{n} ( W / L ) _{A X} ( V _{D D} - V _{T H} ) ^{2}}]$	$V_{Q} < V_{M} (write succeeds)$	$V_{Q} : v o l t a g e o f t h e n o d e s t or in g 1 w h e n i t s bi tl in e i s h e l d a t 0 V an d t h e w or d l in e i s hi g h$ $V_{T p} : P M O S t h r es h o l d v o l t a g e$ $μ_{n}, μ_{p} : e l ec t r o n an d h o l e m o bi l i t i es o f t h e N M O S an d P M O S$ $V_{M} : t r i p p o in t o f t h e o pp os i t e in v er t er$ $(p u l l - u p P M O S in s a t u r a t i o n an d a ccess N M O S in t h e l in e a r r e g i o n; t h e r es u l t r e q u i r es a s ma l l γ)$ $(V_{Q} < V_{M} i s a s im pl e s t a t i c t es t t ha t i g n or es t h e r e g e n er a t i v e f ee d ba c k o f t h e o pp os i t e in v er t er; t h e w r i t e ma r g in i s n or ma l l y t ak e n f r o m a bi tl in e v o l t a g e s w ee p)$
Static noise margin	$S N M = min (s_{1}, s_{2})$	$S N M_{h o l d} \approx \frac{V _{D D}}{2} (1 - \frac{1}{∣ A _{v} ∣})$	$S N M : l a r g es t D C n o i se v o l t a g e t ha t t h e ce l l t o l er a t es o n b o t h s t or a g e n o d es b e f or e t h e s t or e d s t a t e f l i p s$ $s_{1}, s_{2} : s i d e l e n g t h s o f t h e l a r g es t s q u a r es t ha t f i t in t h e tw o l o b es o f t h e b u tt er f l y c u r v e (t h e tw o in v er t er V T C s pl o tt e d a g ain s t e a c h o t h er)$ $S N M_{h o l d} : h o l d ma r g in f or a sy mm e t r i c ce l l w i t h p i ece w i se - l in e a r t r an s f er c u r v es o f g ain A_{v}$ $(r e a d S N M i s l o w er b ec a u se t h e bi tl in e l o a d s t h e 0 n o d e; w r i t e ma r g in i s t h e bi tl in e v o l t a g e a t w hi c h t h e ce l l f l i p s)$
Subthreshold inverter gain and data retention voltage	$∣ A_{v} ∣ = \frac{1}{n} (e^{V_{D D} /2 ϕ_{t}} - 1)$	$V_{D R V, min} = 2 ϕ_{t} ln (1 + n)$	$A_{v} : g ain o f a sy mm e t r i c s u b t h r es h o l d in v er t er a t V_{D D} /2$ $n : s u b t h r es h o l d s l o p e f a c t or o f t h e N M O S an d P M O S (e q u a l s l o p es, e q u a l I_{0} an d n o D I B L a ss u m e d; n \approx 1.2 t o 1.5 g i v es V_{D R V, min} \approx 40 t o 50 mV a t 300 K)$ $ϕ_{t} = k_{B} T / q : t h er ma l v o l t a g e$ $V_{D R V, min} : i d e a l l o w er b o u n d o n t h e d a t a r e t e n t i o n v o l t a g e, f o u n d b y se tt in g ∣ A_{v} ∣ = 1$ $(r e a l D R V i s hi g h er b ec a u se o f t h r es h o l d mi s ma t c h b e tw ee n t h e cr oss - co u pl e d t r an s i s t or s)$ $k_{B} : B o l t z mann co n s t an t$
Standby leakage current	$I_{ce l l} = I_{s u b} + I_{g a t e} + I_{G I D L} + I_{j u n c}$	$I_{s u b} = I_{0} \frac{W}{L} e^{(V_{GS} - V_{T H}) / n ϕ_{t}} (1 - e^{- V_{D S} / ϕ_{t}})$ $P_{s t b y} = V_{D D} I_{ce l l}$	$I_{ce l l} : t o t a l l e ak a g e c u r r e n t o f o n e ce l l in t h e h o l d s t a t e$ $I_{s u b} : s u b t h r es h o l d c u r r e n t o f t h e o f f t r an s i s t or s (o n e N M O S an d o n e P M O S p er in v er t er pl u s t h e a ccess t r an s i s t or s)$ $I_{g a t e}, I_{G I D L}, I_{j u n c} : g a t e t u nn e l l in g, g a t e - in d u ce d d r ain l e ak a g e an d j u n c t i o n l e ak a g e$ $I_{0} : t ec hn o l o g y - d e p e n d e n t c u r r e n t p r e f a c t or$ $P_{s t b y} : s t an d b y p o w er p er ce l l$
Threshold mismatch of the cell transistors	$σ_{V_{T H}} = \frac{A _{V T}}{W L}$	$σ_{S N M} \approx \sum_{i} (\frac{\partial S N M}{\partial V _{T H, i}})^{2} σ_{V_{T H, i}}^{2}$	$σ_{V_{T H}} : s t an d a r d d e v ia t i o n o f t h e t h r es h o l d v o l t a g e o f o n e t r an s i s t or$ $A_{V T} : P e l g r o m ma t c hin g coe f f i c i e n t o f t h e t ec hn o l o g y$ $W, L : g a t e w i d t h an d l e n g t h$ $σ_{S N M} : s t an d a r d d e v ia t i o n o f t h e s t a t i c n o i se ma r g in f r o m t h e s i x in d e p e n d e n t t h r es h o l d v a r ia t i o n s V_{T H, i}$ $(t h e s ma l l es t t r an s i s t or s in t h e ce l l d o mina t e t h e v a r ia t i o n; t h e l in e a r i z e d s u m h o l d s n e a r t h e m e an o n l y, an d t h e l o w - S N M t ai l t ha t se t s a r r a y y i e l d n ee d s M o n t e C a r l o or im p or t an ce s am pl in g)$
Critical charge and soft error rate	$S E R = K F A_{se n s} e^{- Q_{cr i t} / Q_{s}}$	$Q_{cr i t} \approx C_{n o d e} V_{D D}$	$S E R : so f t er r or r a t e p er ce l l$ $F : f l ux o f t h e i o ni z in g p a r t i c l es (n e u t r o n s, a l p ha p a r t i c l es)$ $A_{se n s} : a r e a o f t h e se n s i t i v e (r e v er se - bia se d d r ain) j u n c t i o n$ $Q_{cr i t} : s ma l l es t co l l ec t e d c ha r g e t ha t f l i p s t h e ce l l, w i t h C_{n o d e} t h e s t or a g e n o d e c a p a c i t an ce$ $Q_{s} : c ha r a c t er i s t i c co l l ec t e d c ha r g e, in co u l o mb s (c a l l e d t h e c ha r g e co l l ec t i o n e f f i c i e n cy b y H a z u c ha an d S v e n sso n); i t d e p e n d s o n d o p in g an d s u ppl y v o l t a g e$ $K : f i tt in g co n s t an t o f t h e t ec hn o l o g y$ $(Q_{cr i t} h er e i s t h e l e a d in g - or d er es t ima t e; t h e r es t or in g c u r r e n t o f t h e ce l l in cr e a ses i t)$

Important Questions

Ques: Why does an SRAM cell use six transistors, and what does each pair do?

A cell must hold one bit indefinitely while power is applied, so it uses two cross-coupled inverters (each a PMOS pull-up and an NMOS pull-down) that regenerate each other and give two stable states, as long as the loop gain $A_{v}^{2} > 1$ . Two NMOS access transistors connect the storage nodes to the bitlines when the wordline is high. The access transistors must be able to overpower the cell during a write but must not disturb it during a read, and this conflict is what the $β$ and $γ$ ratios control. Unlike DRAM the cell needs no refresh, but it holds a bit through static leakage paths that consume standby power. Reference: J.M. Rabaey, A. Chandrakasan and B. Nikolic, Digital Integrated Circuits, 2nd ed., Prentice Hall, 2003.

Ques: Why must the cell ratio be greater than one but the pull-up ratio small?

During a read, both bitlines are precharged high and the access transistor of the 0 node forms a voltage divider with the pull-down transistor, so the 0 node rises to $V_{R} = (V_{D D} - V_{T H}) [1 - β / (β + 1)]$ . The cell is stable only if $V_{R}$ stays below the trip point $V_{M}$ of the opposite inverter, which demands a strong pull-down (large $β$ ). During a write, the bitline pulls the 1 node down against the PMOS pull-up, and the node must fall below $V_{M}$ , which needs a weak pull-up (small $γ$ ). Sizing therefore trades read stability against writability, usually with $β \approx 1.5$ to 2 and $γ < 1$ . Reference: E. Seevinck, F.J. List and J. Lohstroh, “Static-noise margin analysis of MOS SRAM cells,” IEEE J. Solid-State Circuits 22, 748 (1987).

Ques: How is the static noise margin obtained from the butterfly curve?

The voltage transfer curve of one inverter is plotted together with the mirror image of the other inverter’s curve. The two curves cross at three points (two stable, one metastable) and enclose two lobes. The SNM is the side of the largest square that fits inside the smaller lobe, because that is the largest DC noise, applied in series with both nodes in the worst direction, that leaves the stored state intact. For read SNM the access transistors are connected to bitlines at $V_{D D}$ , which squeezes the lobes and reduces the margin below the hold SNM. Reference: E. Seevinck, F.J. List and J. Lohstroh, IEEE J. Solid-State Circuits 22, 748 (1987).

Ques: What are the 8T and 10T cells, and why are they used?

In the 6T cell the same access transistors serve for reads and writes, so a read disturbs the cell. In the 8T cell two additional transistors form a separate read port whose gate is connected to the storage node, so the read does not touch the storage nodes and the read SNM becomes equal to the hold SNM. Its read current is then set by the series stack of the read-access and read-buffer transistors instead of by $V_{R}$ . The 8T cell costs more area and needs a second bitline, but it works to a lower supply voltage. The 10T cell adds further devices to also remove the half-select disturb and the leakage on the read bitline. Reference: L. Chang et al., “Stable SRAM cell design for the 32 nm node and beyond,” Symp. VLSI Technology, 128 (2005); B.H. Calhoun and A.P. Chandrakasan, “A 256-kb 65-nm sub-threshold SRAM design for ultra-low-voltage operation,” IEEE J. Solid-State Circuits 42, 680 (2007).

Ques: What limits the minimum supply voltage of an SRAM cell?

The cell keeps its data only while the loop gain exceeds one. For a subthreshold inverter the gain is $(e^{V_{D D} /2 ϕ_{t}} - 1) / n$ , which falls to one at $V_{D D} = 2 ϕ_{t} ln (1 + n)$ , about 40 to 50 mV for an ideal symmetric cell with $n \approx 1.2$ to $1.5$ . In practice threshold mismatch between the six transistors (Pelgrom scaling $σ_{V_{T H}} = A_{V T} / W L$ ) moves the real retention voltage to a few hundred millivolts, and the read and write margins, which need more headroom than the hold margin, set the operating minimum. The ideal bound is the same minimum supply that R.M. Swanson and J.D. Meindl derived for the subthreshold CMOS inverter, and the data retention voltage of real cells was studied by Qin et al. Reference: R.M. Swanson and J.D. Meindl, “Ion-implanted complementary MOS transistors in low-voltage circuits,” IEEE J. Solid-State Circuits 7, 146 (1972); H. Qin, Y. Cao, D. Markovic, A. Vladimirescu and J. Rabaey, “SRAM leakage suppression by minimizing standby supply voltage,” Proc. ISQED, 55 (2004); A.J. Bhavnagarwala, X. Tang and J.D. Meindl, “The impact of intrinsic device fluctuations on CMOS SRAM cell stability,” IEEE J. Solid-State Circuits 36, 658 (2001); M.J.M. Pelgrom, A.C.J. Duinmaijer and A.P.G. Welbers, IEEE J. Solid-State Circuits 24, 1433 (1989).

Ques: How does scaling to FinFET and gate-all-around devices change SRAM sizing?

The width of a FinFET is quantized by the number of fins, so $β$ and $γ$ cannot be tuned continuously. Cells are named by their fin counts in the order pull-up, pass-gate, pull-down. The high-density 1-1-1 cell has $β = 1$ and a poor read margin; the 1-2-2 cell keeps $β = 1$ but doubles the read current, and only a cell with more pull-down than pass-gate fins (such as 1-2-3) raises $β$ above 1. Read and write assist circuits or an 8T cell are used to make up for the missing sizing freedom. The undoped fin body also reduces random dopant fluctuation, so $A_{V T}$ improves and the cell has less threshold variation than a planar cell of the same area. Nanosheet transistors allow continuous sheet width and restore some of the tuning. Reference: C.-H. Jan et al., “A 22nm SoC platform technology featuring 3-D tri-gate and high-k/metal gate, optimized for ultra low power, high performance and high density SoC applications,” IEDM Tech. Dig., 44 (2012).

Ques: What is a soft error, and why does it matter more at low supply voltage?

A soft error is a flip of the stored bit caused by charge generated by an ionizing particle (an alpha particle from packaging, or a secondary from a cosmic-ray neutron) that is collected by a reverse-biased drain junction of the off transistor on the storage node. The cell flips if the collected charge exceeds $Q_{cr i t} \approx C_{n o d e} V_{D D}$ . Scaling reduces both $C_{n o d e}$ and $V_{D D}$ , so $Q_{cr i t}$ falls, but the sensitive area also falls, so the rate per cell has stayed roughly constant while the rate per chip rises with array size. Reference: P. Hazucha and C. Svensson, “Impact of CMOS technology scaling on the atmospheric neutron soft error rate,” IEEE Trans. Nucl. Sci. 47, 2586 (2000).

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