Programmable Unijunction Transistor (PUT)

1. Theory

• Definition: A programmable unijunction transistor (PUT) is a small four-layer PNPN thyristor with an anode gate, used to imitate a UJT with an adjustable firing point.
• Terminals: Anode, cathode and an anode gate connected to the $N_1$ base.
• Programmable standoff ratio: The standoff ratio $\eta$ is set by an external two-resistor divider ($\eta =R_2/(R_1+R_2)$) rather than by a fixed bar geometry as in a UJT.
• Firing mechanism: The device fires by the regenerative PNPN latch of the SCR, not by conductivity modulation of a resistive bar.
• Gate resistance: The Thevenin resistance of the divider ($R_G$) sets the peak current $I_P$; a larger $R_G$ gives a smaller $I_P$.

2. Working Principle

• Off state: While the anode voltage is below the gate voltage plus one diode drop, $J_1$ is reverse biased and only leakage flows.
• Peak point: When the anode reaches $V_P=\eta V_S+V_D$, $J_1$ starts injecting holes and ${\alpha }_1$ rises.
• Latching: Once ${\alpha }_1+{\alpha }_2=1$, the PNPN structure latches and the anode voltage collapses to the low valley voltage.
• Negative resistance: Between the peak and valley points, anode voltage falls as current rises.
• Relaxation oscillation: A capacitor charges through $R_A$ to $V_P$, discharges through the PUT, and the cycle repeats with period $T\approx R_{A}C\ln \left[1/(1-\eta )\right]$.
• Low peak current: The very small $I_P$ allows large timing resistors and long periods with modest capacitors.

3. Applications

• Current status: Largely replaced by 555 timers, comparator circuits and microcontrollers.
• Remaining niche: Simple, very low-current long-period relaxation timers and SCR trigger-pulse generators in legacy designs.

Name	Formula	Related Formulae	Variables/Constants
Programmed standoff ratio and gate voltage	$\eta =\frac{R_2}{R_1+R_2},V_G=\eta V_S$	${\eta }_{UJT}=\frac{R_{B1}}{R_{B1}+R_{B2}}\text{(see Unijunction Transistor page)}$	$\begin{array}{r}\eta :programmedstandoffratio(any\\ valuebetween0and1)\end{array}$ $V_G:gatevoltagesetbythedivider$ $V_S:supplyvoltage$ $R_1,R_2:dividerresistors$
Gate source resistance	$R_G=\frac{R_1{R}_2}{R_1+R_2}=\eta R_1$	$R_G=(1-\eta )R_2$	$\begin{array}{r}{R}_G:Theveninresistanceseenbythe\\ gateterminal,whichalsosetsthepeak\\ current{I}_P(smaller{R}_{G}givesalarger\\ I_P)\end{array}$
Peak-point (firing) voltage	$V_P=V_G+V_D=\eta V_S+V_D$	$V_D\approx 0.5\text{–}0.7\mathrm{V}\text{(see PN Junction Diode page)}$	$\begin{array}{r}{V}_P:anodevoltageatwhich{J}_{1}becomes\\ forwardbiasedandthedevicebeginsto\\ latch\end{array}$ $V_D:forwardvoltageof{J}_1$
Regenerative turn-on after the peak point	${\alpha }_1+{\alpha }_2=1$	$\begin{array}{r}\text{(see}\text{Thyristor}\text{SCR}\text{/}\text{Silicon-Controlled}\\ \text{Switch}\text{pages)}\end{array}$	$\begin{array}{r}\text{(once}{J}_1\text{injects,}{\alpha }_1\text{rises}\text{with}\\ \text{current}\text{and}\text{the}\text{PNPN}\text{loop}\text{latches,}\\ \text{collapsing}\text{the}\text{anode}\text{voltage)}\end{array}$
Negative-resistance region	$\frac{d{V}_A}{d{I}_A}<0(I_P<I_A<I_V)$	$V_V<V_P,I_V>I_P$	$(V_P,I_P):peakpoint$ $(V_V,I_V):valleypoint$ $V_A,I_A:anodevoltageandcurrent$
Relaxation oscillator period	$T=R_{A}C\ln \left(\frac{V_S-V_V}{V_S-V_P}\right)\approx R_{A}C\ln \left(\frac{1}{1-\eta }\right)$	$f=\frac{1}{T}$	$\begin{array}{r}{R}_A,C:timingresistorandcapacitoron\\ theanode\end{array}$ $\begin{array}{r}\text{(approximation}\text{assumes}{V}_V\ll V_S\text{and}\\ V_D\ll \eta V_S\text{)}\end{array}$
Oscillation condition on the anode resistor	$\frac{V_S-V_V}{I_V}<R_A<\frac{V_S-V_P}{I_P}$	$\begin{array}{r}\text{(same}\text{load}\text{line}\text{condition}\text{as}\text{the}\text{UJT,}\\ \text{see}\text{Unijunction}\text{Transistor}\text{page)}\end{array}$	$\begin{array}{r}\text{(too}\text{large}\text{an}{R}_A\text{cannot}\text{supply}{I}_P;\\ \text{too}\text{small}\text{an}{R}_A\text{supplies}\text{more}\text{than}{I}_V\\ \text{so}\text{the}\text{device}\text{stays}\text{latched)}\end{array}$

Important Questions

Ques: How does a PUT differ physically from a UJT if both are described by the same peak-point and oscillator equations?

The equations look the same because both devices have a voltage-threshold firing point and a negative-resistance region, but the mechanisms are different. A UJT is a resistive n-type bar whose built-in divider ($\eta$) is set by geometry, and its negative resistance comes from conductivity modulation as injected holes lower $R_{B1}$ (see the Unijunction Transistor page). A PUT is a four-layer PNPN device: the external gate divider sets $V_G=\eta V_S$, and when the anode exceeds $V_G+V_D$ the $J_1$ junction injects holes, raising ${\alpha }_1$ until ${\alpha }_1+{\alpha }_2=1$ and the structure latches regeneratively, exactly as in an SCR. The negative resistance is therefore the thyristor latch rather than bar modulation, which is why the PUT has a lower valley voltage, is not tied to a fixed bar geometry, and can have its $\eta$ chosen freely by two resistors. Reference: General Electric SCR Manual, 6th ed., 1979; J. Millman and C.C. Halkias, Integrated Electronics, McGraw-Hill, 1972.

Ques: Why does the gate resistance $R_G$ set the peak current, and why does that matter?

At the peak point the PUT must draw enough current through $J_1$ to start the regenerative loop, and that current is supplied through the gate network. The gate sees the divider as a voltage source $V_G$ with series resistance $R_G=\eta R_1$, so the larger $R_G$ is, the less current the gate network can absorb and the smaller the anode current needed to reach latching, which lowers $I_P$. Datasheets show this as a falling $I_P$ with rising $R_G$ rather than as a closed-form equation, so use the manufacturer’s curves for design values. The effect matters for long-period timers: a very small $I_P$ lets the oscillator use a large $R_A$ (the upper bound of the oscillation condition grows as $(V_S-V_P)/I_P$), which makes long time constants possible with a modest capacitor. Reference: General Electric SCR Manual, 6th ed., 1979.

Ques: What is the right way to choose $R_1$ and $R_2$ in a PUT oscillator?

The two resistors do two jobs at once: their ratio sets $\eta =R_2/(R_1+R_2)$ and therefore the firing voltage $V_P=\eta V_S+V_D$ and the period $T\approx R_{A}C\ln [1/(1-\eta )]$, while their parallel combination sets $R_G$ and therefore $I_P$. A practical sequence is to pick the desired $I_P$ (or the largest $R_A$ allowed) to fix $R_G$ from the datasheet curve, then choose $R_1=R_G/\eta$ and $R_2=R_G/(1-\eta )$ for the required $\eta$. Choosing them in the other order can force a $R_G$ that gives an unusable $I_P$ even though $\eta$ is correct. Reference: General Electric SCR Manual, 6th ed., 1979.

Related pages in this vault: Unijunction Transistor (UJT), Thyristor (SCR), Silicon Controlled Switch (SCS), Gate Turn Off (GTO), Integrated Gate-Commutated Thyristor (IGCT), PN Junction.