Gate Turn Off (GTO)

1. Theory

• Definition: A gate turn-off thyristor (GTO) is a four-layer PNPN thyristor that can be turned on by a positive gate current and turned off by a negative gate current.
• Same structure as the SCR: It has the same three junctions and two-transistor latching model; only the gain balance and geometry are changed so the gate can break the latch.
• Gain asymmetry: The NPN gain ${\alpha }_2$ is made high and the PNP gain ${\alpha }_1$ low, so ${\alpha }_1+{\alpha }_2$ sits only just above 1 in the on-state.
• Inefficient anode: Anode shorts or a transparent anode lower the anode injection efficiency to keep ${\alpha }_1$ small.
• Interdigitated cathode: The cathode is split into many narrow fingers surrounded by gate metal, so the gate can reach every part of the $P_2$ base.

2. Working Principle

• Turn-on: A positive gate pulse latches the device on exactly as in an SCR.
• On-state: The $N_1$ base is conductivity-modulated, but less than in an SCR because of the weak anode, so the forward drop is somewhat higher.
• Gate turn-off: A large negative gate current pulls holes out of the $P_2$ base, reducing ${\alpha }_2$ until ${\alpha }_1+{\alpha }_2<1$ and regeneration collapses.
• Low turn-off gain: The anode current divided by the needed reverse gate current is only about 3–5, so the gate driver must sink very large currents.
• Storage, fall and tail: Turn-off goes through a storage delay, a fall in current, and a slow tail as charge in the wide $N_1$ base recombines; the tail sets most of the switching loss.
• Snubber required: A snubber limits the re-applied $dV/dt$ to prevent retriggering and current filamentation during turn-off.

3. Applications

• Current status: Largely replaced by IGCTs and press-pack IGBTs, which need simpler gate drives and no large snubbers.
• Historical role: High-power traction inverters, large industrial motor drives and early static compensators.

Name	Formula	Related Formulae	Variables/Constants
Anode current with reverse gate current	$I_A=\frac{-{\alpha }_2{I}_{GR}}{1-({\alpha }_1+{\alpha }_2)}$	$I_G=-I_{GR},I_K=I_A-I_{GR}$	$\begin{array}{r}{I}_{GR}:magnitudeofthereverse\\ (turn-off)gatecurrent\end{array}$ $I_A,I_K:anodeandcathodecurrents$ $\begin{array}{r}\text{(leakage}\text{terms}\text{neglected;}\text{see}\\ \text{Thyristor}\text{SCR}\text{page}\text{for}\text{the}\text{full}\\ \text{expression)}\end{array}$
Turn-off gain	${\beta }_{off}=\frac{I_A}{I_{GR}}=\frac{{\alpha }_2}{{\alpha }_1+{\alpha }_2-1}$	$I_{GR}=I_A\frac{{\alpha }_1+{\alpha }_2-1}{{\alpha }_2}$	$\begin{array}{r}{\beta }_{off}:ratiooftheanodecurrent\\ thatcanbeturnedofftothegate\\ currentrequired\end{array}$ $\begin{array}{r}\text{(large}\text{only}\text{if}{\alpha }_1+{\alpha }_2\text{is}\\ \text{just}\text{above}\text{1,}{\alpha }_2\text{high,}{\alpha }_1\\ \text{low)}\end{array}$
Turn-off design condition	${\alpha }_2\gg {\alpha }_1,{\alpha }_1+{\alpha }_2\gtrsim 1$	${\gamma }_{anode}\text{kept low via anode shorts / transparent anode}$	$\begin{array}{r}{\gamma }_{anode}:emitterinjection\\ efficiencyoftheanode(p_1)emitter\\ (seeBJTpage)\end{array}$
Maximum cathode finger width	$w_{max}=\sqrt{\frac{8B{V}_{J3}}{{\rho }_s{J}_{GR}}}$	$\Delta V=\frac{{\rho }_s{J}_{GR}{w}^2}{8},{\rho }_s=\frac{1}{q{\mu }_p{N}_A{W}_{pB}}$	$\begin{array}{r}{w}_{max}:widestcathodeemitterfinger\\ whosecentrecanstillbereversebiased\\ bythegateextractioncurrentwithout\\ avalanching{J}_3\end{array}$ $\begin{array}{r}B{V}_{J3}:breakdownvoltageofthe{n}_2/p_2\\ emitterjunction\end{array}$ ${\rho }_s:sheetresistanceofthe{p}_{2}base$ $J_{GR}:gateextractioncurrentdensity$ $W_{pB}:p_{2}basethickness$
Storage time	$t_s\approx \frac{Q_{pB}}{I_{GR}}$	$Q_{pB}\approx \tau I_A\text{(see PN Junction Diode / PIN Diode pages)}$	$\begin{array}{r}{t}_s:delaywhilethegateremovesthe\\ storedchargeinthe{p}_{2}basebefore\\ J_{3}beginstorecover\end{array}$ $\begin{array}{r}{Q}_{pB}:storedchargetobeextracted\\ (approximateestimate)\end{array}$
Tail current	$i_{tail}(t)\approx I_{tail,0}\exp \left(-\frac{t}{{\tau }_{n1}}\right)$	$t_{off}=t_s+t_f+t_{tail}$	$\begin{array}{r}{i}_{tail}:residualanodecurrentafter\\ thegatehasregainedcontrol,decaying\\ byrecombinationofchargestoredinthe\\ wide{n}_{1}base\end{array}$ ${\tau }_{n1}:carrierlifetimeinthe{n}_{1}base$ $t_f:falltime$
Re-applied dv/dt limit	$i_{disp}=C_{J2}\frac{dV}{dt}$	${\left(\frac{dV}{dt}\right)}_{crit}\approx \frac{I_{G,trig}}{C_{J2}}\text{(see Thyristor SCR page)}$	$\begin{array}{r}{i}_{disp}:displacementcurrentthroughthe\\ J_{2}depletioncapacitance\end{array}$ $\text{(sets the snubber requirement after turn-off)}$
Blocking voltage	$V_{DRM}\lesssim B{V}_{J2}\approx \frac{{\epsilon }_s{E}_{crit}^2}{2q{N}_D}$	$\text{(see Thyristor SCR / Avalanche Diode pages)}$	$\begin{array}{r}{N}_D:dopingofthelightlydoped{n}_1\\ base,whichsetstheblockingcapability\end{array}$

Important Questions

Ques: What lets a GTO turn off from the gate when an SCR cannot?

Both devices latch because ${\alpha }_1+{\alpha }_2\ge 1$ closes a positive-feedback loop. In an SCR the cathode emitter dominates the current in the $p_2$ base, and the gate can only add carriers there, so it cannot break the loop. In a GTO a negative gate current removes holes from the $p_2$ base; this lowers the base-emitter forward bias of the NPN half, which reduces the injection efficiency and hence ${\alpha }_2$ until ${\alpha }_1+{\alpha }_2$ falls below 1 and the regeneration collapses. Setting $I_G=-I_{GR}$ in the two-transistor equations gives the turn-off gain ${\beta }_{off}={\alpha }_2/({\alpha }_1+{\alpha }_2-1)$: only a small reverse gate current is needed if the loop gain sits just above 1. Reference: S.M. Sze and Kwok K. Ng, Physics of Semiconductor Devices, 3rd ed., Wiley, 2007; B.J. Baliga, Fundamentals of Power Semiconductor Devices, Springer, 2008.

Ques: Why is turn-off gain so low in practice, and what does it cost to improve it?

${\beta }_{off}$ is large only when ${\alpha }_2$ is high and ${\alpha }_1$ is low, but a low ${\alpha }_1$ makes it harder to sustain the latched on-state. The anode emitter is therefore deliberately made inefficient (anode shorts or a transparent anode keep ${\gamma }_{anode}$ low), and that raises the on-state voltage drop because conductivity modulation of the wide $n_1$ base is weaker than in an SCR (see the PIN Diode page for the plasma picture). Practical GTOs end up with ${\beta }_{off}$ of only about 3 to 5, so turning off a 3000 A device can require hundreds of amperes of reverse gate current, which makes the gate drive large, expensive, and a significant design problem. Reference: B.J. Baliga, Fundamentals of Power Semiconductor Devices, Springer, 2008.

Ques: Why is the cathode split into many narrow fingers?

During turn-off, the extraction current flows laterally through the thin, resistive $p_2$ base to the gate contact, and the voltage that builds up along the way is what reverse biases the $n_2/p_2$ emitter junction. The portion of an emitter finger far from the gate contact sees the smallest reverse bias, so it keeps conducting longest while current crowds into it, causing a filament that can destroy the device. The finger-width relation $w_{max}=\sqrt{8B{V}_{J3}/({\rho }_s{J}_{GR})}$ (a simple uniform-extraction estimate) shows the width must be limited so the centre of every finger is reverse biased before avalanche. This is why GTOs have many narrow, interdigitated cathode fingers with gate metal between them. Reference: B.J. Baliga, Fundamentals of Power Semiconductor Devices, Springer, 2008.

Ques: Why does GTO turn-off have a tail current, and why is a snubber mandatory?

Once the gate regains control, charge is still stored in the wide, lightly doped $n_1$ base where the gate has no direct access, so the anode current does not drop to zero immediately; it decays exponentially by recombination (the tail), and this decay sets the turn-off loss. During the tail, voltage is already rising across the device, so power dissipation is high. A rising $dV/dt$ also produces displacement current $C_{J2}dV/dt$ through $J_2$, which can retrigger the device if it is too fast, so GTOs always require a snubber to limit the rate of voltage rise. This snubber loss, along with the large gate drive, is the main motivation for later gate-commutated designs such as the IGCT. Reference: B.J. Baliga, Fundamentals of Power Semiconductor Devices, Springer, 2008.

Related pages in this vault: Integrated Gate-Commutated Thyristor (IGCT), Thyristor (SCR), Silicon Controlled Switch (SCS), Bipolar Junction Transistor (BJT), Programmable Unijunction Transistor (PUT), Insulated Gate Bipolar Transistor (IGBT), Bipolar Transistors (BJT and SiGe HBT), Silicon Power MOSFET, IGBT and Thyristors, Power Device Compact Models.