Silicon Controlled Switch (SCS)

1. Theory

Definition: A silicon controlled switch (SCS) is a low-power, four-terminal PNPN thyristor with external contacts to both internal bases.
Terminals: Anode, cathode, an anode gate ( $G_{A}$ ) on the $N_{1}$ base and a cathode gate ( $G_{K}$ ) on the $P_{2}$ base.
Same latching model: It uses the SCR’s two-transistor model, gains and junctions; the new feature is access to both bases.
Gate sign convention: Gate currents are positive when flowing into the device, so pulling current out of the anode gate is a negative $I_{G A}$ .
Two turn-off gains: The cathode gate gives $β_{o f f, K} = α_{2} / (α_{1} + α_{2} - 1)$ and the anode gate gives $β_{o f f, A} = (1 - α_{2}) / (α_{1} + α_{2} - 1)$ ; the cathode gate is more efficient whenever $α_{2} > 1/2$ .

2. Working Principle

Turn-on: A positive cathode-gate current or a current pulled out of the anode gate raises $α_{1} + α_{2}$ to 1 and latches the device.
Gate turn-off: Extracting current from the cathode gate, or injecting it into the anode gate, drives the loop gain below 1.
Current limit for turn-off: Small area and no specialised cathode geometry restrict gate turn-off to milliampere to about hundred-milliampere currents.
Adjustable thresholds: Resistors from a gate to its neighbouring terminal divert base current, raising the trigger and holding levels.
Commutation: Like an SCR, it also turns off when the anode current falls below the holding current.

3. Applications

Current status: Largely obsolete; logic ICs, microcontrollers and small MOSFETs now do these jobs, and few SCS parts remain in production.
Historical role: Counters, ring counters, alarm and latching-indicator circuits, and lamp and relay drivers.

Name	Formula	Related Formulae	Variables/Constants
Cathode current (terminal balance)	$I_{K} = I_{A} + I_{G K} + I_{G A}$	$I_{C 1} + I_{C 2} = I_{A} + I_{G A}$	$I_{A}, I_{K} : an o d e an d c a t h o d e c u r r e n t s$ $I_{G K}, I_{G A} : c a t h o d e g a t e an d an o d e g a t e c u r r e n t s (p os i t i v e in t o t h e d e v i ce)$ $I_{C 1}, I_{C 2} : co l l ec t or c u r r e n t s o f t h e P N P an d N P N ha l v es$
Anode current with both gates	$I_{A} = \frac{α _{2} I _{G K} - ( 1 - α _{2} ) I _{G A} + I _{C B O 1} + I _{C B O 2}}{1 - ( α _{1} + α _{2} )}$	$I_{C 1} = α_{1} I_{A} + I_{C B O 1}, I_{C 2} = α_{2} I_{K} + I_{C B O 2}$	$I_{C B O 1}, I_{C B O 2} : co l l ec t or l e ak a g e c u r r e n t s$ $(reduces to the SCR expression when I_{G A} = 0; see Thyristor SCR page)$
Latching (turn-on) condition	$α_{1} + α_{2} = 1$	$α_{i} = α_{i} (I_{E}) increases with emitter current (see Thyristor SCR page)$	$(either a positive I_{G K} or a negative I_{G A} raises the gains until this is met)$
Gate trigger threshold	$V_{G K} \approx V_{T} ln (\frac{I _{G K}}{I _{S}}) \approx 0.6 - 0.7 V$	$I = I_{S} [exp (\frac{V}{V _{T}}) - 1] (see PN Junction Diode page)$	$V_{G K} : g a t e - c a t h o d e v o l t a g e, se t b y t h e f or w a r d bia s o f J_{3}$ $I_{S} : J_{3} s a t u r a t i o n c u r r e n t$ $(the anode gate triggers when it is pulled about one diode drop below the anode, by the same relation applied to J_{1})$
Turn-off gain via the cathode gate	$β_{o f f, K} = \frac{I _{A}}{I _{GR}} = \frac{α _{2}}{α _{1} + α _{2} - 1}$	$I_{G K} = - I_{GR} (see Gate Turn-Off Thyristor page)$	$I_{GR} : ma g ni t u d e o f t h e c u r r e n t e x t r a c t e d f r o m t h e p_{2} ba se$ $β_{o f f, K} : an o d e c u r r e n t t ha t c an b e t u r n e d o f f p er u ni t o f c a t h o d e g a t e e x t r a c t i o n c u r r e n t$
Turn-off gain via the anode gate	$β_{o f f, A} = \frac{I _{A}}{I _{G A}} = \frac{1 - α _{2}}{α _{1} + α _{2} - 1}$	$I_{G A} = I_{A} \frac{α _{1} + α _{2} - 1}{1 - α _{2}} > 0$	$I_{G A} : p os i t i v e c u r r e n t inj ec t e d in t o t h e n_{1} ba se a t t u r n - o f f$ $β_{o f f, A} : an o d e c u r r e n t t ha t c an b e t u r n e d o f f p er u ni t o f an o d e g a t e c u r r e n t$
Holding current and dv/dt limit	$α_{1} (I_{H}) + α_{2} (I_{H}) = 1, i_{d i s p} = C_{J 2} \frac{d V}{d t}$	$(see Thyristor SCR page)$	$I_{H} : minim u m an o d e c u r r e n t t ha t k ee p s t h e d e v i ce l a t c h e d$ $C_{J 2} : J_{2} d e pl e t i o n c a p a c i t an ce$
Blocking voltage	$V_{B O} ≲ B V_{J 2} \approx \frac{ε _{s} E _{cr i t}^{2}}{2 q N _{D}}$	$(see Thyristor SCR / Avalanche Diode pages)$	$N_{D} : d o p in g o f t h e l i g h tl y d o p e d n_{1} ba se$

Important Questions

Ques: What does access to both bases give an SCS that an ordinary SCR does not have?

An SCR exposes only the $p_{2}$ base, so current can only be injected there and the device can only be turned on from the gate. The SCS also exposes the $n_{1}$ base, so either base can be driven: a positive cathode-gate current or a negative (extracted) anode-gate current raises $α_{1} + α_{2}$ toward 1 and triggers the device, while a negative cathode-gate current or a positive anode-gate current drives the gains below 1 and turns it off. External resistors or bias networks at the two gates can also divert part of each base current, which shifts the trigger and holding levels, and this tunability is the main practical reason SCS devices are used in small timing, counting, and alarm circuits. Reference: S.M. Sze and Kwok K. Ng, Physics of Semiconductor Devices, 3rd ed., Wiley, 2007.

Ques: Why does the SCS turn off from the gate only at small currents, and which gate is better?

The two turn-off gains follow from the same two-transistor equations: $β_{o f f, K} = α_{2} / (α_{1} + α_{2} - 1)$ for the cathode gate and $β_{o f f, A} = (1 - α_{2}) / (α_{1} + α_{2} - 1)$ for the anode gate. Both grow large only when the loop gain $α_{1} + α_{2}$ sits just above 1, and shrink as it moves further above 1. Their ratio is $β_{o f f, K} / β_{o f f, A} = α_{2} / (1 - α_{2})$ , so the cathode gate is the more efficient turn-off terminal whenever $α_{2} > 1/2$ , which is the normal case since the NPN half is usually the higher-gain transistor. As an illustration (not device data), $α_{1} = 0.4$ and $α_{2} = 0.7$ give $β_{o f f, K} = 7$ and $β_{o f f, A} = 3$ . In practice the SCS is a small-area, low-current part, and unlike a GTO it has no specialized cathode geometry for extracting large currents uniformly, so gate turn-off is practical only at milliampere to roughly hundred-milliampere anode currents. Reference: S.M. Sze and Kwok K. Ng, Physics of Semiconductor Devices, 3rd ed., Wiley, 2007.

Ques: Why does a resistor from a gate to its adjacent terminal change the trigger level?

A resistor from the cathode gate to the cathode shunts part of the PNP collector current around the base-emitter junction $J_{3}$ . Until that current exceeds the roughly $0.6 V / R$ drawn by the resistor, the NPN half sees little base drive, so its gain stays low and $α_{1} + α_{2}$ stays below 1. A smaller resistance therefore raises the anode current (and voltage) needed to latch, and also raises the holding current. The same logic applies to a resistor between the anode gate and the anode. This is the practical mechanism for setting thresholds in an SCS circuit without changing the device. Reference: S.M. Sze and Kwok K. Ng, Physics of Semiconductor Devices, 3rd ed., Wiley, 2007.

Quartz 5

Explorer