RC Delay and Repeater Insertion

1. Theory

• Definition: RC delay is the time for a signal to propagate along an interconnect whose resistance and capacitance are distributed along its length; it grows with the square of the length, so long wires are broken into sections by repeaters (van der Meijs; Ismail and Friedman).
• Elmore delay: The first moment of the impulse response, a sum of resistance-capacitance products over an RC tree, gives a simple upper estimate of the 50 per cent delay (van der Meijs).
• Distributed line: An open-ended uniform line has an Elmore delay of $rc{l}^2/2$ and a 50 per cent delay of about $0.38rc{l}^2$, against $0.69rc{l}^2$ if the capacitance were lumped (background knowledge; van der Meijs).
• Repeaters: Inserting $k$ inverters of size $h$ makes the delay linear in length; Bakoglu’s optimum sets the number and size from the line and inverter parameters (Ismail and Friedman).
• Scaling: At constant capacitance per length, the resistance per length of a wire rises as the square of the scaling factor, so global wire delay grows each generation while gate delay falls, and line and via resistance dominate delay at the 7 and 5 $\mathrm{nm}$ nodes (Besser; background knowledge for the scaling).

2. Working Principle

• Diffusion of charge: A voltage step at one end of an RC line charges it like heat diffusing along a rod, so the arrival time grows with $rc{l}^2$ and the edge spreads out with distance (background knowledge).
• Moment matching: The Elmore delay uses only the first moment of the response, which is exact for the area under the response curve and an upper bound on the 50 per cent delay for RC trees (background knowledge; van der Meijs).
• Repeater trade-off: Each repeater adds its own intrinsic delay but restores the edge and cuts the quadratic term; the optimum balances the repeater delay $R_0{C}_0$ against the wire delay of each section (Ismail and Friedman; background knowledge).
• Driver dominance: For short or wide wires the driver resistance charging the total capacitance dominates, and wire resistance matters only when $rl$ approaches the driver resistance (van der Meijs; background knowledge).

3. Applications

• Timing analysis: Elmore and moment-based delay estimates in placement, routing and static timing of RC networks (van der Meijs).
• Repeater planning: Number, size and spacing of repeaters on long intermediate and global wires (Ismail and Friedman).
• Layer assignment: Routing timing-critical long nets on wider, thicker upper layers, where $rc$ is lower (background knowledge).
• Technology assessment: Comparing metals, barriers and low-k dielectrics through their effect on $rc$ (Besser; Wire Resistance and Wire Capacitance pages).

Delay Models

Name	Formula	Related Formulae	Variables/Constants
Elmore delay of an RC tree	$T_{Di}={\sum }_{k=1}^N{R}_{ik}{C}_k$	$t_{50}\approx 0.69T_{Di}(\text{single-pole estimate})$	$T_{Di}:Elmoredelayatnodei$ $\begin{array}{r}{R}_{ik}:resistanceofthepathsharedbynode\\ iandnodekfromthesource\end{array}$ $C_k:capacitanceatnodek$ $N:numberofnodes$ $\begin{array}{r}{t}_{50}:50percentdelay;vanderMeijs:the\\ ElmoresumforRCladdersandtrees,with\\ 0.69T_{Di}usedastheapproximationofthe\\ wiredelay{t}_{50},andauniformRCline\\ alwaysmodelledtofirstorderasa\\ symmetricpisectionwithhalfthewire\\ capacitanceateachend;R=\rho l/(wt),R_{\square }\\ =\rho /tandC={\epsilon }_0{\epsilon }_{r}wl/d,withexamplesof\\ 40\Omega persquare(240and440\Omega for6and\\ 11squares)andM1capacitancesof41\\ aF/\mu {\mathrm{m}}^{2}and47aF/\mu \mathrm{m}overactiveand30\\ aF/\mu {\mathrm{m}}^{2}and40aF/\mu \mathrm{m}overfield\end{array}$ $(nocomputedvalue)$
Distributed RC line: lumped against distributed delay	$t_{50,dist}\approx 0.38rc{l}^2,t_{50,lump}\approx 0.69rc{l}^2$	$T_{D,dist}=\frac{rc{l}^2}{2}(\text{Elmore value of a uniform line})$	$\begin{array}{r}{t}_{50,dist}:50percentdelayofanopen-ended\\ distributedlinedrivenbyanidealstep\end{array}$ $r,c:resistanceandcapacitanceperunitlength$ $l:length$ $\begin{array}{r}{t}_{50,lump}:50percentdelayifthewhole\\ capacitancewerelumpedattheend\end{array}$ $\begin{array}{r}{T}_{D,dist}:Elmoredelayofthedistributedline\\ (0.38coefficientfromthediffusion\\ solution,backgroundknowledge);vander\\ Meijs:delayisquadraticinlinelength;\\ resistanceperlengthfromtheWire\\ Resistancepageandcapacitanceperlength\\ fromtheWireCapacitancepage\end{array}$ $\begin{array}{r}(computed:0.69xrc{l}^2/2=0.345rc{l}^2,9\\ percentbelow0.38rc{l}^2;foranassumed10\\ by20\mathrm{nm}Culineat16\mu \Omega \mathrm{cm}effective,\\ 800\Omega /\mu \mathrm{m}and0.2fF/\mu \mathrm{m}(assumed),10and\\ 100\mu \mathrm{m}lengthsgive6.1and608\mathrm{ps})\end{array}$
Driver, line and load	$T_D\approx R_s\left(cl+C_L\right)+rl\left(\frac{cl}{2}+C_L\right)$	$t_{50}\approx 0.69R_s\left(cl+C_L\right)+0.69rl{C}_L+0.38rc{l}^2$	$\begin{array}{r}{T}_D:Elmoredelayofadriverofresistance\\ R_{s}throughalineoftotalresistancerl\\ andcapacitanceclintoaload{C}_L\end{array}$ $\begin{array}{r}{t}_{50}:50percentdelaywith0.69forthe\\ lumpedtermsand0.38forthedistributed\\ term(backgroundknowledgeforthemixed\\ coefficients);vanderMeijs:the\\ canonicaldriver-line-loadElmoreform,\\ quadraticinlength\end{array}$ $\begin{array}{r}(computed:anassumed1\mathrm{k\Omega }driver,10\mathrm{fF}\\ loadand1\mathrm{mm}ofglobalCu,1by2\mu \mathrm{m}at\\ 2.2\mu \Omega \mathrm{cm}with0.2fF/\mu \mathrm{m},giverl=11\\ \Omega ,cl=200\mathrm{fF},T_D=211\mathrm{ps}and{t}_{50}=146\\ \mathrm{ps},dominatedbythedriver)\end{array}$

Repeaters and Scaling

Name	Formula	Related Formulae	Variables/Constants
Optimal repeater insertion (Bakoglu)	$k_{opt}=\sqrt{\frac{R_t{C}_t}{2R_0{C}_0}},h_{opt}=\sqrt{\frac{R_0{C}_t}{R_t{C}_0}}$	$T_{min}\approx 2.5\sqrt{R_0{C}_0{R}_t{C}_t}$	$k_{opt}:optimumnumberofrepeatersections$ $\begin{array}{r}{h}_{opt}:optimumrepeatersizerelativetoa\\ minimuminverter\end{array}$ $R_t,C_t:totallineresistanceandcapacitance$ $\begin{array}{r}{R}_0,C_0:outputresistanceandinput\\ capacitanceofaminimuminverter\end{array}$ $\begin{array}{r}{T}_{min}:minimumtotaldelay(minimum-delay\\ expression,backgroundknowledgeafter\\ Bakoglu);IsmailandFriedman:theRC\\ solutionfor{k}_{opt}and{h}_{opt}isthesameas\\ Bakogl{u}^{\prime }s,andinductancelowersboth(RLC\\ correctionsontheCrosstalkandInductive\\ Effectspage)\end{array}$ $\begin{array}{r}(computed:a1\mathrm{cm}intermediatelineof100\\ by200\mathrm{nm}Cuatanassumed3\mu \Omega \mathrm{cm}and\\ 0.2fF/\mu \mathrm{m}has{R}_t=15\mathrm{k\Omega }and{C}_t=2\mathrm{pF},an\\ unrepeated0.38R_t{C}_{t}of11.4\mathrm{ns};withan\\ assumed{R}_0=10\mathrm{k\Omega }and{C}_0=1\mathrm{fF},k_{opt}=39,\\ h_{opt}=37and{T}_{min}=1.37\mathrm{ns},8.3times\\ faster)\end{array}$
Delay per length with repeaters	$\frac{T_{min}}{l}\approx 2.5\sqrt{R_0{C}_{0}rc}$	$l_{crit}=\frac{l}{k_{opt}}=\sqrt{\frac{2R_0{C}_0}{rc}}$	$\begin{array}{r}{T}_{min}/l:delayperunitlengthofan\\ optimallyrepeatedline,linearinlength\end{array}$ $\begin{array}{r}{l}_{crit}:optimumrepeaterspacing,other\\ symbolsasabove(backgroundknowledge,\\ followingfromtheBakoglusolution);\\ Besser:capacitancescalingslowsbeyond\\ 10\mathrm{nm}andlineandviaresistanceare\\ expectedtodominatedelayatthe7and5\\ \mathrm{nm}nodes\end{array}$ $\begin{array}{r}(computed:fortheexamplelinethe\\ spacingis0.26\mathrm{mm}andthedelay137\mathrm{ps}\\ per\mathrm{mm})\end{array}$
Scaling of wire delay	$rc=\frac{\rho }{wh}c\Rightarrow rc\propto S^2(w,h\text{scaled by }1/S,c\text{per length fixed})$	$t_{local}\propto rc{l}^2\approx \text{constant}(l\propto 1/S),t_{global}\propto S^2(\text{fixed }l)$	$\begin{array}{r}rc:productofresistanceandcapacitance\\ perlength\end{array}$ $\rho :resistivity$ $\epsilon :permittivity$ $S:scalingfactor$ $\begin{array}{r}{t}_{local},t_{global}:delayoflocalwiresthat\\ shrinkwiththecircuitandofglobal\\ wiresthatkeeptheirlength(background\\ knowledge,ignoringsizeeffects,which\\ makeresistancegrowfaster);sizeeffects\\ ontheWireResistancepage\end{array}$ $\begin{array}{r}(computed:halvingwidthandthickness\\ raisesrc4times;withthesizeeffectit\\ risesmore)\end{array}$

Important Questions

Ques: Is the 50 per cent delay of a distributed RC line 0.38 RC or 0.345 RC?

The two values come from different approximations. The exact step response of an open-ended uniform RC line, found by solving the diffusion equation, reaches 50 per cent at about $0.38rc{l}^2$ (background knowledge). Van der Meijs instead approximates every wire delay as 0.69 times the Elmore delay, which for a distributed line is $rc{l}^2/2$, giving $0.345rc{l}^2$, 9 per cent lower (computed). The 0.69 factor is exact only for a single pole, so applying it to a distributed line underestimates the delay. The 0.38 value is therefore the more accurate one for a bare line, while the 0.69 Elmore estimate is a convenient, slightly optimistic shortcut that is exact for lumped parts such as the driver resistance charging the load. Mixed estimates use 0.69 for lumped terms and 0.38 for the distributed term. Reference: N. van der Meijs (NvdM), ET4293 Digital VLSI and ET1205 interconnect lecture slides, TU Delft (2008), based on Chapter 4 of a 2nd-edition textbook not named in the slides (fetch-tool summary).

Ques: How long can a narrow local wire be before its own RC delay matters?

Only tens of micrometres at the tightest pitches. An assumed 10 by 20 $\mathrm{nm}$ Cu line with the 16 $\mu \Omega \mathrm{cm}$ effective resistivity estimated on the Wire Resistance page has about 800 $\Omega /\mu \mathrm{m}$, and with an assumed 0.2 $fF/\mu \mathrm{m}$ its distributed delay is 6.1 $\mathrm{ps}$ for 10 $\mu \mathrm{m}$ but 608 $\mathrm{ps}$ for 100 $\mu \mathrm{m}$ (computed), because the delay grows with the square of the length. Gate delays are a few picoseconds, so such a line should stay below a few tens of micrometres. Besser notes that line and via resistance are expected to dominate delay at the 7 and 5 $\mathrm{nm}$ nodes. Longer connections are therefore routed on wider upper layers, where the resistance per length is two to three orders of magnitude lower. Reference: P. Besser, ‘BEOL Interconnect Innovations for Improving Performance’, NCCAVS Symposium, San Jose (23 February 2017) (slides) (fetch-tool summary); Wire Resistance and Size Effects page of this vault.

Ques: How many repeaters does a long wire need, and how much do they help?

Bakoglu’s optimum, as given by Ismail and Friedman, is $k_{opt}=\sqrt{R_t{C}_t/(2R_0{C}_0)}$ sections of size $h_{opt}=\sqrt{R_0{C}_t/(R_t{C}_0)}$. For an assumed 1 $\mathrm{cm}$ line of 100 by 200 $\mathrm{nm}$ Cu at 3 $\mu \Omega \mathrm{cm}$ and 0.2 $fF/\mu \mathrm{m}$, the line has 15 $\mathrm{k\Omega }$ and 2 $\mathrm{pF}$, so the unrepeated distributed delay is 11.4 $\mathrm{ns}$ (computed). With an assumed minimum inverter of 10 $\mathrm{k\Omega }$ and 1 $\mathrm{fF}$, the optimum is about 39 repeaters, 37 times minimum size, spaced about 0.26 $\mathrm{mm}$ apart, and the minimum delay $2.5\sqrt{R_0{C}_0{R}_t{C}_t}$ is 1.37 $\mathrm{ns}$ (computed, background knowledge for the delay expression), 8.3 times faster. The repeated delay grows only linearly, about 137 $\mathrm{ps}$ per $\mathrm{mm}$ here (computed). Reference: Y. I. Ismail and E. G. Friedman, ‘Effects of Inductance on the Propagation Delay and Repeater Insertion in VLSI Circuits’, DAC 1999 (University of Rochester copy; equations reconstructed from a garbled PDF) (fetch-tool summary).

Ques: Why does wire delay get worse with scaling while transistors get faster?

Because shrinking a wire’s width and thickness by a factor $S$ raises its resistance per length by $S^2$, while its capacitance per length stays about the same, since all dimensions shrink together, so $rc$ rises by $S^2$, four times for each halving (computed, background knowledge for the scaling argument). A local wire that also shrinks in length by $S$ keeps about the same delay, but a global wire that spans a chip of fixed size becomes $S^2$ slower. The resistivity size effect makes this worse, because the resistivity itself rises as the wire narrows. Besser expects line and via resistance to dominate delay at the 7 and 5 $\mathrm{nm}$ nodes, with capacitance scaling slowing beyond 10 $\mathrm{nm}$. Repeaters, thicker upper layers and lower-resistance metals offset part of the loss. Reference: P. Besser, ‘BEOL Interconnect Innovations for Improving Performance’, NCCAVS Symposium, San Jose (23 February 2017) (slides) (fetch-tool summary); Wire Resistance and Size Effects page of this vault.

Ques: When does the driver, rather than the wire, set the delay?

When the wire resistance is small compared with the driver resistance. For the Elmore form $R_s(cl+C_L)+rl(cl/2+C_L)$, an assumed 1 $\mathrm{k\Omega }$ driver, a 10 $\mathrm{fF}$ load and 1 $\mathrm{mm}$ of global Cu, 1 by 2 $\mu \mathrm{m}$ at 2.2 $\mu \Omega \mathrm{cm}$ with 0.2 $fF/\mu \mathrm{m}$, give a line of only 11 $\Omega$ and 200 $\mathrm{fF}$ (computed). The Elmore delay is then 211 $\mathrm{ps}$ and the 50 per cent delay about 146 $\mathrm{ps}$, almost all from the driver charging 210 $\mathrm{fF}$ (computed). Widening the wire would barely help, while a stronger driver would. The opposite case is the narrow local line, where the line resistance reaches hundreds of ohms per micrometre. Van der Meijs notes that the delay is quadratic in length, which holds once $rl$ exceeds the driver resistance. Reference: N. van der Meijs (NvdM), ET4293 Digital VLSI and ET1205 interconnect lecture slides, TU Delft (2008), based on Chapter 4 of a 2nd-edition textbook not named in the slides (fetch-tool summary).

Ques: How accurate is the Elmore delay for interconnect timing?

Accurate enough for estimates and optimization, but not for sign-off. The Elmore delay ${\sum }_k{R}_{ik}{C}_k$ is the first moment of the impulse response, and van der Meijs uses 0.69 times it as the 50 per cent delay for RC ladders and trees. For a single pole this is exact, but for a distributed line it is 9 per cent low, and for nodes near the driver of a large tree it can overestimate the delay, because the response there is not single-pole (computed for the line; background knowledge for trees). It also ignores inductance: Ismail and Friedman show that RC models misestimate repeater delay by up to 30 per cent and oversize repeaters when inductance matters. Its simplicity and closed form make it the standard objective in routing and buffer insertion. Reference: N. van der Meijs (NvdM), ET4293 Digital VLSI and ET1205 interconnect lecture slides, TU Delft (2008), based on Chapter 4 of a 2nd-edition textbook not named in the slides (fetch-tool summary); Y. I. Ismail and E. G. Friedman, ‘Effects of Inductance on the Propagation Delay and Repeater Insertion in VLSI Circuits’, DAC 1999 (University of Rochester copy; equations reconstructed from a garbled PDF) (fetch-tool summary).

Related pages in this vault: Crosstalk and Inductive Effects, Wire Capacitance and Low-k Dielectrics, Contacts and Vias, Interconnect Joule Heating, Wire Resistance and Size Effects.