Contacts and Vias

1. Theory

• Definition: Contacts connect the first metal level to the silicided source, drain and gate of transistors in the middle of line, and vias connect successive metal levels; both are short vertical conductors whose resistance is set by an interface resistivity, a barrier and a small cross-section (Stavitski et al.; Lanzillo et al.).
• Specific contact resistivity: The metal-semiconductor interface has a resistance per area ${\rho }_c$, which must fall below about $1\times 10^{-9}$ $\Omega \mathrm{c}{\mathrm{m}}^2$ at the 7 and 5 $\mathrm{nm}$ nodes, where a 20 by 20 $\mathrm{nm}$ contact of that quality already has about 250 $\Omega$ (imec; computed).
• Transfer length: Current enters a silicided contact within a transfer length $L_c=\sqrt{{\rho }_c/R_s}$ of its edge, about 0.1 $\mu \mathrm{m}$ for PtSi, so longer contacts do not lower the resistance further (Stavitski et al.).
• Via barriers: Diffusion barriers such as TaN have resistivities of hundreds to thousands of $\mu \Omega \mathrm{cm}$, so at small via sizes the barrier at the via bottom can dominate the via resistance (Besser; van der Straten et al.).
• Performance impact: Via resistance has a smaller effect on logic performance than line resistance per relative change, but both grow with scaling (Lanzillo et al.).

2. Working Principle

• Tunnelling contacts: Heavy doping thins the Schottky barrier at the silicide-semiconductor interface so carriers tunnel through it, which lowers ${\rho }_c$; at lower doping the I-V becomes nonlinear and ${\rho }_c$ rises steeply (Stavitski et al.; background knowledge for tunnelling; Schottky Diode page).
• Current crowding: In a long planar contact the current flows mostly near the leading edge, over a transfer length set by ${\rho }_c$ and the sheet resistance below (Stavitski et al.).
• Via conduction path: Current passes from the lower line through the barrier at the via bottom, up the copper core and into the upper line, with each part in series and with size effects in the narrow core (background knowledge; Wire Resistance page).
• Barrier conformality: A conformal ALD barrier can be thinner at the via bottom than a directional PVD barrier of the same nominal sidewall thickness, so its bottom contribution can be smaller even with a higher film resistivity (my reading of van der Straten et al. and Zhang et al.).

3. Applications

• Source/drain contact engineering: Doping, implants such as Ga in p-SiGe and laser anneals to lower ${\rho }_c$ at advanced nodes (imec).
• Contact metrology: TLM, circular TLM and cross-Kelvin structures for extracting ${\rho }_c$ (Stavitski et al.; imec).
• Via and barrier optimization: Thin ALD barriers, barrier materials and redundant vias to lower via resistance (van der Straten et al.; Zhang et al.; Lanzillo et al.).
• Timing and IR-drop models: Contact and via resistances in parasitic extraction for timing and power-grid analysis (Lanzillo et al.; background knowledge).

Contacts

Name	Formula	Related Formulae	Variables/Constants
Specific contact resistivity and contact resistance	$R_c=\frac{{\rho }_c}{A_c}(\text{contact shorter than the transfer length})$	${\rho }_c={\left(\frac{\partial J}{\partial V}\right)}_{V=0}^{-1}$	$R_c:contactresistance$ $\begin{array}{r}{\rho }_c:specificcontactresistivityofthe\\ metalorsilicidetosemiconductor\\ interface\end{array}$ $A_c:contactarea$ $J:currentdensity$ $\begin{array}{r}V:voltageacrosstheinterface\\ (definitions,backgroundknowledge;\\ barrierphysicsontheSchottkyDiode\\ page);imec:recordPMOSsource/drain\\ contactresistivitybelow1\times 10^{-9}\Omega \mathrm{c}{\mathrm{m}}^{2}with\\ shallowGaimplantationintop-SiGeand\\ nanosecondlaseranneal,measuredon\\ multi-ringcircularTLMstructures,with\\ valuesbelow1\times 10^{-9}\Omega \mathrm{c}{\mathrm{m}}^{2}targetedfor\\ highlydopedn-Siandp-SiGeatN7andN5,\\ wherecontactresistancethreatensto\\ becomethedominatingparasitic\end{array}$ $\begin{array}{r}(computed:a20by20\mathrm{nm}contacthas250\Omega \\ at1\times 10^{-9}\Omega \mathrm{c}{\mathrm{m}}^{2}and2.5\mathrm{k\Omega }at1\times 10^{-8}\Omega \mathrm{c}{\mathrm{m}}^2)\end{array}$
Transmission line model of a silicided contact	$R_c=\frac{2\sqrt{{\rho }_c{R}_s}}{W}\tanh \left(\frac{L}{2L_c}\right),L_c=\sqrt{\frac{{\rho }_c}{R_s}}$	$R_0=\frac{2\sqrt{{\rho }_c{R}_s}}{W}(L\gg L_c),{\rho }_c=\frac{L_c{R}_{0}W}{2},R_{c}W=\frac{\left(R_n-R_{ref}\right)W}{n}$	$\begin{array}{r}{R}_s:sheetresistanceofthesiliconunder\\ thesilicide\end{array}$ $W:silicidewidth$ $L:silicidedsegmentlength$ $L_c:transferlength$ $R_0:saturationcontactresistance$ $R_n:resistancewithnsilicidedsegments$ $R_{ref}:referenceresistance$ $\begin{array}{r}n:numberofsegments(transfer-length\\ relation,backgroundknowledge);Stavitski\\ etal.:theScottmethodonstructures\\ with5to150segmentsof0.1to3\mu \mathrm{m}\\ lengthand2and8\mu \mathrm{m}width,{\rho }_{c}risingas\\ dopingfallsandfallingwithtemperature,\\ PtSitransferlengthsof0.08to0.122\mu \mathrm{m},\\ lowestmeasurabledopingof4to5\times 10^{18}and\\ 2to3\times 10^{18}\mathrm{c}{\mathrm{m}}^{-3}forNiSionn+andp+and7\\ to8\times 10^{18}and1to2\times 10^{18}\mathrm{c}{\mathrm{m}}^{-3}forPtSi,\\ lateralsilicidegrowthof0.025to0.035\\ \mu \mathrm{m}(NiSi)and0.035to0.05\mu \mathrm{m}(PtSi)per\\ sidethatmustbemeasuredbyTEM,NiSi\\ andPtSisheetresistancesof7to8and\\ 25to26\Omega /\mathrm{sq},andnonlinearI-Vat\\ intermediatedopinglinkedtotheSchottky\\ barrier\end{array}$ $\begin{array}{r}(computed:anassumed{\rho }_c=1\times 10^{-8}\Omega \mathrm{c}{\mathrm{m}}^2\\ underanassumed100\Omega /\mathrm{sq}gives{L}_c=0.1\mu \mathrm{m},\\ insidethePtSirange)\end{array}$

Vias and Barriers

Name	Formula	Related Formulae	Variables/Constants
Series model of via resistance	$R_{via}\approx \frac{{\rho }_b{t}_b}{A_{via}}+\frac{{\rho }_{core}{h}_{core}}{A_{core}}+R_{int}$	$R_{stack}={\sum }_i{R}_{via,i},R_{redundant}=\frac{R_{via}}{n_v}$	$R_{via}:viaresistance$ $\begin{array}{r}{\rho }_b,t_b:resistivityandthicknessofthe\\ barrierattheviabottom\end{array}$ $A_{via}:viabottomarea$ $\begin{array}{r}{\rho }_{core},h_{core},A_{core}:resistivity,heightand\\ areaofthecoppercore\end{array}$ $R_{int}:interfaceresistances$ $R_{stack}:resistanceofstackedvias$ $\begin{array}{r}{n}_v:numberofredundantviasinparallel\\ (seriespicture,backgroundknowledge;\\ coreresistivityfromtheWireResistance\\ page);Besser:TaNabout1000\mu \Omega \mathrm{cm},and\\ at12\mathrm{nm}linewidthloweringbarrier\\ resistivityfrom1000to25\mu \Omega \mathrm{cm}cuts\\ lineresistancebyabout40percent;\\ Lanzilloetal.:barrieroptimization\\ beyondthe5\mathrm{nm}nodecanlowervia\\ resistancebyupto26percent,about2\\ percentperformanceuplift\end{array}$ $\begin{array}{r}(computed:anassumed20\mathrm{nm}squareviaof\\ 30\mathrm{nm}heightwith2\mathrm{nm}ofPVDTaNat250\\ \mu \Omega \mathrm{cm}andaCucoreat5\mu \Omega \mathrm{cm}gives\\ 12.5+5.5=18\Omega ,thebarriertaking70\\ percent)\end{array}$
ALD against PVD TaN barriers	$R_b=\frac{{\rho }_b{t}_{b,bottom}}{A_{via}}$	$\frac{\Delta R_{via}}{R_{via}}\text{(measured)}$	$R_b:barriercontributiontoviaresistance$ $\begin{array}{r}{t}_{b,bottom}:barrierthicknessactuallypresentat\\ theviabottom,othersymbolsasabove;\\ vanderStratenetal.:Ta-richPVDTaNof\\ about240\mu \Omega \mathrm{cm}andALDTaNofabout5000\\ \mu \Omega \mathrm{cm},PVDresistivityrisingsharplyat\\ highnitrogenflowandlowDCpower,and\\ viaresistancefallingasALDreplacesPVD\\ TaN,about28percentlowerat3\mathrm{nm};\\ Zhangetal.:PEALDTaNofabout2000\\ \mu \Omega \mathrm{cm}and11.6g/c{\mathrm{m}}^{3}againstabout250\\ \mu \Omega \mathrm{cm}and15.0g/c{\mathrm{m}}^{3}forTa-richPVDTaN,\\ a10\mathring{\mathrm{A}}PEALDbarrierloweringvia\\ resistanceby50percentagainstthePVD\\ baselineon32\mathrm{nm}structures,and\\ significantintegrationchallengesbelow\\ 30\mathrm{nm}\end{array}$ $\begin{array}{r}(computed:inapureseriesmodel1\mathrm{nm}of\\ ALDTaNat5000or2000\mu \Omega \mathrm{cm}ona20\mathrm{nm}\\ viabottomwouldadd125or50\Omega ,more\\ thanthe12.5\Omega of2\mathrm{nm}PVDTaN,sothe\\ measuredreductionsmeantheseriesmodel\\ failsforthesefilms(seetheQ/A))\end{array}$

Performance Impact

Name	Formula	Related Formulae	Variables/Constants
Performance sensitivity to line and via resistance	$\frac{\Delta f}{f}\approx -S_R\frac{\Delta R}{R}$	$S_R\approx \frac{0.08}{0.25}(\text{line}),S_R\approx \frac{0.02}{0.26}(\text{via})$	$\Delta f/f:relativefrequencychange$ $\begin{array}{r}{S}_R:sensitivitytoarelativeresistance\\ change\Delta R/R(linearsensitivityform,my\\ reading);Lanzilloetal.(7,5and3\mathrm{nm}\\ nodes,abinitio,finite-elementand\\ circuitanalysis):line-edgeroughnessand\\ line-heightvariationtogetheraddmore\\ than25percentlineresistancebeyond5\\ \mathrm{nm}withabout8percentperformance\\ penalty,andbarrieroptimizationlowering\\ viaresistancebyupto26percentgives\\ about2percentuplift;imec:contact\\ resistancethreatenstodominatethe\\ parasiticsatN7andN5\end{array}$ $\begin{array}{r}(computed:about0.32percentof\\ performanceperpercentofline\\ resistanceandabout0.08percentperper\\ centofviaresistance)\end{array}$

Important Questions

Ques: How large is the resistance of a nanometre-scale contact?

For a contact shorter than its transfer length, the resistance is ${\rho }_c/A_c$ (background knowledge). A 20 by 20 $\mathrm{nm}$ contact has 250 $\Omega$ at $1\times 10^{-9}$ $\Omega \mathrm{c}{\mathrm{m}}^2$ and 2.5 $\mathrm{k\Omega }$ at $1\times 10^{-8}$ $\Omega \mathrm{c}{\mathrm{m}}^2$ (computed), comparable to or above the channel resistance of a small transistor. This is why imec describes contact resistance as threatening to become the dominating parasitic at the N7 and N5 nodes and why it targets values below $1\times 10^{-9}$ $\Omega \mathrm{c}{\mathrm{m}}^2$ for highly doped n-Si and p-SiGe. Its 2017 record PMOS result, below $1\times 10^{-9}$ $\Omega \mathrm{c}{\mathrm{m}}^2$, used a shallow Ga implant into p-SiGe and a nanosecond laser anneal, which it attributes to Ge and Ga segregation at the surface, and was measured on multi-ring circular TLM structures. Reference: imec, ‘imec achieves record-low source/drain contact resistivity for PMOS transistors’, press release, 2017 Symposia on VLSI Technology and Circuits, Kyoto (8 June 2017) (fetch-tool summary).

Ques: How is specific contact resistivity extracted from TLM structures, and what goes wrong?

Stavitski et al. used the Scott method: the contact resistance per width follows from $(R_n-R_{ref})W/n$ for chains of $n$ silicided segments, and fitting $R_c=2\sqrt{{\rho }_c{R}_s}\tanh (L/2L_c)/W$ against segment length gives the saturation value and the transfer length, from which ${\rho }_c=L_c{R}_{0}W/2$. The main errors were the small difference $R_n-R_{ref}$ at low resistance, reduced with more segments; lateral silicide growth of 0.025 to 0.05 $\mu \mathrm{m}$ per side, which had to be measured by TEM; merging of the shortest segments; 20 to 30 per cent thickness nonuniformity of NiSi on arsenic-doped silicon; and nonlinear I-V at intermediate doping. They recommend at least 0.2 $\mu \mathrm{m}$ between the smallest segments and checking two widths for consistency. Reference: N. Stavitski, M. J. H. van Dal, A. Lauwers, C. Vrancken, A. Y. Kovalgin and R. A. M. Wolters, ‘Evaluation of Transmission Line Model Structures for Silicide-to-Silicon Specific Contact Resistance Extraction’, IEEE Transactions on Electron Devices 55(5), 1170-1176 (2008) (University of Twente copy) (fetch-tool summary).

Ques: Is ALD TaN about 2000 or 5000 microohm centimetres?

Both values are reported by overlapping groups for different processes. Zhang et al. give about 2000 $\mu \Omega \mathrm{cm}$ for plasma-enhanced ALD TaN, with a density of about 11.6 $g/c{\mathrm{m}}^3$, deposited at 275 ${}^{\circ }\mathrm{C}$, while van der Straten et al. give about 5000 $\mu \Omega \mathrm{cm}$ for their ALD TaN a year later. The PVD values agree, about 240 and 250 $\mu \Omega \mathrm{cm}$ for Ta-rich films. ALD TaN resistivity depends strongly on nitrogen content, plasma use and density, and nitrogen-rich, less dense films are more resistive (background knowledge), so the two values most likely describe different ALD processes rather than an error (my reading). The 2000 $\mu \Omega \mathrm{cm}$ value applies to plasma-enhanced ALD, and 5000 $\mu \Omega \mathrm{cm}$ to the films of the 2014 study. Reference: X. Zhang, O. van der Straten, T. Bolom, M. He, J. Maniscalco and D. Edelstein, ‘X-ray Characterization of PEALD versus PVD Tantalum Nitride Barrier Deposition and the Impact on Via Contact Resistance’, 224th ECS Meeting, Abstract 1883 (2013) (fetch-tool summary); O. van der Straten, X. Zhang, K. Motoyama, C. J. Penny, J. Maniscalco and S. Knupp, ‘ALD and PVD tantalum nitride barrier resistivity and their significance in via resistance trends’, ECS Transactions 64(9), 117 (2014), doi:10.1149/06409.0117ecst (abstract only).

Ques: Why does a high-resistivity ALD barrier lower via resistance?

Van der Straten et al. found via resistance about 28 per cent lower with 3 $\mathrm{nm}$ of ALD TaN than with PVD TaN, and Zhang et al. 50 per cent lower with 10 $\mathring{\mathrm{A}}$ of PEALD TaN, although ALD TaN is 8 to 20 times more resistive. A simple series model predicts the opposite: 1 $\mathrm{nm}$ of ALD TaN at 2000 to 5000 $\mu \Omega \mathrm{cm}$ on a 20 $\mathrm{nm}$ via bottom adds 50 to 125 $\Omega$, against 12.5 $\Omega$ for 2 $\mathrm{nm}$ of PVD TaN (computed). The likely explanation is that directional PVD leaves a thicker barrier at the via bottom and a thinner Cu core for the same sidewall coverage, while conformal ALD reaches the target thickness everywhere, and that bulk resistivity does not describe vertical conduction through a film only a few atoms thick (my reading). The measurements, not the series model, should guide barrier choice. Reference: O. van der Straten, X. Zhang, K. Motoyama, C. J. Penny, J. Maniscalco and S. Knupp, ‘ALD and PVD tantalum nitride barrier resistivity and their significance in via resistance trends’, ECS Transactions 64(9), 117 (2014), doi:10.1149/06409.0117ecst (abstract only); X. Zhang, O. van der Straten, T. Bolom, M. He, J. Maniscalco and D. Edelstein, ‘X-ray Characterization of PEALD versus PVD Tantalum Nitride Barrier Deposition and the Impact on Via Contact Resistance’, 224th ECS Meeting, Abstract 1883 (2013) (fetch-tool summary).

Ques: Does via resistance matter as much for performance as line resistance?

Less per relative change, according to Lanzillo et al. They found that line-edge roughness and line-height variation together add more than 25 per cent line resistance beyond the 5 $\mathrm{nm}$ node with about 8 per cent performance penalty, while barrier optimization that lowers via resistance by up to 26 per cent gives about 2 per cent uplift. That is about 0.32 per cent of performance per per cent of line resistance and 0.08 per cent per per cent of via resistance (computed). Vias are short and few compared with the total wire length on a critical path, so their share of the total resistance is smaller. In an assumed 20 $\mathrm{nm}$ via, 2 $\mathrm{nm}$ of PVD TaN would carry about 70 per cent of an 18 $\Omega$ via resistance (computed), so barrier changes are where via gains come from. Reference: N. A. Lanzillo, K. Motoyama, T. B. Hook and L. Clevenger, ‘Impact of Line and Via Resistance on Device Performance at the 5nm Gate All Around Node and beyond’, IITC 2018, doi:10.1109/IITC.2018.8430294 (abstract only).

Ques: Why does the transfer length limit how small a contact can usefully be made?

Because current enters a planar contact mainly within one transfer length of its edge. With $L_c=\sqrt{{\rho }_c/R_s}$, an assumed $1\times 10^{-8}$ $\Omega \mathrm{c}{\mathrm{m}}^2$ over silicon of 100 $\Omega /\mathrm{sq}$ gives 0.1 $\mu \mathrm{m}$ (computed), in the range of 0.08 to 0.122 $\mu \mathrm{m}$ that Stavitski et al. measured for PtSi. Contacts much longer than this give the saturation resistance $2\sqrt{{\rho }_c{R}_s}/W$ and gain nothing from extra length. Contacts much shorter, as at advanced nodes, use their whole area, and their resistance rises as ${\rho }_c/A_c$ when they shrink (background knowledge). This is why scaled contacts require ${\rho }_c$ itself to fall, through higher active doping, lower Schottky barriers or interface dipoles, rather than through layout (my reading). Reference: N. Stavitski, M. J. H. van Dal, A. Lauwers, C. Vrancken, A. Y. Kovalgin and R. A. M. Wolters, ‘Evaluation of Transmission Line Model Structures for Silicide-to-Silicon Specific Contact Resistance Extraction’, IEEE Transactions on Electron Devices 55(5), 1170-1176 (2008) (University of Twente copy) (fetch-tool summary); imec, ‘imec achieves record-low source/drain contact resistivity for PMOS transistors’, press release, 2017 Symposia on VLSI Technology and Circuits, Kyoto (8 June 2017) (fetch-tool summary).

Related pages in this vault: RC Delay and Repeater Insertion, Interconnect Joule Heating, Wire Resistance and Size Effects, Schottky Diode, Wire Capacitance and Low-k Dielectrics, Power Delivery Networks, Metal Contact Materials, Metal Semiconductor Contacts, E-Beam Inspection and Defect Review, Picosecond Ultrasonic Film Metrology, Optical Emission Spectroscopy Endpoint (OES), CMP Polisher.