Ferroelectric Field Effect Transistor (FeFET)

1. Theory

• Definition: A ferroelectric field-effect transistor (FeFET) is a MOSFET with a ferroelectric layer (doped $\mathrm{Hf}{\mathrm{O}}_2$ or a perovskite) in its gate stack, storing a bit as the polarization direction that sets the threshold voltage.
• One-transistor cell: The cell is a single transistor, and the read is a non-destructive drain-current measurement, unlike the capacitor-based FeRAM.
• Gate stacks: MFIS (metal-ferroelectric-insulator-semiconductor) with an interfacial layer, or MFMIS with an internal metal electrode.
• Threshold shift: Polarization shifts $V_T$, but the memory window is limited to about $2V_c=2E_c{t}_{FE}$ (about 2 V for 10 nm $\mathrm{Hf}{\mathrm{O}}_2$).
• Interfacial layer: A thin $\mathrm{Si}{\mathrm{O}}_2$ or SiON layer is needed for a good silicon interface but takes part of the gate voltage and causes depolarization.
• $\mathrm{Hf}{\mathrm{O}}_2$ advantage: Doped $\mathrm{Hf}{\mathrm{O}}_2$ is ferroelectric at a few nanometres and fits existing high-k metal gate processes, unlike earlier perovskite FeFETs.

2. Working Principle

• Write: A gate pulse exceeding the coercive voltage (plus the interlayer drop) sets the polarization up or down.
• Read: At a read voltage between the two thresholds, the low-$V_T$ state conducts much more than the high-$V_T$ state.
• Voltage division: The gate voltage splits across the ferroelectric, the interlayer and the silicon surface potential.
• Depolarization: Without enough compensating charge, the field inside the ferroelectric opposes the polarization and degrades retention.
• Multi-level states: Partial switching leaves intermediate thresholds, enabling analog or multi-bit storage.
• Grain statistics: In scaled devices only a few grains sit under the gate, so switching occurs in visible steps and threshold spread grows.
• On/off ratio: Limited by leakage and threshold distribution rather than by the subthreshold slope.

3. Applications

• Current status: Emerging technology demonstrated in 28 nm-class embedded processes; not yet in high-volume products.
• Embedded non-volatile memory (target): Low-power, fast-write eNVM for microcontrollers and IoT chips at advanced logic nodes.
• In-memory and neuromorphic computing (research): Multi-level FeFETs as analog synaptic weights.

Name	Formula	Related Formulae	Variables/Constants
Gate stack capacitance and baseline threshold voltage	$\frac{1}{C_{stack}}=\frac{t_{FE}}{{\epsilon }_0{\epsilon }_b}+\frac{t_{IL}}{{\epsilon }_0{\epsilon }_{IL}}$	$V_{T,0}=V_{FB}+2{\varphi }_F+\frac{\sqrt{4{\epsilon }_{s}q{N}_A{\varphi }_F}}{C_{stack}}$	$\begin{array}{r}{C}_{stack}:capacitanceperunitareaof\\ theferroelectricandinterlayerin\\ series,withtheferroelectrictreatedas\\ alineardielectric\end{array}$ $\begin{array}{r}{t}_{FE},{\epsilon }_b:thicknessand\\ backgroundrelativepermittivityofthe\\ ferroelectric\end{array}$ $\begin{array}{r}{t}_{IL},{\epsilon }_{IL}:thicknessand\\ relativepermittivityoftheinterfacial\\ layerbetweentheferroelectricandthe\\ silicon\end{array}$ $\begin{array}{r}{V}_{T,0}:thresholdvoltageofthe\\ unpolarizedstack(zeropolarization);\\ thepolarizedstatessitoneitherside\\ ofit,soitmarksthecentreofthe\\ window\end{array}$ $\begin{array}{r}{V}_{FB},{\varphi }_F,N_A,{\epsilon }_s:\\ flat-bandvoltage,Fermipotential,doping\\ andpermittivityofthep-typechannel\\ (asontheLongChannelMOSFETpage),\\ with{V}_{FB}=({\Phi }_M-{\Phi }_S)/qminusanyfixed\\ interfacechargeover{C}_{stack}\end{array}$
Threshold shift from a fixed polarization	$\Delta V_T=-\frac{P{t}_{FE}}{{\epsilon }_0{\epsilon }_b}$	$V_T=V_{T,0}+\Delta V_T$ $\begin{array}{r}{\text{MW}}_{fixed}=\frac{2P_r{t}_{FE}}{{\epsilon }_0{\epsilon }_b}\end{array}$	$\begin{array}{r}\Delta V_T:thresholdshiftcausedbya\\ polarizationPpointingtowardthe\\ channel(negativeshift)orawayfromit\\ (positiveshift)\end{array}$ $\begin{array}{r}P:polarizationoftheferroelectric,\\ whichgivesaboundsheetchargeatthe\\ interfacenexttotheinterlayer\end{array}$ $\begin{array}{r}M{W}_{fixed}:memorywindowobtainedifthe\\ polarizationstayedat\pm P_{r}without\\ anycompensatingcharge\end{array}$ $P_r:remanentpolarization$ $\begin{array}{r}(thefixed-polarizationwindowisalarge\\ overestimate,becausetheboundchargeis\\ screenedbychargeinthechanneland\\ thegate;thewindowthatisreachedis\\ limitedbythecoercivevoltage.For\\ P_r=20\mu C/c{m}^2,t_{FE}=10nmand\\ {\epsilon }_b=30itgivesabout15V,against\\ measuredwindowsof1to2V)\end{array}$
Memory window limit	$MW\lesssim 2V_c=2E_c{t}_{FE}$	$MW=V_{T,HVT}-V_{T,LVT}$	$\begin{array}{r}MW:memorywindow,thedifferencebetween\\ thethresholdvoltagesofthe\\ high-threshold(HVT)andlow-threshold\\ (LVT)states\end{array}$ $V_c:coercivevoltageoftheferroelectriclayer$ $E_c:coercivefieldofthethinfilm$ $t_{FE}:ferroelectricthickness$ $\begin{array}{r}(Miller-McWhorterresult:atthreshold\\ thechannelneedsonlyasmallcharge,\\ soDissmallcomparedwith{P}_{r}andthe\\ ferroelectricsitsonitsloopwherethe\\ branchcrossesP\approx 0,atabout+E_{c}onone\\ branchand-E_{c}ontheother;thetwo\\ thresholdsthereforedifferbyabout2V_c.\\ Theinterlayerandincompletesaturation\\ maketherealwindowsmaller)\end{array}$
Voltage division in the gate stack	$V_G=V_{FE}+V_{IL}+{\psi }_s+\left({\Phi }_M-{\Phi }_S\right)/q$	$D={\epsilon }_0{\epsilon }_b{E}_{FE}+P={\epsilon }_0{\epsilon }_{IL}{E}_{IL}=-Q_s$ $V_{IL}=\frac{D{t}_{IL}}{{\epsilon }_0{\epsilon }_{IL}}$	$V_G:gatevoltage$ $\begin{array}{r}{V}_{FE},V_{IL}:voltagesacrossthe\\ ferroelectricandtheinterlayer\end{array}$ ${\psi }_s:surfacepotentialofthechannel$ $\begin{array}{r}{\Phi }_M,{\Phi }_S:workfunctionsofthe\\ gatemetalandthesemiconductor\end{array}$ $\begin{array}{r}D:electricdisplacement,continuous\\ throughthestackifthereisno\\ interfacecharge\end{array}$ $\begin{array}{r}{E}_{FE},E_{IL}:electricfieldsinthe\\ ferroelectricandtheinterlayer\end{array}$ $\begin{array}{r}{Q}_s:chargeperunitareainthe\\ semiconductor(depletionplusinversionor\\ accumulationcharge)\end{array}$
Write voltage	$V_{G,write}\approx V_c+\frac{\left(P_r+{\epsilon }_0{\epsilon }_b{E}_c\right)t_{IL}}{{\epsilon }_0{\epsilon }_{IL}}+{\psi }_s$	$E_{IL}=\frac{D}{{\epsilon }_0{\epsilon }_{IL}}$	$\begin{array}{r}{V}_{G,write}:gatevoltageneededto\\ completetheswitchingto+P_r(atthe\\ startofswitchingPisstill-P_r,Dis\\ negativeandlessvoltageisneeded;as\\ thepolarizationreversesthechannelmust\\ supplytheextracharge2P_r)\end{array}$ $\begin{array}{r}{V}_c:coercivevoltageacrossthe\\ ferroelectriclayer\end{array}$ $\begin{array}{r}{P}_r+{\epsilon }_0{\epsilon }_b{E}_c:\\ approximatedisplacementDattheend\\ oftheswitching(fieldstillnear{E}_c)\end{array}$ $\begin{array}{r}{t}_{IL},{\epsilon }_{IL}:thicknessand\\ permittivityoftheinterlayer\end{array}$ $\begin{array}{r}{\psi }_s:surfacepotential,about2{\varphi }_F\\ ininversionandnearzeroin\\ accumulation\end{array}$ $\begin{array}{r}{E}_{IL}:fieldintheinterlayerduring\\ thewrite,whichishighandstresses\\ theinterlayer(athininterlayerwitha\\ largerpermittivitylowersthewrite\\ voltageandthestress)\end{array}$
Depolarization field at zero gate voltage	$E_{FE}=\frac{D-P}{{\epsilon }_0{\epsilon }_b}$	$E_{FE}\to -\frac{P}{{\epsilon }_0{\epsilon }_b}(D\to 0)$ $V_{FE}+V_{IL}+{\psi }_s+\left({\Phi }_M-{\Phi }_S\right)/q=0$	$\begin{array}{r}{E}_{FE}:fieldintheferroelectric,which\\ isoppositetothepolarizationwhenD<P\end{array}$ $\begin{array}{r}D:displacementinthestack,equalto\\ -Q_s,soitissetbythechargein\\ thesemiconductor(andbythecharge\\ thatcanbetrappedattheinterfaces)\end{array}$ $P:polarizationoftheferroelectric$ $\begin{array}{r}(thepolarizationisstableonlyifthe\\ screeningchargebringsDclosetoP;a\\ thickinterlayerorweakscreeninggives\\ afieldthatdrivesthepolarization\\ back;D\to 0istheworstcase,sincethe\\ depletionchargekeepsDnonzero)\end{array}$
Metal-ferroelectric-metal-insulator-semiconductor (MFMIS) charge balance	$A_{FE}{D}_{FE}=A_{MOS}{D}_{MOS}$	$r_A=\frac{A_{FE}}{A_{MOS}}$ $V_G=V_{FE}+V_{MOS}$	$\begin{array}{r}{A}_{FE},A_{MOS}:areasofthe\\ ferroelectriccapacitorandofthe\\ transistorgatestackconnectedbythe\\ floatinginternalmetal\end{array}$ $\begin{array}{r}{D}_{FE},D_{MOS}:displacementinthe\\ ferroelectricandinthetransistorgate\\ insulator\end{array}$ $\begin{array}{r}{r}_A:arearatio,whichsetshowthe\\ gatevoltageissharedbetweenthetwo\\ stacks\end{array}$ $\begin{array}{r}{V}_{FE},V_{MOS}:voltagesacrossthe\\ ferroelectriccapacitorandacrossthe\\ transistorstack(insulatorplus\\ semiconductor)\end{array}$ $\begin{array}{r}(theinternalmetalremovestheinterface\\ betweentheferroelectricandthe\\ semiconductor,andthearearatiocanbe\\ chosenfreely;asmaller{r}_{A}givesalarger\\ D_{FE}forthesameMOScharge,sothe\\ ferroelectricsaturateswithlesscharge\\ inthechannelandtakesalargershare\\ of{V}_G)\end{array}$
Read current and the ratio of the two states	$I_D={\mu }_n{C}_{stack}\frac{W}{L}\left(V_{read}-V_T-\frac{V_{DS}}{2}\right)V_{DS}$	$\frac{I_{LVT}}{I_{HVT}}\approx 10^{MW/S}$ $V_{read}=\frac{V_{T,HVT}+V_{T,LVT}}{2}$	$\begin{array}{r}{I}_D:draincurrentinthelinearregion\\ for{V}_{read}>V_T\end{array}$ $\begin{array}{r}{V}_T:thresholdvoltageofthestatethat\\ isread(V_{T,LVT}or{V}_{T,HVT})\end{array}$ $\begin{array}{r}{I}_{LVT}/I_{HVT}:ratioofthesubthreshold\\ currentsofthetwostatesatthesame\\ gatevoltage\end{array}$ $S:subthresholdswinginvoltsperdecade$ $V_{read}:readvoltageinthemiddleofthewindow$ $\begin{array}{r}(theratioisanidealsubthreshold\\ value;inpracticeleakageandthe\\ spreadofthethresholdslimitit.C_{stack}\\ with{\epsilon }_{b}istherightsmall-signal\\ gatecapacitanceonlywhilethereaddoes\\ notdisturbthepolarization)\end{array}$
Partial switching and analog states	$V_T=V_{T,HVT}-fMW$	$f=\frac{\Delta P}{2P_s}=1-\exp \left[-{\left(\frac{t}{\tau }\right)}^n\right]$	$\begin{array}{r}f:fractionoftheferroelectric\\ polarizationthathasswitchedtothe\\ low-thresholddirection\end{array}$ $MW:memorywindow$ $\begin{array}{r}\Delta P,P_s:switchedpolarizationand\\ saturationpolarization\end{array}$ $\begin{array}{r}t,\tau ,n:pulseduration,\\ characteristicswitchingtimeandexponent\\ oftheKAImodeloftheFeRAMpage\end{array}$ $\begin{array}{r}(theintermediatethresholdscanbeused\\ asmulti-levelstatesorasanalog\\ weights)\end{array}$
Grain statistics in a scaled device	${\sigma }_f=\sqrt{\frac{f\left(1-f\right)}{N_g}}$	$N_g=\frac{WL}{A_{grain}}$ ${\sigma }_{V_T}=MW{\sigma }_f$	$\begin{array}{r}{\sigma }_f:standarddeviationofthe\\ switchedfractionamongdeviceswith{N}_g\\ independentdomains(binomialstatistics)\end{array}$ $f:averageswitchedfraction$ $\begin{array}{r}{N}_g:numberofgrainsorswitching\\ domainsinthechannelareaWbyL\end{array}$ $\begin{array}{r}{A}_{grain}:averageareaofone\\ ferroelectricgrain(afewtensof\\ nanometersacrossindopedHf{O}_2)\end{array}$ $\begin{array}{r}(independent,equal-weightdomainsanda\\ linear{V}_T(f)assumed;adomainoverthe\\ currentpercolationpathweighsmore)\end{array}$ $\begin{array}{r}{\sigma }_{V_T}:resultingstandarddeviation\\ ofthethresholdvoltage\end{array}$ $\begin{array}{r}(thevariationgrowsasthetransistor\\ areaapproachesthegrainsize)\end{array}$

Important Questions

Ques: How does a FeFET store and read a bit, and how does it differ from FeRAM?

In a FeFET the ferroelectric is part of the gate stack of a transistor. The direction of the polarization changes the threshold voltage ($\Delta V_T=-P{t}_{FE}/{\epsilon }_0{\epsilon }_b$ in the fixed-polarization picture), so a gate voltage between the two thresholds gives a high or low drain current. The read is non-destructive and uses only the transistor current, in contrast to FeRAM where the charge of the capacitor is sensed and the data must be rewritten. The write is by a gate pulse that exceeds the coercive voltage, and the cell has the area of one transistor. Reference: T.P. Ma and J.-P. Han, “Why is nonvolatile ferroelectric memory field-effect transistor still elusive?,” IEEE Electron Device Lett. 23, 386 (2002).

Ques: Why is the memory window of a FeFET limited to about twice the coercive voltage?

The polarization can be reversed only when the voltage across the ferroelectric exceeds $V_c=E_c{t}_{FE}$, and in the read state the polarization must be stable at zero gate voltage. At threshold the channel needs only a small charge, so the displacement $D$ is small compared with $P_r$ and the ferroelectric sits near the point where its loop crosses $P\approx 0$, which is at $+E_c$ on one branch and $-E_c$ on the other. The two thresholds therefore differ by about $2V_c$, so $MW\lesssim 2E_c{t}_{FE}$ (the Miller-McWhorter result). The fixed-polarization value $2P_r{t}_{FE}/{\epsilon }_0{\epsilon }_b$ is several times larger, but it would need the bound charge to remain unscreened. In an HfO${}_2$ film with $E_c\approx 1$ MV/cm and $t_{FE}=10$ nm the limit is about 2 V. Reference: S.L. Miller and P.J. McWhorter, “Physics of the ferroelectric nonvolatile memory field effect transistor,” J. Appl. Phys. 72, 5999 (1992); T.P. Ma and J.-P. Han, IEEE Electron Device Lett. 23, 386 (2002); T. Mikolajick et al., “Next generation ferroelectric materials for semiconductor process integration and their applications,” J. Appl. Phys. 129, 100901 (2021).

Ques: Why is an interfacial layer needed, and what does it do to the gate stack?

Ferroelectric oxides react with silicon and form a poor interface, so in practice a thin insulating interlayer (SiO${}_2$ or SiON, a few nanometers) sits between the ferroelectric and the silicon (MFIS). The interlayer is in series with the ferroelectric, so it takes a voltage $V_{IL}=D{t}_{IL}/{\epsilon }_0{\epsilon }_{IL}$ and raises the gate voltage needed for writing. The field in the interlayer is large during the write, which stresses it. The depolarization field itself comes from incomplete compensation of the bound polarization charge; the interlayer makes it worse because it separates the ferroelectric from the screening charge in the silicon, so after the gate voltage is removed part of the field falls across the ferroelectric in the direction opposing $P$. A high-permittivity interlayer or an internal metal (MFMIS) reduces these effects. Reference: T.P. Ma and J.-P. Han, IEEE Electron Device Lett. 23, 386 (2002).

Ques: What is the depolarization field and why does it matter for the stored state?

With the gate at 0 V the ferroelectric field is $E_{FE}=(D-P)/{\epsilon }_0{\epsilon }_b$. If the semiconductor and the interfaces supply enough compensating charge for $D\approx P$, the field is small and the state is stable. If $D\to 0$ the field becomes $-P/{\epsilon }_0{\epsilon }_b$, which is opposed to the polarization and large enough to depolarize it. A thin interlayer, a high permittivity, a conductive path in the film and trapped charge at the interface all increase the compensation. Retention and its time dependence are covered on the reliability pages. Reference: R. Mehta, B.D. Silverman and J.T. Jacobs, J. Appl. Phys. 44, 3379 (1973); T.P. Ma and J.-P. Han, IEEE Electron Device Lett. 23, 386 (2002).

Ques: How are multi-level states and the device variation determined?

A pulse that switches only a fraction $f$ of the ferroelectric leaves an intermediate threshold, $V_T=V_{T,HVT}-fMW$, so the amplitude or duration of the pulse can program several levels. In a transistor of area $WL$ the number of independent grains is $N_g=WL/A_{grain}$, so the switched fraction has a binomial spread ${\sigma }_f=\sqrt{f(1-f)/N_g}$ and a threshold spread ${\sigma }_{V_T}=MW{\sigma }_f$. When the channel only holds a few grains, each domain gives a visible step of the threshold voltage, which limits the number of levels and the uniformity of scaled devices. Reference: H. Mulaosmanovic et al., “Switching kinetics in nanoscale hafnium oxide based ferroelectric field-effect transistors,” ACS Appl. Mater. Interfaces 9, 3792 (2017).

Ques: How does the HfO${}_2$ FeFET compare with the perovskite FeFET?

The early FeFETs used perovskite ferroelectrics (PZT, SBT) on silicon, which needed thick films and buffer layers, gave large interface reactions and had short retention, so they did not reach production. Doped HfO${}_2$ is ferroelectric in films of only a few nanometers, is already used in high-k metal gate processes, and can be integrated in the gate stack of a planar transistor with little change. FeFETs of this kind have been demonstrated in a 28 nm high-k metal gate process. The drawbacks are the limited window of about $2V_c$ (a few volts or less) and the high field in the interlayer. Reference: J. Müller et al., “Ferroelectric hafnium oxide based materials and devices: assessment of current status and future prospects,” ECS J. Solid State Sci. Technol. 4, N30 (2015); S. Trentzsch et al., “A 28nm HKMG super low power embedded NVM technology based on ferroelectric FETs,” IEDM Tech. Dig., 2016, p. 294.

Ques: Why is the on/off ratio smaller in practice than $10^{MW/S}$?

At a read voltage in the middle of the window the subthreshold current of the low-threshold state is $10^{MW/S}$ higher than that of the high-threshold state. For a window of 1.5 V and a swing of 80 mV/dec this would exceed ten orders of magnitude, but the measured ratio is typically a few orders. The high-threshold state is limited by the gate leakage through the thin stack, the junction leakage and the tail of the threshold distribution, and the low-threshold state by the series resistance and the spread of the threshold. The ratio is therefore set by the leakage floor and the distribution, not by the subthreshold slope. Reference: S.M. Sze and Kwok K. Ng, Physics of Semiconductor Devices, 3rd ed., Wiley, 2007.

Related pages in this vault: Ferroelectric Random Access Memory (FeRAM), Ferroelectric NAND and 3D Ferroelectric Memory (Vertical FeFET and Stacked FeRAM), Piezoresponse Force Microscope (PFM), Ferroelectric Tunnel Junction (FTJ), Ferroelectric Random Access Memory (FeRAM, PZT and HfO2), Organic Ferroelectric Polymer Memory (PVDF and P(VDF-TrFE)), Steep Slope FETs (Tunnel FET, Impact Ionization MOS, Negative Capacitance FET), Floating Body Random Access Memory (Capacitorless 1T DRAM), Organic Charge Trap Transistor Memory (Polymer Electret and Nanoparticle).