Charge Trap Flash Memory (SONOS, TANOS and 3D NAND)

1. Theory

Definition: A charge-trap flash cell is an n-channel transistor whose bit is stored as electrons in discrete traps of a dielectric layer (usually silicon nitride) between a tunnel layer and a blocking layer.
Variants: SONOS and MONOS (oxide blocking layer), TANOS ( $A l_{2} O_{3}$ blocking layer with a TaN gate) and BE-SONOS (bandgap-engineered ONO tunnel layer); the vertical arrangement forms 3D NAND.
Localized charge: Each trapped electron stays put, so a single oxide defect discharges only nearby traps rather than the whole storage layer.
Thinner tunnel layer: Localized storage tolerates a thinner tunnel layer, allowing lower program voltages, and removes floating-gate-to-floating-gate coupling.
Charge centroid: The threshold shift depends on where the trapped charge sits; charge moving toward the gate lowers the window even without loss.
Conformal film: A thin ONO film can be deposited along a hole wall, which is why charge trap storage enables 3D NAND.

2. Working Principle

Program: Fowler-Nordheim tunnelling (or hot-carrier injection) sends electrons through the tunnel layer into nitride traps, raising $V_{T}$ .
Erase: A large negative gate voltage pulls trapped electrons out, or injects holes to neutralize them.
Erase saturation: Electron back-injection from the gate through the blocking layer stops erase in SONOS; TANOS (high-k blocking, high work-function gate) and BE-SONOS fix this.
Retention loss: Thermal (Poole-Frenkel) emission, trap-to-band tunnelling through the tunnel layer and charge hopping within the nitride.
3D NAND gate-all-around cell: The cylindrical geometry concentrates the field at the channel, improving program and erase efficiency.
Layer-count limit: Series string resistance, high-aspect-ratio hole etching and stack stress limit stacking, so layers are built in tiers.
Multi-level cells: The window must hold $2^{b}$ threshold distributions with margins, so each extra bit halves the allowed width.

3. Applications

Solid-state drives: 3D NAND (TLC and QLC) in consumer, enterprise and data-centre SSDs.
Mobile and removable storage: Smartphone storage (UFS, eMMC), memory cards and USB drives.
Embedded non-volatile memory: SONOS cells embedded in microcontrollers and secure ICs.

Name	Formula	Related Formulae	Variables/Constants
Gate stack equivalent oxide thickness	$E O T_{t o t} = E O T_{b l k} + E O T_{N} + E O T_{t u n}$	$E O T_{i} = t_{i} \frac{ε _{S i O_{2}}}{ε _{r, i}}$ $C_{s t a c k} = \frac{ε _{0} ε _{S i O_{2}}}{E O T _{t o t}}$	$E O T_{t o t} : e q u i v a l e n t o x i d e t hi c k n ess o f t h e w h o l e g a t e s t a c k$ $E O T_{b l k}, E O T_{N}, E O T_{t u n} : e q u i v a l e n t o x i d e t hi c k n esses o f t h e b l oc k in g d i e l ec t r i c, t h e t r a pp in g ni t r i d e an d t h e t u nn e l d i e l ec t r i c$ $t_{i}, ε_{r, i} : p h y s i c a l t hi c k n ess an d r e l a t i v e p er mi tt i v i t y o f l a y er i$ $C_{s t a c k} : c a p a c i t an ce p er u ni t a r e a o f t h e co m pl e t e s t a c k (t h e l a y er s a r e in ser i es)$ $(t h e or d er f r o m t h e g a t e i s b l oc k in g l a y er, c ha r g e t r a pp in g l a y er, t u nn e l l a y er, c hann e l)$
Threshold shift from trapped charge	$Δ V_{T} = - \frac{Q _{t} E O T _{g}}{ε _{0} ε _{S i O_{2}}}$	$Q_{t} = - q n_{t}$ $E O T_{g} = E O T_{b l k} + \frac{ε _{S i O_{2}}}{ε _{N}} x_{c}$	$Δ V_{T} : t h r es h o l d v o l t a g e s hi f t c a u se d b y t h e c ha r g e in t h e t r a pp in g l a y er$ $Q_{t} : t r a pp e d c ha r g e p er u ni t a r e a (n e g a t i v e f or t r a pp e d e l ec t r o n s)$ $n_{t} : a r e a l d e n s i t y o f t r a pp e d e l ec t r o n s$ $E O T_{g} : e q u i v a l e n t o x i d e t hi c k n ess b e tw ee n t h e g a t e an d t h e ce n t r o i d o f t h e t r a pp e d c ha r g e$ $x_{c} : d i s t an ce o f t h e c ha r g e ce n t r o i d f r o m t h e b l oc k in g d i e l ec t r i c / ni t r i d e in t er f a ce$ $(c ha r g e n e a r t h e g a t e i s scr ee n e d b y i t an d s hi f t s t h e t h r es h o l d l i ttl e, w hi l e c ha r g e n e a r t h e c hann e l s hi f t s i t t h e m os t)$
Field in the tunnel and blocking layers	$E_{t u n} = \frac{V _{G} - V _{F B} - ψ _{s}}{E O T _{t o t}} + \frac{Q _{t} E O T _{g}}{ε _{0} ε _{S i O_{2}} E O T _{t o t}}$	$E_{b l k} = \frac{V _{G} - V _{F B} - ψ _{s}}{E O T _{t o t}} - \frac{Q _{t} E O T _{c}}{ε _{0} ε _{S i O_{2}} E O T _{t o t}}$ $E O T_{c} = E O T_{t o t} - E O T_{g}$	$E_{t u n} : f i e l d in t h e t u nn e l l a y er, in o x i d e - e q u i v a l e n t u ni t s an d p os i t i v e f r o m t h e g a t e t o w a r d t h e c hann e l$ $E_{b l k} : f i e l d in t h e b l oc k in g l a y er, in t h e s am e u ni t s$ $V_{G} : g a t e v o l t a g e$ $V_{F B} : f l a t - ban d v o l t a g e o f t h e u n c ha r g e d s t a c k$ $ψ_{s} : s u r f a ce p o t e n t ia l o f t h e c hann e l$ $E O T_{c} : e q u i v a l e n t o x i d e t hi c k n ess b e tw ee n t h e c ha r g e ce n t r o i d an d t h e c hann e l$ $(s t or e d e l ec t r o n s r e d u ce E_{t u n} an d in cr e a se E_{b l k} in a p os i t i v e - V_{G} p r o g r am o p er a t i o n; t h e t u nn e l c u r r e n t f o l l o w s t h e F o w l er - N or d h e im l a w o f t h e F l o a t in g G a t e F l a s h p a g e)$ $(f r o m G a u s s^{'} s l a w f or a c ha r g e s h ee t a t t h e ce n t r o i d; t h e r e l a t i o n s a r e l in e a r, so t h ey h o l d f or er a se (V_{G} < 0) a s w e l l . T h e p h y s i c a l f i e l d in a l a y er o f p er mi tt i v i t y ε_{r, i} i s t h e o x i d e - e q u i v a l e n t v a l u e t im es ε_{S i O_{2}} / ε_{r, i})$
Trap filling kinetics	$\frac{d n _{t}}{d t} = σ_{t} \frac{J _{inj}}{q} (N_{t} - n_{t}) - e_{n} n_{t}$	$n_{t} (t) \approx N_{t} [1 - exp (- σ_{t} \frac{J _{inj}}{q} t)] (e_{n} \approx 0)$	$n_{t} : a r e a l d e n s i t y o f f i l l e d t r a p s$ $N_{t} : a r e a l d e n s i t y o f a v ai l ab l e t r a p s in t h e ni t r i d e$ $σ_{t} : c a pt u r e cr oss sec t i o n o f a t r a p f or an inj ec t e d e l ec t r o n$ $J_{inj} : c u r r e n t d e n s i t y o f e l ec t r o n s inj ec t e d f r o m t h e c hann e l t h r o ug h t h e t u nn e l l a y er$ $e_{n} : e mi ss i o n r a t e o f a t r a pp e d e l ec t r o n$ $(t h e t r a pp e d c ha r g e s a t u r a t es a t N_{t} or w h e n E_{t u n} f a l l s b ec a u se o f t h e s t or e d c ha r g e; s in g l e t r a p l e v e l, co n s t an t σ_{t} an d u ni f or m N_{t} a ss u m e d)$
Thermal emission from traps (Poole-Frenkel)	$e_{n} = σ_{t} v_{t h} N_{C} exp [- \frac{E _{T} - Δ E _{P F}}{k _{B} T}]$	$Δ E_{P F} = \frac{q ^{3} E _{N}}{π ε _{0} ε _{\infty, N}}$	$e_{n} : e mi ss i o n r a t e o f an e l ec t r o n f r o m a t r a p t o t h e ni t r i d e co n d u c t i o n ban d$ $v_{t h} : t h er ma l v e l oc i t y o f e l ec t r o n s$ $N_{C} : e f f ec t i v e d e n s i t y o f s t a t es o f t h e ni t r i d e co n d u c t i o n ban d$ $E_{T} : t r a p d e pt h b e l o w t h e co n d u c t i o n ban d o f t h e ni t r i d e (e n er g y)$ $Δ E_{P F} : l o w er in g o f t h e t r a p ba r r i er b y t h e e l ec t r i c f i e l d E_{N} in t h e ni t r i d e (P oo l e - F r e nk e l e f f ec t)$ $ε_{\infty, N} : hi g h - f r e q u e n cy r e l a t i v e p er mi tt i v i t y o f t h e ni t r i d e$ $(t h e e mi ss i o n r a t e in cr e a ses w i t h t h e t e m p er a t u r e an d w i t h t h e f i e l d, w hi c h e x pl ain s t h e t h er ma l an d bia s d e p e n d e n ce o f t h e c ha r g e l oss; w h e t h er P oo l e - F r e nk e l e mi ss i o n or t r a p - a ss i s t e d t u nn e l l in g d o mina t es in t h e ni t r i d e i s s t i l l d e ba t e d)$ $k_{B} : B o l t z mann co n s t an t$
Trap-to-band tunnelling through the tunnel layer	$e_{t u n} = ν_{0} exp [- \frac{2 x _{t}}{ℏ} 2 m_{o x} q ϕ_{t}]$	$t_{r e t} \sim \frac{1}{e _{t u n}}$	$e_{t u n} : t u nn e l l in g r a t e o f a t r a pp e d e l ec t r o n ba c k t o t h e c hann e l$ $ν_{0} : a tt e m pt f r e q u e n cy$ $x_{t} : d i s t an ce f r o m t h e t r a p t o t h e t u nn e l l a y er / c hann e l in t er f a ce$ $m_{o x} : e l ec t r o n t u nn e l l in g ma ss in t h e t u nn e l d i e l ec t r i c$ $ϕ_{t} : ba r r i er h e i g h t see n b y t h e t r a pp e d e l ec t r o n t o w a r d t h e c hann e l, in v o l t s$ $t_{r e t} : c ha r a c t er i s t i c r e t e n t i o n t im e o f a t r a pp e d e l ec t r o n a t d e pt h x_{t}$ $(a t hi c k er t u nn e l l a y er g i v es an e x p o n e n t ia l l y l a r g er r e t e n t i o n t im e b u t r e d u ces t h e p r o g r am an d er a se c u r r e n t s; r ec t an g u l a r ba r r i er, n o f i e l d or t h er ma l a ss i s t an ce; f or a t r a p in s i d e t h e ni t r i d e t h e ba r r i er i s t h e t u nn e l o x i d e pl u s a l o w er ni t r i d e sec t i o n)$
Erase saturation by gate back-injection	$J_{g} = A_{g} E_{b l k}^{2} exp (- \frac{B _{g}}{E _{b l k}})$	$ϕ_{B, b l k} = Φ_{M} - χ_{b l k}$ $J_{g} (E_{b l k}) = J_{t u n} (E_{t u n}) \to erase saturation$	$J_{g} : c u r r e n t d e n s i t y o f e l ec t r o n s t u nn e l l in g f r o m t h e g a t e t h r o ug h t h e b l oc k in g l a y er in t o t h e ni t r i d e d u r in g er a se$ $E_{b l k} : f i e l d in t h e b l oc k in g l a y er$ $A_{g}, B_{g} : F o w l er - N or d h e im co n s t an t s o f t h e g a t e - b l oc k in g l a y er ba r r i er$ $Φ_{M} : w or k f u n c t i o n o f t h e g a t e m e t a l in v o l t s$ $χ_{b l k} : e l ec t r o n a f f ini t y o f t h e b l oc k in g d i e l ec t r i c in v o l t s$ $ϕ_{B, b l k} : ba r r i er h e i g h t f or g a t e e l ec t r o n s, in cr e a se d b y u s in g a hi g h w or k f u n c t i o n m e t a l g a t e$ $J_{t u n} : r e m o v a l c u r r e n t d e n s i t y (h o l e inj ec t i o n or e l ec t r o n e mi ss i o n) t h r o ug h t h e t u nn e l l a y er$
Field in a cylindrical (gate-all-around) cell	$E (r) = \frac{λ}{2 π ε r}$	$\frac{E _{t u n}}{E _{b l k}} = \frac{ε _{b l k}}{ε _{t u n}} \frac{r _{g}}{r _{c}}$ $C^{'} = \frac{2 π ε _{0}}{\sum _{i} l n ( r _{i + 1} / r _{i} ) / ε _{r, i}}$	$E (r) : e l ec t r i c f i e l d a t r a d i u s r in a d i e l ec t r i c o f p er mi tt i v i t y ε$ $λ : c ha r g e p er u ni t l e n g t h o n t h e c hann e l (an d t h e o pp os i t e c ha r g e o n t h e g a t e)$ $r_{c}, r_{g} : r a d i u s o f t h e c hann e l an d inn er r a d i u s o f t h e g a t e$ $ε_{t u n}, ε_{b l k} : p er mi tt i v i t i es o f t h e t u nn e l an d b l oc k in g l a y er s$ $C^{'} : c a p a c i t an ce p er u ni t l e n g t h o f t h e co n ce n t r i c s t a c k, w i t h l a y er i b e tw ee n r a d ii r_{i} an d r_{i + 1}$ $(f or e q u a l p er mi tt i v i t i es t h e f i e l d i s hi g h er in t h e t u nn e l l a y er t han in t h e b l oc k in g l a y er, w hi c h f a v or s p r o g r am an d er a se o v er g a t e ba c k - inj ec t i o n)$
String on-current of a vertical channel	$I_{s t r in g} \approx \frac{V _{B L}}{R _{S S L} + R _{GS L} + N _{W L} R _{ce l l}}$	$R_{ce l l} = \frac{L _{ce l l}}{μ _{e f f} C _{o x} 2 π r _{c} ( V _{p a ss} - V _{T} )}$	$I_{s t r in g} : r e a d c u r r e n t o f o n e v er t i c a l s t r in g o f N_{W L} ce l l s in ser i es$ $V_{B L} : bi t l in e v o l t a g e a cr oss t h e s t r in g$ $R_{S S L}, R_{GS L} : o n - r es i s t an ces o f t h e s t r in g an d g r o u n d se l ec t t r an s i s t or s$ $N_{W L} : n u mb er o f ce l l s (w or d l in e l a y er s) in ser i es$ $R_{ce l l} : o n - r es i s t an ce o f o n e u n se l ec t e d ce l l a t t h e p a ss v o l t a g e V_{p a ss}$ $L_{ce l l} : c hann e l l e n g t h o f o n e ce l l (t h e g a t e h e i g h t)$ $μ_{e f f} : e f f ec t i v e m o bi l i t y o f t h e p o l y s i l i co n c hann e l, w hi c h i s m u c h l o w er t han in s in g l e - cr y s t a l s i l i co n$ $C_{o x} : g a t e s t a c k c a p a c i t an ce p er u ni t a r e a a t t h e c hann e l r a d i u s$ $(t h e c u r r e n t f a l l s a s m or e l a y er s a r e s t a c k e d; s im pl e ser i es m o d e l t ha t i g n or es p o l y s i l i co n g r ain - b o u n d a r y ba r r i er s, t h e j u n c t i o n - f r ee f r in g in g - f i e l d so u r ce an d d r ain o f e a c h ce l l an d t h e f l o a t in g c hann e l p o t e n t ia l)$
Threshold window for multi-level cells	$M W = 2^{b} w + (2^{b} - 1) m$	$M W = ∣ Δ V_{T, p r o g} - Δ V_{T, er a se} ∣$ $N_{l e v e l} = 2^{b}$	$M W : t o t a l t h r es h o l d v o l t a g e r an g e n ee d e d f or b bi t s p er ce l l, f r o m t h e l o w er e d g e o f t h e l o w es t d i s t r ib u t i o n t o t h e u pp er e d g e o f t h e hi g h es t$ $b : n u mb er o f bi t s s t or e d p er ce l l (1 f or S L C, 2 f or M L C, 3 f or T L C, 4 f or Q L C)$ $w : w i d t h o f o n e t h r es h o l d v o l t a g e d i s t r ib u t i o n$ $m : ma r g in l e f t b e tw ee n n e i g hb or in g d i s t r ib u t i o n s$ $N_{l e v e l} : n u mb er o f t h r es h o l d v o l t a g e l e v e l s$ $(t h e a v ai l ab l e w in d o w i s l imi t e d b y t h e ma x im u m f i e l d an d b y t r a p s a t u r a t i o n, so m or e bi t s n ee d na r r o w er d i s t r ib u t i o n s)$

Important Questions

Ques: How does charge trap storage differ from a floating gate?

In a charge trap cell the charge is held in discrete traps in a dielectric layer, usually silicon nitride, between a tunnel layer and a blocking layer, instead of on a conducting polysilicon gate. Each trapped electron is localized, so a defect in the tunnel layer discharges only the traps nearby rather than the whole gate. This allows a thinner tunnel layer and a lower program voltage, and it removes the floating gate to floating gate coupling because the charge does not spread between neighboring cells. The disadvantage is that the stored charge has a lower density, so the window is smaller, and the trapped charge sits in a thin layer where it can be thermally emitted. Reference: M.H. White, D.A. Adams and J. Bu, “On the go with SONOS,” IEEE Circuits Devices Mag. 16(4), 22 (2000).

Ques: Why does the position of the trapped charge matter for the threshold shift?

A charge sheet at a distance from the gate induces a threshold shift $Δ V_{T} = - Q_{t} E O T_{g} / ε_{0} ε_{S i O_{2}}$ , where $E O T_{g}$ is the oxide-equivalent thickness between the gate and the charge. Charge at the gate interface is imaged in the gate and has no effect, and charge at the channel interface has the full effect of $- Q_{t} / C_{s t a c k}$ . The trapped charge is spread through the nitride, so the centroid $x_{c}$ determines the window, and charge moving toward the gate (or into the blocking layer) during retention reduces the window even without any loss of charge. Reference: J. Brewer and M. Gill (eds.), Nonvolatile Memory Technologies with Emphasis on Flash, Wiley-IEEE Press, 2008.

Ques: Why does erase saturate in a SONOS cell, and how do TANOS and BE-SONOS address it?

During erase a large negative gate voltage pulls out the trapped electrons, but it also raises the field in the blocking oxide, so electrons are injected from the gate into the nitride ( $J_{g}$ ). When $J_{g}$ equals the removal current through the tunnel layer, the threshold stops decreasing and the erase saturates at a threshold well above the neutral value. TANOS replaces the blocking oxide by Al $_{2}$ O $_{3}$ (higher permittivity, so a lower field) and the gate by TaN (high work function, so the barrier $Φ_{M} - χ_{b l k}$ is larger), which suppresses back-injection. BE-SONOS replaces the single tunnel oxide with a thin oxide-nitride-oxide stack that behaves as a thick barrier at low field (good retention) but as a thin one at high field (good erase). Reference: H.-T. Lue et al., “BE-SONOS: A bandgap engineered SONOS with excellent performance and reliability,” IEDM Tech. Dig., 2005, p. 547; Y. Shin et al., “A novel NAND-type MONOS memory using 63nm process technology for multi-gigabit flash EEPROMs,” IEDM Tech. Dig., 327 (2005).

Ques: What are the retention mechanisms of a charge trap cell?

Trapped electrons are lost in three ways. They are emitted thermally to the nitride conduction band (Poole-Frenkel, $e_{n}$ rising with temperature and field), and they tunnel directly from the trap into the channel through the tunnel layer ( $e_{t u n}$ , exponentially dependent on the distance $x_{t}$ ). They also move laterally and vertically within the nitride by hopping between traps, which shifts the centroid and changes the threshold. Shallow traps empty first, which gives the fast initial loss of threshold shift, and the loss rate falls with time. A thicker tunnel layer improves the retention but reduces the program speed. Reference: M.H. White, D.A. Adams and J. Bu, IEEE Circuits Devices Mag. 16(4), 22 (2000); J. Brewer and M. Gill (eds.), Nonvolatile Memory Technologies with Emphasis on Flash, Wiley-IEEE Press, 2008; J. Frenkel, Phys. Rev. 54, 647 (1938).

Ques: Why is charge trap storage used for 3D NAND?

In a vertical string the gates are stacked layers and the memory film is deposited conformally along the wall of a hole etched through the stack. The film is a thin oxide-nitride-oxide layer with polysilicon channel in the middle, which is possible with a charge trap film but not with a floating gate that would need separately patterned polysilicon islands. The gate-all-around geometry also raises the field at the channel: $E_{t u n} / E_{b l k} = (ε_{b l k} / ε_{t u n}) (r_{g} / r_{c})$ , which makes program and erase more efficient and cuts back-injection. The nitride layer is continuous between cells, so charge spreading between layers becomes a retention issue. Reference: H. Tanaka et al., “Bit cost scalable technology with punch and plug process for ultra high density flash memory,” Symp. VLSI Technol., 2007, p. 14; J. Jang et al., “Vertical cell array using TCAT (Terabit Cell Array Transistor) technology for ultra high density NAND flash memory,” Symp. VLSI Technol., 2009, p. 192.

Ques: What limits the number of layers that can be stacked?

The string current falls as $I_{s t r in g} \approx V_{B L} / (R_{S S L} + R_{GS L} + N_{W L} R_{ce l l})$ because the cells are in series and the polysilicon channel has low mobility, so the read current decreases with the number of layers. The aspect ratio of the channel hole also grows with the layers, and the hole must be etched with a uniform profile, so the cell dimensions vary between the top and the bottom of the stack. Finally the total stack height raises the mechanical stress and the cost of each deposition and etch step, so layers are often stacked in tiers. Reference: J. Jang et al., Symp. VLSI Technol., 2009, p. 192.

Ques: How many bits per cell can be stored?

The threshold window must hold $2^{b}$ distributions of width $w$ separated by margins $m$ , so $M W = 2^{b} w + (2^{b} - 1) m$ . At a fixed window every additional bit halves the allowed width, and at the same time the program verification must be finer, so programming takes longer. The window is limited by the largest field the stack can sustain, and in a charge trap cell also by trap saturation and erase saturation, which is why the number of stored bits per cell has grown more slowly than the number of layers. Reference: J. Brewer and M. Gill (eds.), Nonvolatile Memory Technologies with Emphasis on Flash, Wiley-IEEE Press, 2008.

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