1. Theory

  • Definition: Floating body RAM (capacitorless 1T-DRAM; Innovative Silicon’s commercial version was marketed as Z-RAM) stores a bit as excess holes in the electrically floating body of a single MOSFET, usually on SOI.
  • No capacitor: The cell is one transistor; the body’s own capacitance holds the charge.
  • Threshold modulation: Stored holes raise the body potential, which lowers by , so the 1 state conducts more current than the 0 state.
  • Body types: Partially depleted SOI bodies store holes in a neutral region; fully depleted and double-gate bodies need back-gate accumulation to form a hole well.
  • Small memory window: Junction forward current caps the body potential, limiting the threshold shift to a few hundred millivolts.

2. Working Principle

  • Write 1 by impact ionization: High drain voltage with the gate on makes channel electrons ionize near the drain, and the holes flow into the body.
  • Write 1 by GIDL: Negative gate and positive drain create band-to-band tunnelling at the gate-drain overlap without channel current.
  • Bipolar write: The parasitic N-P-N transistor amplifies the hole generation.
  • Write 0 (erase): Forward-biasing the body-drain junction, or coupling the body down through the gate, sweeps the holes out.
  • Read: A non-destructive drain-current measurement at a gate voltage between the two thresholds.
  • Retention and disturb: Holes leak through the junctions and recombine (tens to hundreds of ms, falling steeply with temperature), and accesses to neighbouring cells disturb the body potential.

3. Applications

  • Current status: Not in volume production; the small, temperature-sensitive window, threshold variation and disturb kept it from replacing the 1T1C cell.
  • Research interest: Dense embedded memory concepts on SOI, FinFET and nanowire bodies.
NameFormulaRelated FormulaeVariables/Constants
Body capacitance and gate coupling




Threshold voltage shift and memory window






Hole generation by impact ionization (write 1)




Hole generation by GIDL (write 1)




Parasitic bipolar amplification and latch condition




Equilibrium body potential (maximum stored charge)






Erase of the body (write 0)



Retention of the stored holes




Hole charge held by back-gate accumulation (fully depleted body)



Important Questions

Ques: What is stored in a floating body RAM cell, and how is it read?

A floating body cell is a single MOSFET (usually on silicon-on-insulator) whose neutral body is isolated from every contact, so excess holes placed in it stay there until they leak or recombine. The holes raise the body potential by , which lowers the threshold by , so the drain current is higher for the 1 state than for the 0 state. A read is simply a drain current measurement at a gate voltage between the two thresholds, which is non-destructive. The cell has no capacitor and occupies roughly the area of one transistor. Reference: S. Okhonin, M. Nagoga, J.M. Sallese and P. Fazan, “A capacitor-less 1T-DRAM cell,” IEEE Electron Device Lett. 23, 85 (2002); T. Ohsawa, K. Fujita, T. Higashi et al., “Memory design using a one-transistor gain cell on SOI,” IEEE J. Solid-State Circuits 37, 1510 (2002).

Ques: How are holes written into the body?

There are three methods. In impact ionization the cell is biased with a high drain voltage and an on-gate, so channel electrons ionize at the drain and the holes flow into the body (). In GIDL writing the gate is pulled negative and the drain positive, so band-to-band tunnelling at the gate-drain overlap generates electron-hole pairs and the holes flow into the body, which needs no channel current. In bipolar writing the holes from impact ionization act as base current of the parasitic n-p-n transistor, and the gain increases the total hole generation, with a regenerative condition at . Reference: S. Okhonin, M. Nagoga, J.M. Sallese and P. Fazan, IEEE Electron Device Lett. 23, 85 (2002); C. Hu, S.C. Tam, F.-C. Hsu, P.-K. Ko, T.-Y. Chan and K.W. Terrill, “Hot-electron-induced MOSFET degradation - model, monitor, and improvement,” IEEE Trans. Electron Devices 32, 375 (1985).

Ques: How are the holes removed, and what limits the stored charge?

Holes are removed by pulling the drain (or the source) negative so that the body-drain junction conducts, with the forward current sweeping the holes out, or by lowering the gate voltage so that capacitive coupling drops the body potential. The stored charge is capped by the same junctions: once the body potential rises to a few tenths of a volt, the forward current of the body-source and body-drain junctions equals the generation current, which sets . The memory window is therefore only a few hundred millivolts of threshold shift at most. Reference: S. Okhonin, M. Nagoga, J.M. Sallese and P. Fazan, IEEE Electron Device Lett. 23, 85 (2002).

Ques: What are the retention mechanisms, and why is the cell sensitive to disturb?

The stored holes escape through the forward-biased junctions (), recombine in the body by SRH processes, and are lost by gate-induced leakage, so retention is of the order of tens to hundreds of milliseconds and falls steeply as the temperature rises. The body is also coupled to the bitline and the gate of neighboring cells in an array: every access to another cell on the same bitline or wordline shifts the body potential a little, and these repeated pulses add or remove holes from cells that were not selected (disturb). Both effects reduce the already small memory window. Reference: T. Ohsawa, K. Fujita, T. Higashi et al., IEEE J. Solid-State Circuits 37, 1510 (2002).

Ques: How do partially depleted, fully depleted and double-gate bodies differ for this memory?

A partially depleted SOI device has a thick body with a neutral region where holes can be stored, and it is the simplest case, but it requires a thicker film and is hard to scale. A fully depleted device has no neutral region, so a hole well must be created by biasing the back gate into accumulation at the back surface, as in the double-gate design where is stored. Fin and nanowire bodies can be used, but their small volume means less charge, so the window shrinks with scaling. Bulk-silicon versions make the p-type body float by isolating it with a buried n-well underneath and shallow trench isolation at the sides, so no SOI wafer is needed. Reference: S.M. Sze and Kwok K. Ng, Physics of Semiconductor Devices, 3rd ed., Wiley, 2007; R. Ranica et al., “A one transistor cell on bulk substrate (1T-Bulk) for low-cost and high density eDRAM,” Symp. VLSI Technology, 128 (2004).

Ques: Why has this memory not replaced the 1T1C cell?

Floating body RAM has been limited by the small and temperature-sensitive memory window, the threshold voltage variation between cells (which is comparable to the window), the disturb between neighbors, and the need to bias the cell at high drain voltages for writing, which stresses the device and dissipates power. The 1T1C capacitor, by contrast, has a larger signal that is independent of the threshold voltage. Gain cells and, more recently, oxide-semiconductor transistors address the same goal of removing the capacitor with a different mechanism. Reference: T. Ohsawa, K. Fujita, T. Higashi et al., IEEE J. Solid-State Circuits 37, 1510 (2002).

Related pages in this vault: Dynamic Random Access Memory (DRAM), Silicon on Insulator (SOI) MOSFET, Gain Cell (2T and 3T eDRAM), Static Random Access Memory (SRAM), Fin Field Effect Transistor (FinFET), Static and Dynamic Random Access Memory (SRAM and DRAM), Schottky Barrier and Dynamic Threshold_MOSFET, EPROM, EEPROM and Legacy Non-Volatile Cells (FAMOS, FLOTOX, Split-Gate), Insulated Gate Bipolar Transistor (IGBT).