1. Theory
- Scope: Three-dimensional ferroelectric memory: the vertical gate-all-around FeFET in a 3D NAND-type string, and the stacked vertical ferroelectric capacitor of a 3D FeRAM.
- Ferroelectric NAND string: Same geometry as charge-trap 3D NAND, but the hole wall is coated with doped instead of an oxide-nitride-oxide film, storing the bit as polarization.
- Field-driven write: Polarization switches by field with no carrier injection, so program voltages are set by the coercive voltage, not an 8 to 10 MV/cm tunnelling field.
- Cylindrical field profile: The field falls as , so switching starts at the inner radius () and completes at the outer radius (), giving partial-switching states.
- Window bound: The memory window lies between about and , smaller than a charge-trap window.
- 3D FeRAM: Ferroelectric capacitors stacked along a vertical pillar; each cell is read destructively by its switched charge .
2. Working Principle
- String read: Unselected cells receive a pass voltage, and the selected cell’s threshold decides whether the string conducts.
- Pass-voltage window: must exceed the high-threshold state but stay below the switching onset, or it disturbs stored polarization.
- Program inhibit: Unselected strings are self-boosted so their ferroelectric layers see too little voltage to switch.
- Channel compensation: An n-type polysilicon or IGZO channel cannot supply holes, so a negative write forms depletion that takes part of the voltage.
- 3D FeRAM read: A switched cell releases about times its area of extra charge onto a long pillar bit line, then is rewritten.
- Scaling limits: Hole aspect ratio, conformal deposition, series string resistance and grain statistics in small cells limit layer count and uniformity.
3. Applications
- Current status: In research and development; stacked ferroelectric memory has been demonstrated at tens-of-gigabit scale but is not yet in mass production.
- High-density storage (target): Ferroelectric NAND as a lower-voltage, faster-program alternative to charge-trap 3D NAND.
- Non-volatile DRAM-class memory (target): 3D FeRAM for near-DRAM speed with persistence in AI and data-centre memory.
| Name | Formula | Related Formulae | Variables/Constants |
|---|---|---|---|
| Gate stack capacitance of a vertical (cylindrical) FeFET | |||
| Threshold shift from the polarization in a cylindrical layer | |||
| Field and coercive voltages in a cylindrical ferroelectric layer | |||
| Memory window bounds in a vertical FeFET | |||
| String current of a ferroelectric NAND string | |||
| Pass voltage window | |||
| Self-boosting program inhibit in a ferroelectric NAND string | |||
| Switched charge and capacitance of a vertical ferroelectric capacitor | |||
| Bit density and aspect ratio of a vertical stack |
Important Questions
Ques: How is a ferroelectric NAND string built, and how does it differ from a charge-trap 3D NAND string?
The geometry is the same as in 3D NAND: a stack of gate layers is etched through by a vertical hole, and the hole wall is coated with the memory film, an interlayer and the channel. In a ferroelectric string the memory film is a ferroelectric layer (doped HfO) instead of the oxide-nitride-oxide film, so a bit is stored as the direction of polarization and not as trapped charge. The cells are in series on one channel, and the string current is divided by the sum of the resistances of all the cells and select transistors. Two differences follow. First, the ferroelectric is switched by the field, with no carrier injection through a tunnel layer, so the program voltage is set by and not by a tunnelling field of 8 to 10 MV/cm as in flash. Second, the window is limited to about (cylindrical bounds in the window row), one to two volts for a 10 nm film, against several volts in a charge-trap cell, which limits the number of levels per cell. Reference: K. Florent et al., “Vertical ferroelectric HfO FET based on 3-D NAND architecture: towards dense low-power memory,” IEDM Tech. Dig. (2018), paper 2.5; T. Mikolajick et al., J. Appl. Phys. 129, 100901 (2021).
Ques: Why does the polarization of a cylindrical ferroelectric layer start to switch at the inner radius?
In a cylinder the displacement falls as , so the field is highest at the inner interface. If the field profile is taken as , the field reaches at the inner radius at and at the outer radius only at . For an example with nm, nm (so nm) and MV/cm (0.1 V/nm), these are 0.55 V and 1.65 V, compared with 1.0 V for a planar layer of the same thickness. A pulse between these two voltages switches only part of the thickness, which gives an intermediate threshold, so the outcome of a program pulse depends on the radius as well as on the amplitude. The effect disappears when . Reference: standard coaxial-capacitor electrostatics; T. Mikolajick et al., J. Appl. Phys. 129, 100901 (2021).
Ques: Why does the pass voltage have to lie between two limits?
In a read, every unselected cell must conduct whatever its stored state, so must be above the threshold of the high-threshold state, or the string current is cut off. In a ferroelectric cell the same voltage also drives the polarization, and a pass voltage above the switching-onset voltage starts to move the high-threshold cells toward the low-threshold state. At the channel charge is small, so the high-threshold layer already sits near , the onset of its switching; for an ideal square loop and the static pass window nearly closes (pass-window row, my reading). The usable margin comes from the switching kinetics: a short pass pulse switches only a small part of the grains. In a charge-trap string, in contrast, the pass voltage is far below the tunnelling field of the tunnel layer, so this limit is looser. Reference: K. Florent et al., IEDM Tech. Dig. (2018), paper 2.5; T. Mikolajick et al., J. Appl. Phys. 129, 100901 (2021).
Ques: Why is the channel material an issue in a ferroelectric NAND string?
Polarization switching needs no carrier injection, but the polarization has to be compensated by charge. With a negative gate pulse on an n-type channel, no holes are available to compensate the polarization, so a depletion region forms and the surface potential takes part of the voltage (the term in the write-voltage row), which raises the voltage needed. Polysilicon also has a low mobility, which raises in the string current, and its grain boundaries add variation. Oxide semiconductors such as IGZO have a very low off-current, which should help a boosted channel hold its potential during inhibit, but they also carry no hole inversion layer, so the depletion problem remains. They have been proposed as an alternative channel, with trade-offs between mobility, hole supply and process temperature. Reference: T. Mikolajick et al., J. Appl. Phys. 129, 100901 (2021); K. Florent et al., IEDM Tech. Dig. (2018), paper 2.5.
Ques: How does a vertical 3D FeRAM differ from a ferroelectric NAND string?
A 3D FeRAM stacks ferroelectric capacitors along a vertical pillar, and each cell is read by reversing its polarization and measuring the charge , which is destructive and needs a write-back, as in the planar FeRAM page. The charge per cell scales with the height of the cell and with the shell radius (the logarithmic mean of and ), so a thin stack layer and a narrow pillar both reduce the signal, and the sense margin depends on , which grows with the pillar length. A ferroelectric NAND string has no destructive read and uses the threshold voltage, but its cells are in series, so the read current and the pass voltage window limit the number of layers. The two are different trades between density, read signal and endurance, not versions of the same cell. Reference: S. Ramaswamy et al., “NVDRAM: a 32Gb dual layer 3D stacked non-volatile ferroelectric memory with near-DRAM performance for demanding AI workloads,” IEDM Tech. Dig. (2023); T. Mikolajick et al., J. Appl. Phys. 129, 100901 (2021).
Ques: What limits the number of layers and the scaling of the cell?
The aspect ratio grows with the number of layers and is limited by the hole etch and by the conformal deposition of the ferroelectric, interlayer and channel inside the hole, which have to fit within together with the channel. For a given hole radius, a thicker ferroelectric reduces the channel radius and makes the field non-uniform (cylindrical rows). As the cell shrinks, the number of grains falls, and the spread of the switched fraction and so of the threshold grows (the grain statistics on the FeFET page). The string current also falls with , because pass-cell resistances are added in series. Reference: T. Mikolajick et al., J. Appl. Phys. 129, 100901 (2021); H. Mulaosmanovic et al., ACS Appl. Mater. Interfaces 9, 3792 (2017) (grain statistics in scaled FeFETs).
Related pages in this vault: Ferroelectric Field Effect Transistor (FeFET), Ferroelectric Random Access Memory (FeRAM), Charge Trap Flash Memory (SONOS, TANOS and 3D NAND), Floating Gate Flash Memory (NOR and NAND), Ferroelectric Tunnel Junction (FTJ), Dynamic Random Access Memory (DRAM), Ferroelectric Random Access Memory (FeRAM, PZT and HfO2), Floating Gate and Charge-Trap Flash Memory (NOR, NAND and 3D NAND), Piezoresponse Force Microscope (PFM).