1. Theory

Definition: Steep-slope FETs are transistors designed to switch with a subthreshold swing below the 60 mV/dec Boltzmann limit of a MOSFET at 300 K.
Scope: This page covers the tunnel FET (TFET), the impact-ionization MOS (I-MOS) and the negative-capacitance FET (NC-FET); ferroelectric memory FETs are in the Memory folder.
Boltzmann limit: A MOSFET injects carriers thermally over a barrier, so its current cannot rise faster than one decade per $(k_{B} T / q) ln 10$ of surface potential.
TFET: A gated P-I-N junction where the gate aligns the channel conduction band with the source valence band, so current flows by band-to-band tunnelling.
I-MOS: A gated P-I-N structure biased near avalanche, where the gate triggers impact-ionization multiplication in an intrinsic region.
NC-FET: A ferroelectric layer in series with the gate dielectric provides a negative capacitance that amplifies the internal gate voltage.

2. Working Principle

TFET switching: The band edge filters out the thermal tail of the source carriers, so the current turns on over a narrower voltage range than thermionic injection allows.
TFET limitations: Low on-current (small tunnelling probability), a swing that worsens as current rises, and ambipolar leakage in homojunction devices.
TFET heterojunctions: Staggered or broken-gap junctions (e.g. InAs/GaSb) and narrow-gap sources raise tunnelling probability and on-current.
I-MOS switching: Avalanche feedback gives an extremely abrupt turn-on, but needs high voltage and suffers hot-carrier damage and threshold drift.
NC-FET internal gain: When $∣ C_{F E} ∣ > C_{M O S}$ the stack is stable and hysteresis-free, and the internal node swings more than the gate ( $A_{V} > 1$ ), lowering the swing.
NC-FET debate: How much of the measured steep swing comes from true negative capacitance versus polarization switching and trapped charge is still debated.

3. Applications

Current status: All three are research devices; none is yet in mainstream production.
Ultra-low-power logic (target): TFETs aim at sub-0.3 V logic for IoT and always-on circuits where MOSFET leakage limits voltage scaling.
Low-voltage CMOS boosters (target): NC-FET ferroelectric gate stacks are being explored as an add-on to existing FinFET and GAA processes.

Tunnel Field-Effect Transistor (TFET)

Name	Formula	Related Formulae	Variables/Constants
Band-to-band tunneling transmission (WKB)	$T_{W K B} \approx exp [- \frac{4 λ 2 m ^{*} E _{g}^{3/2}}{3ℏ ( E _{g} + Δ ϕ )}]$	$λ = \frac{ε _{c h}}{ε _{o x}} t_{c h} t_{o x}$	$T_{W K B} : t u nn e l in g p r o babi l i t y t h r o ug h t h e t r ian g u l a r so u r ce - c hann e l ba r r i er$ $λ : scr ee nin g (na t u r a l) l e n g t h o v er w hi c h t h e g a t e co n t r o l s t h e ban d b e n d in g$ $m^{*} : r e d u ce d t u nn e l in g e f f ec t i v e ma ss$ $E_{g} : ban d g a p a t t h e t u nn e l j u n c t i o n (e n er g i es in j o u l es)$ $Δ ϕ : e n er g y w in d o w in w hi c h t h e f i l l e d so u r ce s t a t es f a ce e m pt y c hann e l s t a t es$ $t_{c h}, t_{o x} : c hann e l an d o x i d e t hi c k n ess$
Landauer tunnel current	$I_{D S} = \frac{2 q}{h} \int T (E) M (E) [f_{S} (E) - f_{D} (E)] d E$		$T (E) : e n er g y - d e p e n d e n t t r an s mi ss i o n p r o babi l i t y, e q u a l t o T_{W K B} in s i d e t h e o v er l a p w in d o w$ $f_{S}, f_{D} : F er mi - D i r a c d i s t r ib u t i o n s o f t h e so u r ce an d d r ain$ $M (E) : n u mb er o f t r an s v er se m o d es a t e n er g y E, in c l u d in g an y v a l l ey d e g e n er a cy$ $h : P l an c k co n s t an t$
Kane band-to-band generation rate	$G_{B T B T} = A \frac{E ^{2}}{E _{g}} exp (- \frac{B E _{g}^{3/2}}{E})$	$B = \frac{π m ^{*}}{2 2 q ℏ}$	$G_{B T B T} : t u nn e l in g g e n er a t i o n r a t e p er u ni t v o l u m e f or a d i r ec t g a p an d u ni f or m f i e l d$ $E : l oc a l e l ec t r i c f i e l d$ $A : ma t er ia l - d e p e n d e n t p r e f a c t or t ha t i s u s u a l l y f i tt e d t o m e a s u r e d d a t a$ $B : e x p o n e n t ia l f i e l d coe f f i c i e n t$
Subthreshold swing factorization	$S = \frac{\partial V _{GS}}{\partial ψ _{s}} \cdot \frac{\partial ψ _{s}}{\partial l o g _{10} I _{D S}}$	$\frac{\partial V _{GS}}{\partial ψ _{s}} = m = 1 + \frac{C _{s}}{C _{o x}}, \frac{\partial ψ _{s}}{\partial l o g _{10} I _{D S}} \geq \frac{k _{B} T}{q} ln 10 (MOSFET only)$	$ψ_{s} : s u r f a ce p o t e n t ia l (t h e ban d b e n d in g in t h e c hann e l)$ $m : b o d y f a c t or (g a t e e f f i c i e n cy), a l w a y s a t l e a s t 1$ $C_{s} : se mi co n d u c t or c a p a c i t an ce in c l u d in g d e pl e t i o n an d in t er f a ce t r a p s$ $(a TFET controls the injection through the band alignment, so the second factor is not limited by the Boltzmann tail and S can fall below 60 mV/dec)$ $k_{B} : B o l t z mann co n s t an t$
Average swing over a current range	$S_{a v g} = \frac{V _{GS} ( I _{2} ) - V _{GS} ( I _{1} )}{l o g _{10} ( I _{2} / I _{1} )}$		$S_{a v g} : a v er a g e s w in g b e tw ee n tw o c u r r e n t l e v e l s I_{1} an d I_{2}, t h e m e anin g f u l n u mb er f or a T F E T s in ce i t s l oc a l s w in g v a r i es w i t h bia s$ $V_{GS} (I) : g a t e v o l t a g e t ha t g i v es d r ain c u r r e n t I$
Effective tunneling gap in a heterojunction	$E_{g, e f f} = E_{C, c h} - E_{V, sr c}$	$E_{g, e f f} \leq 0 (broken-gap alignment)$	$E_{C, c h} : co n d u c t i o n ban d e d g e o f t h e c hann e l ma t er ia l$ $E_{V, sr c} : v a l e n ce ban d e d g e o f t h e so u r ce ma t er ia l$ $E_{g, e f f} : t h e g a p t ha t r e pl a ces E_{g} in t h e t u nn e l in g e x p o n e n t w h e n t h e so u r ce an d c hann e l d i f f er$

Impact-Ionization MOS (I-MOS)

Name	Formula	Related Formulae	Variables/Constants
Impact ionization multiplication	$M = \frac{1}{1 - \int _{0}^{L_{i}} α d x}$	$\int_{0}^{L_{i}} α d x = 1 (breakdown condition; see the Avalanche Diode page)$	$M : a v a l an c h e m u l t i pl i c a t i o n f a c t or o f t h e in t r in s i c r e g i o n$ $α : im p a c t i o ni z a t i o n coe f f i c i e n t, w hi c h d e p e n d s s t r o n g l y o n t h e l oc a l f i e l d$ $L_{i} : l e n g t h o f t h e in t r in s i c (g a t e - co n t r o l l e d) r e g i o n$
Impact-ionization MOS drain current	$I_{D} = M I_{0}$		$I_{0} : c u r r e n t inj ec t e d in t o t h e in t r in s i c r e g i o n b y t h e r e v er se - bia se d so u r ce j u n c t i o n$ $(the gate modulates the field in the intrinsic region, and avalanche gives an abrupt switch with a simulated swing below about 10 mV/dec at the cost of high voltage operation and hot-carrier damage; M assumes equal electron and hole ionization coefficients, see the Avalanche Diode page for the general integral)$

Negative-Capacitance FET (NC-FET)

Name	Formula	Related Formulae	Variables/Constants
Landau-Khalatnikov ferroelectric energy and voltage	$U = α P^{2} + β P^{4} + γ P^{6} - E P$ $V_{F E} = t_{F E} (2 α P + 4 β P^{3} + 6 γ P^{5})$	$E = 2 α P + 4 β P^{3} + 6 γ P^{5} (static, \partial U / \partial P = 0)$	$U : f r ee e n er g y d e n s i t y$ $P : p o l a r i z a t i o n (e q u a l t o t h e c ha r g e p er u ni t a r e a Q o n t h e pl a t es)$ $α, β, γ : L an d a u coe f f i c i e n t s, w i t h α < 0 f or a f er r oe l ec t r i c$ $E : e l ec t r i c f i e l d in t h e f er r oe l ec t r i c$ $V_{F E}, t_{F E} : v o l t a g e a cr oss an d t hi c k n ess o f t h e f er r oe l ec t r i c l a y er$
Ferroelectric capacitance	$C_{F E} = (\frac{d V _{F E}}{d Q})^{- 1} = \frac{1}{t _{F E} ( 2 α + 12 β P ^{2} + 30 γ P ^{4} )}$	$C_{F E} (P = 0) = \frac{1}{2 α t _{F E}} < 0$	$C_{F E} : d i f f er e n t ia l c a p a c i t an ce o f t h e f er r oe l ec t r i c l a y er, w hi c h i s n e g a t i v e in t h e r e g i o n w h er e 2 α + 12 β P^{2} + 30 γ P^{4} < 0$ $Q : c ha r g e p er u ni t a r e a$
Internal voltage gain	$A_{V} = \frac{\partial V _{in t}}{\partial V _{GS}} = \frac{C _{F E}}{C _{F E} + C _{M O S}}$	$C_{M O S} = \frac{C _{o x} C _{d e p}}{C _{o x} + C _{d e p}}$	$V_{in t} : v o l t a g e o n t h e in t er na l n o d e b e tw ee n t h e f er r oe l ec t r i c an d t h e o x i d e$ $C_{M O S} : c a p a c i t an ce o f t h e M O S g a t e s t a c k see n f r o m t h e in t er na l n o d e$ $A_{V} : in t er na l v o l t a g e am pl i f i c a t i o n, g r e a t er t han o n e w h e n C_{F E} < 0 an d ∣ C_{F E} ∣ > C_{M O S}$
Subthreshold swing of an NC-FET	$S = (1 + \frac{C _{M O S}}{C _{F E}}) m \frac{k _{B} T}{q} ln 10$	$m = 1 + \frac{C _{d e p}}{C _{o x}}$	$S : s u b t h r es h o l d s w in g, b e l o w t h e 60 mV / d ec l imi t i f ∣ C_{F E} ∣ i s o n l y s l i g h tl y l a r g er t han C_{M O S} an d C_{F E} < 0$ $m : b o d y f a c t or o f t h e u n d er l y in g M O S F E T$ $k_{B} : B o l t z mann co n s t an t$
Stability and hysteresis-free condition	$∣ C_{F E} ∣ > C_{M O S}$ $t_{F E} < \frac{1}{2 ∣ α ∣ C _{M O S, ma x}}$		$C_{M O S, ma x} : l a r g es t v a l u e o f C_{M O S} o v er t h e g a t e s w ee p, a pp r o a c hin g C_{o x} in s t r o n g in v er s i o n$ $(the condition at P = 0 is necessary but not sufficient, since the first condition must hold over the whole sweep)$
Remnant polarization and coercive field (sixth-order term neglected)	$P_{r} = \frac{∣ α ∣}{2 β}$ $E_{C} = \frac{4}{3} \frac{∣ α ∣ ^{3/2}}{6 β}$		$P_{r} : r e mnan t p o l a r i z a t i o n a t z er o f i e l d$ $E_{C} : coer c i v e f i e l d, a t w hi c h t h e p o l a r i z a t i o n s w i t c h es$ $γ : se t t o z er o f or t h ese c l ose d f or m s$

Important Questions

Ques: Why can a tunnel FET have a swing below 60 mV/dec when a MOSFET cannot?

In a MOSFET, carriers are injected over a barrier by thermal emission from the Boltzmann tail of the source distribution, which sets $\partial ψ_{s} / \partial lo g_{10} I \geq (k_{B} T / q) ln 10$ and thus $S \geq 60 mV/dec$ at 300 K. In a TFET, the current is carried by band-to-band tunneling, and the gate moves the conduction band of the channel past the valence band of the source; the Fermi tail is filtered out by the band edge, so the current switches on over a narrower voltage range than the thermal limit allows. The price is a low on-current (the tunneling probability is small even when aligned), a swing that rises as the current rises, and, in homojunction devices, ambipolar leakage at negative gate voltage. Reference: A.M. Ionescu and H. Riel, “Tunnel field-effect transistors as energy-efficient electronic switches,” Nature 479, 329 (2011); A.C. Seabaugh and Q. Zhang, “Low-voltage tunnel transistors for beyond CMOS logic,” Proc. IEEE 98, 2095 (2010).

Ques: Why do TFETs use heterojunctions or narrow-gap source materials?

The exponent of $T_{W K B}$ scales as $E_{g}^{3/2} / (E_{g} + Δ ϕ)$ , so a smaller (effective) gap and a higher effective overlap both enlarge the tunneling probability and the on-current. Staggered or broken-gap heterojunctions (for example InAs/GaSb) make $E_{g, e f f}$ small or negative, and a narrow-gap source gives a high on-current while a wider-gap channel limits the off-state leakage and ambipolar current. Since the tunneling window is limited to the source side of the junction, $m^{*}$ should also be small. Reference: A.C. Seabaugh and Q. Zhang, Proc. IEEE 98, 2095 (2010).

Ques: How can a negative capacitance be stable inside a transistor?

A ferroelectric on its own has an energy landscape with a double well, and the region between the wells, where $C_{F E} < 0$ , is not stable at fixed voltage. Placed in series with a positive capacitor $C_{M O S}$ , the combined energy has a single minimum if $∣ C_{F E} ∣ > C_{M O S}$ , so the stack is stable and hysteresis-free; the polarization then moves through the otherwise unreachable negative-capacitance region, and the internal node voltage swings by more than the gate voltage, $A_{V} > 1$ . Whether this behaviour survives in the dynamic switching of real devices, and how much of the measured steep swing is due to polarization switching and trapped charge, is still debated. Reference: S. Salahuddin and S. Datta, “Use of negative capacitance to provide voltage amplification for low power nanoscale devices,” Nano Lett. 8, 405 (2008); M. Hoffmann et al., “Unveiling the double-well energy landscape in a ferroelectric layer,” Nature 565, 464 (2019); A.K. Yadav et al., “Spatially resolved steady-state negative capacitance,” Nature 565, 468 (2019).

Quartz 5

Explorer

Steep Slope FETs (Tunnel FET, Impact Ionization MOS, Negative Capacitance FET)