1. Theory
- Definition: A MOS varactor is a MOS capacitor used as a voltage-controlled capacitance, built either as an NMOS gate in an n-well with n+ contacts (accumulation mode, A-MOS) or as a PMOS in an n-well with source and drain tied together and the well biased separately (inversion mode, I-MOS) (Razavi; Li et al.; Andreani and Mattisson).
- Monotonic tuning: An ordinary MOSFET with source, drain and bulk tied has a nonmonotonic C-V curve with a dip in depletion; both varactor connections avoid one of the two branches, so the capacitance moves monotonically between and (Razavi; Li et al.).
- Tuning ratio: The ratio is set by the oxide capacitance against the series oxide-depletion capacitance, diluted by the fixed overlap and fringe capacitance; measured values are about 2.5 to 3.4, with simulated values of 6 to 11 for long or special structures (Razavi; Li et al.; Chartered patent).
- Quality factor: Q is limited by the distributed channel or accumulation-layer resistance and falls roughly as , so short gates give high Q and a small ratio (Razavi).
- Advantage over the PN varactor: MOS varactors replaced PN-junction varactors in CMOS RF design, because they tolerate both polarities of bias without forward conduction and give larger ratios in a standard process; the PN varactor is covered on the Diodes pages (Razavi; Andreani and Mattisson).
2. Working Principle
- Accumulation mode: With the gate positive with respect to the n-well, electrons from the n+ contacts accumulate under the gate and the full oxide capacitance appears; with the gate negative, electrons are repelled, a depletion region forms in series with the oxide, and no inversion layer forms because no source of holes is connected (Razavi).
- Inversion mode: With source and drain at the well potential of a PMOS, the device moves between depletion and strong inversion and never enters accumulation, giving a monotonic curve with a steeper transition (Andreani and Mattisson; Li et al.; background knowledge for the bias arrangement).
- Transition voltage: The change from to happens over a few hundred millivolts around flat band, so the large signal swing of an oscillator averages the capacitance over the curve (Razavi; US 7,038,527).
- Loss: Charge reaches the middle of the gate through the accumulation or inversion layer, so the series resistance is that of a distributed RC line, about one-twelfth of the end-to-end resistance when both ends are contacted (Razavi).
3. Applications
- LC voltage-controlled oscillators: The tuning element of integrated LC VCOs for frequency synthesizers from about 1 to tens of GHz, usually in back-to-back pairs across the tank (Razavi; Andreani and Mattisson; Xiao et al.).
- Tunable filters and matching networks: Voltage-tuned capacitance in RF filters and in tunable matching networks of integrated amplifiers (background knowledge).
- Current status: In CMOS, accumulation-mode varactors are the standard choice for analog tuning, with switched capacitor banks used for coarse tuning, while hyperabrupt PN varactors remain in some bipolar and BiCMOS processes (Razavi; background knowledge for the band switching).
Capacitance-Voltage Characteristic
| Name | Formula | Related Formulae | Variables/Constants |
|---|---|---|---|
| Maximum and minimum capacitance of an accumulation-mode varactor | |||
| Overlap capacitance and gate length | |||
| Tanh model of the C-V curve and its charge |
Quality Factor and Series Resistance
| Name | Formula | Related Formulae | Variables/Constants |
|---|---|---|---|
| Quality factor and distributed channel resistance | |||
| Cutoff frequency of a varactor |
Tuning in LC Oscillators
| Name | Formula | Related Formulae | Variables/Constants |
|---|---|---|---|
| Tuning range of an LC oscillator | |||
| Extending the tuning ratio with a buried junction |
Important Questions
Ques: Why are MOS varactors used in VCOs instead of plain MOSFET gate capacitance or PN varactors?
A plain MOSFET with source, drain and bulk tied has a gate capacitance that falls in depletion and rises again in both accumulation and inversion, so the frequency would not move monotonically with the control voltage, which Razavi notes causes problems for VCO tuning and PLL design. The accumulation-mode varactor, an NMOS in an n-well, has no source of holes and therefore no inversion branch, and its curve rises monotonically from to , scales well to 65 and tolerates both polarities of bias. A PN varactor must stay reverse biased to avoid forward conduction. Andreani and Mattisson built 1.8 VCOs tuned by both MOS varactor types and found lower power and lower phase noise than with a diode varactor, with the accumulation-mode varactor best overall. Reference: B. Razavi, RF Microelectronics, 2nd ed., Sec. 7.5 Varactors, pp. 483-490 (course extract hosted by the University of Patras; book title and author identified from the extract’s running headers and page range, not printed in the text) (fetch-tool summary); P. Andreani and S. Mattisson, ‘On the use of MOS varactors in RF VCOs’, IEEE J. Solid-State Circuits 35(6), 905-910 (2000), doi:10.1109/4.845194 (abstract only).
Ques: Is the tuning ratio of an accumulation-mode MOS varactor about 2.5, 3.4 or 6?
All three are reported for different structures. Razavi’s 65 example with a 50 gate has an ideal ratio of 5.72 if were only the overlap, but about 2.5 in practice with the oxide-depletion series term, and Xiao et al. also give 2.5 at 0.18 . Li et al. measured about 3.4 for 0.5 gates, since a longer gate dilutes the overlap. The Chartered patent’s simulated 6.2 for a conventional n-MOS varactor at 0.18 is per unit width and probably ignores fringe and wiring parasitics (my reading). Intrinsically, a 2.5 oxide on an assumed well gives about 12 at 1 of band bending (computed). The measured values of 2.5 to 3.4 are the more likely ones for real layouts. Reference: B. Razavi, RF Microelectronics, 2nd ed., Sec. 7.5 Varactors, pp. 483-490 (course extract hosted by the University of Patras; book title and author identified from the extract’s running headers and page range, not printed in the text) (fetch-tool summary); Xiao Shimao, Ma Chengyan and Ye Tianchun, ‘A novel 2.95-3.65 GHz CMOS LC-VCO using tuning curve compensation’, Journal of Semiconductors 30(10), 105001 (2009), doi:10.1088/1674-4926/30/10/105001 (fetch-tool summary); M. Li, R. E. Amaya, R. G. Harrison and N. G. Tarr, ‘Investigation of CMOS Varactors for High-GHz-Range Applications’, Research Letters in Electronics 2009, Article ID 535809, doi:10.1155/2009/535809 (fetch-tool summary); M. Sarkar and P. R. Verma (Chartered Semiconductor Manufacturing), ‘MOS varactors with large tuning range’, US Patent 7,618,873 B2 (granted 2009) (fetch-tool summary).
Ques: How does gate length trade tuning ratio against Q?
The overlap capacitance does not change with voltage, so a short gate has a ratio close to 1, while the channel resistance and capacitance both grow with length, so Q falls roughly as . In Razavi’s 65 example, doubling from 50 to 100 raises from 1.03 to 1.88 and the overlap-limited ratio from 5.72 to 10.4, while Q falls 3.65 times, from 1.83 times more capacitance and twice the resistance (computed). With the distributed one-twelfth factor, an assumed 400 and 0.5 beyond flat band give at 5 for a 0.5 gate and 7.6 for 1 (computed). Razavi concludes that up to about 10 twice the minimum length widens the tuning range while keeping the varactor Q well above the inductor Q. Reference: B. Razavi, RF Microelectronics, 2nd ed., Sec. 7.5 Varactors, pp. 483-490 (course extract hosted by the University of Patras; book title and author identified from the extract’s running headers and page range, not printed in the text) (fetch-tool summary).
Ques: Which has the higher Q, an accumulation-mode or an inversion-mode MOS varactor?
The sources disagree. Li et al. measured a cutoff frequency of about 130 for an accumulation-mode varactor against about 100 for an inversion-mode one in 0.18 CMOS, so Q of about 26 against 20 at 5 (computed), and attribute it to the lower series resistance of the accumulation layer, consistent with electrons being more mobile than holes in a PMOS inversion layer (background knowledge). US 7,038,527 instead simulates Q of 136 to 915 for an inversion-mode connection and only 82 to 380 for an accumulation connection near 10 , but in a different structure with a separate back gate. The measured data of Li et al., supported by Andreani and Mattisson’s finding that accumulation mode gave the best VCO, are the more likely guide for standard layouts (my reading). Reference: M. Li, R. E. Amaya, R. G. Harrison and N. G. Tarr, ‘Investigation of CMOS Varactors for High-GHz-Range Applications’, Research Letters in Electronics 2009, Article ID 535809, doi:10.1155/2009/535809 (fetch-tool summary); ‘MOS varactor for LC VCOs’, US Patent 7,038,527 (assignee and year not in the text read) (fetch-tool summary); P. Andreani and S. Mattisson, ‘On the use of MOS varactors in RF VCOs’, IEEE J. Solid-State Circuits 35(6), 905-910 (2000), doi:10.1109/4.845194 (abstract only).
Ques: Why does a MOS varactor need a smooth model such as the tanh form?
Because an oscillator swings the varactor across its whole C-V curve, and the simulator needs a capacitance with continuous derivatives. Razavi gives , where and set the position and slope, and notes that tabulated data can produce artefacts such as a high noise floor. Charge-based simulators such as Spectre need the charge, , while voltage-based ones such as HSPICE use C(V) directly, and the two can predict different tuning ranges. Differentiating the charge returns the tanh capacitance (computed), which confirms the reconstruction of the garbled equation in the extract. Razavi also stresses that and in the model include the overlap capacitance, so the fitted curve reproduces the measured extremes of the full layout rather than those of the intrinsic device. Reference: B. Razavi, RF Microelectronics, 2nd ed., Sec. 7.5 Varactors, pp. 483-490 (course extract hosted by the University of Patras; book title and author identified from the extract’s running headers and page range, not printed in the text) (fetch-tool summary).
Ques: What are the tuning ratios in the Chartered buried-junction varactor patent, and is the p-MOS baseline 4.5 or 4.7?
The patent places a buried p-well under an n-well accumulation varactor so that its depletion merges with that under the gate, lowering while stays at . The simulated n-MOS ratios of 6.2, 9.6 and 11.35 follow from its capacitances (computed). For p-MOS, of and of give 4.72, not the stated 4.5 (computed), while the improved devices agree at 7.1 and 8.3. The stated 58 per cent gain matches a 4.5 baseline but would be 50 per cent from 4.72 (computed). A of about , rounded to 0.9 in the table, would explain 4.5 (my reading), so the stated ratio is the more likely one and the capacitance is the rounded value. Reference: M. Sarkar and P. R. Verma (Chartered Semiconductor Manufacturing), ‘MOS varactors with large tuning range’, US Patent 7,618,873 B2 (granted 2009) (fetch-tool summary).
Related pages in this vault: Varactor Diode, MOS and Poly-Insulator Capacitors, RF MEMS Passives, MIM and MOM Capacitors, Deep-Trench Capacitors, Long Channel MOSFET, RF and Non-Quasi-Static Effects, MOS Capacitor.