1. Theory

Definition: An oxide capacitor uses the thin gate oxide or a dedicated thin oxide between two conducting plates: a poly or metal gate over an inversion or accumulation layer in silicon (MOS capacitor), over a heavily doped diffusion (poly-diffusion capacitor), or over a second poly layer (poly-poly capacitor) (Kraft; Niknejad and Boser).
Capacitance: The parallel-plate relation $C = ε_{0} ε_{r} A / t_{o x}$ gives the highest density of any planar on-chip capacitor, about 2 to 5 $fF/ μ m^{2}$ for gate oxides of 6 to 15 $nm$ (GF180MCU; Niknejad and Boser; computed).
Voltage dependence: A MOS capacitor on lightly doped silicon is strongly nonlinear, since it passes through accumulation, depletion and inversion with the gate voltage; with a heavily doped bottom plate or a second poly plate, the coefficient falls to about 10 to 50 $ppm/V$ (MOS Capacitor page; Kraft; Allen).
Accuracy: Absolute values vary by 10 to 30 per cent with the oxide thickness, but ratios of identical unit capacitors match to about 0.02 to 0.3 per cent (Kraft; Allen).
Parasitics: The bottom plate couples to the substrate through its junction or the field oxide, and fringe capacitance adds to both plates (Kraft; Niknejad and Boser).
Leakage: Thin gate oxides conduct by tunnelling, so a large MOS capacitor has a measurable gate current below about 3 $nm$ (Intel).
Voltage limit: The rated voltage is set by the oxide breakdown field, about 11 $MV/cm$ , with a large margin for long-term breakdown (GF180MCU; computed).

2. Working Principle

Charge storage: The gate charge is balanced by mobile carriers at the silicon surface, an inversion layer supplied by source and drain or an accumulation layer supplied by the substrate or well, so the full oxide capacitance appears only when the surface is accumulated or strongly inverted (MOS Capacitor page; Niknejad and Boser).
Depletion region: Between flat band and threshold the depletion capacitance appears in series with the oxide and the capacitance dips; poly depletion at the gate adds a smaller series term (MOS Capacitor page; background knowledge).
Distributed channel: The charge reaches the middle of the plate through the resistance of the channel, so a MOS capacitor is a distributed RC line whose capacitance falls above a corner frequency that scales as $1/ L^{2}$ (Meng et al.; background knowledge).
Poly-poly and poly-diffusion: With both plates heavily doped, neither plate depletes appreciably, so the capacitance is nearly constant and the device behaves as a linear capacitor (Kraft; Allen).
Leakage control: Biasing a decap below flat band, in depletion, removes most of the carriers that tunnel, cutting leakage about 100 times at a 25 per cent loss of capacitance (Intel).

3. Applications

Supply decoupling: Thin-oxide MOS capacitors fill unused space in standard-cell and IP layouts as on-chip decoupling, where no other planar capacitor reaches the same density in the front end (Meng et al.; Niknejad and Boser).
Compensation and bypass: Miller compensation and bias bypass, where nonlinearity does not matter (Niknejad and Boser).
Switched-capacitor circuits and data converters: Poly-poly capacitors in switched-capacitor filters and charge-redistribution DACs and ADCs in processes that offer them, for their linearity and matching (Niknejad and Boser; Kraft).
Current status: In modern processes without a second poly, MIM and MOM capacitors have largely replaced poly-poly capacitors for precision work, while MOS capacitors remain the standard decoupling element (Niknejad and Boser; MIM and MOM Capacitors page).

Capacitance and Voltage Limit

Name	Formula	Related Formulae	Variables/Constants
Capacitance of a parallel-plate oxide capacitor	$C = \frac{ε _{0} ε _{r} A}{t _{o x}} = C_{o x} A$	$t_{o x} = \frac{ε _{0} ε _{r}}{C _{o x}}$	$C : c a p a c i t an ce$ $ε_{0} : v a c uu m p er mi tt i v i t y (8.854 \times 1 0^{- 3} fF / μ m)$ $ε_{r} : r e l a t i v e p er mi tt i v i t y (3.9 f or S i O 2)$ $A : pl a t e a r e a$ $t_{o x} : d i e l ec t r i c t hi c k n ess$ $C_{o x} : c a p a c i t an ce p er a r e a; K r a f t : p o l y - d i f f u s i o n c a p a c i t or s o n 5 t o 50 nm g a t e o x i d e g i v e 500 pF/m m^{2} t o 1.5 nF/m m^{2}, f i e l d o x i d e i s ab o u t t e n t im es t hi c k er; GF 180 M C U : C_{o x} o f 4.4 fF/ μ m^{2} (3.4 t o 5.4) f or t h e 3.3 V g a t e an d 2.3 fF/ μ m^{2} (1.8 t o 2.8) f or t h e 6 V g a t e; N ik n e j a d an d B oser : g a t e c a p a c i t an ce ab o u t 5300 aF/ μ m^{2} an d p o l y - p o l y ab o u t 1000 aF/ μ m^{2}; A l l e n : M O S 0.35 t o 0.5 an d p o l y - p o l y 0.3 t o 0.4 fF/ μ m^{2} in an o l d er p r ocess; M O S p h y s i cs i s o n t h e M O S C a p a c i t or p a g e$ $(co m p u t e d : 4.4 an d 2.3 fF/ μ m^{2} cor r es p o n d t o 7.8 an d 15.0 nm o f S i O 2, 5.3 fF/ μ m^{2} t o 6.5 nm, an d K r a f t^{'} s 0.5 t o 1.5 fF/ μ m^{2} t o 69 t o 23 nm; 1 nF n ee d s 0.19 m m^{2} a t 5.3 fF/ μ m^{2})$
Maximum voltage from oxide breakdown	$E_{o x} = \frac{V}{t _{o x}}, V_{ma x} \approx \frac{E _{u se}}{E _{B D}} B V_{o x}$	$E_{B D} = \frac{B V _{o x}}{t _{o x}}$	$E_{o x} : o x i d e f i e l d$ $V : v o l t a g e a cr oss t h e d i e l ec t r i c$ $V_{ma x} : a l l o w e d o p er a t in g v o l t a g e$ $E_{u se} : a l l o w e d l o n g - t er m f i e l d$ $E_{B D} : b r e ak d o w n f i e l d$ $B V_{o x} : b r e ak d o w n v o l t a g e (t h e d er a t in g r u l e i s ba c k g r o u n d k n o w l e d g e; t im e - d e p e n d e n t b r e ak d o w n i s o n t h e E l ec t r i c a l S t r ess an d C M O S L o g i c T r an s i s t or s p a g es); GF 180 M C U : B V_{o x} o f ab o u t 9 V (a t l e a s t 7) f or t h e 3.3 V g a t e o x i d e an d ab o u t 16 V (a t l e a s t 12) f or t h e 6 V o x i d e$ $(co m p u t e d : w i t h t h e t hi c k n esses ab o v e, 9 V o v er 7.8 nm i s 11.5 MV/cm an d 16 V o v er 15.0 nm i s 10.7 MV/cm, so t h e r a t e d 3.3 an d 6 V a r e ab o u t 37 p er ce n t o f b r e ak d o w n)$
Poly depletion in series with the oxide	$\frac{1}{C _{e f f}} = \frac{1}{C _{o x}} + \frac{1}{C _{p o l y}}, C_{p o l y} = \frac{ε _{s}}{W _{p}}$	$t_{e f f} = t_{o x} + \frac{ε _{o x}}{ε _{s}} W_{p}$	$C_{e f f} : e f f ec t i v e c a p a c i t an ce p er a r e a$ $C_{o x} : o x i d e c a p a c i t an ce p er a r e a$ $C_{p o l y} : c a p a c i t an ce o f t h e d e pl e t e d l a y er o f w i d t h W_{p} a t t h e b o tt o m o f t h e p o l y g a t e$ $ε_{s} an d ε_{o x} : p er mi tt i v i t i es o f S i an d S i O 2$ $t_{e f f} : e l ec t r i c a l l y e f f ec t i v e t hi c k n ess (ba c k g r o u n d k n o w l e d g e; t h e s am e a ppl i es t o t h e s u b s t r a t e s i d e in d e pl e t i o n, see t h e M O S C a p a c i t or p a g e)$ $(co m p u t e d : 1 nm o f p o l y d e pl e t i o n a dd s 0.33 nm t o t_{e f f}, w hi c h l o w er s a 6.5 nm c a p a c i t or b y ab o u t 5 p er ce n t)$

Linearity, Matching and Parasitics

Name	Formula	Related Formulae	Variables/Constants
Voltage and temperature coefficients	$C (V, T) = C_{0} [1 + V C_{1} V + V C_{2} V^{2}] [1 + T C_{1} (T - T_{0})]$	$C_{M O S} (V_{G}) : C_{o x} (accumulation), \frac{C _{o x} C _{d}}{C _{o x} + C _{d}} (depletion), C_{o x} (inversion, low f)$	$C (V, T) : c a p a c i t an ce a t bia s V an d t e m p er a t u r e T$ $C_{0} : v a l u e a t z er o bia s an d T_{0}$ $V C_{1} an d V C_{2} : v o l t a g e coe f f i c i e n t s$ $T C_{1} : t e m p er a t u r e coe f f i c i e n t, C_{M O S} (V_{G}) : s ma l l - s i g na l c a p a c i t an ce o f a M O S c a p a c i t or a g ain s t g a t e v o l t a g e$ $C_{d} : d e pl e t i o n c a p a c i t an ce (r e g i o n s f r o m t h e M O S C a p a c i t or p a g e); K r a f t : p o l y - d i f f u s i o n 7 ppm/V an d 20 ppm/K, c a p a c i t or s in g e n er a l 10 t o 100 ppm/V an d 25 ppm/K; A l l e n : M O S \pm 20 ppm/V an d 20 ppm/K, p o l y - p o l y \pm 50 ppm/V an d 25 ppm/K; N ik n e j a d an d B oser : a g a t e c a p a c i t or ha s h ug e V C an d a bi g T C an d i s u se f u l o n l y f or b y p a ss an d M i l l er co m p e n s a t i o n, p o l y - p o l y ab o u t 10 ppm/V an d 25 ppm/K$ $(co m p u t e d : a t 10 ppm/V an d 5 V t h e c a p a c i t an ce c han g es b y 0.005 p er ce n t; a M O S c a p a c i t or bia se d t h r o ug h d e pl e t i o n c han g es b y t e n s o f p er ce n t (M O S C a p a c i t or p a g e), so o n l y a h e a v i l y d o p e d b o tt o m pl a t e or a f i x e d a cc u m u l a t i o n or in v er s i o n bia s g i v es t h e l o w coe f f i c i e n t s)$
Matching and edge effects	$\frac{Δ C}{C} \approx \frac{Δ t _{o x}}{t _{o x}} + 2Δ l (\frac{1}{W} + \frac{1}{L})$	$\frac{Δ C}{C}_{s q u a r e} = \frac{4Δ l}{a}$	$Δ C / C : r e l a t i v e c a p a c i t an ce er r or$ $Δ t_{o x} : t hi c k n ess er r or$ $Δ l : e d g e (l i t h o g r a p h y an d e t c h) er r or p er s i d e$ $W an d L : pl a t e w i d t h an d l e n g t h$ $a : s i d e o f a s q u a r e pl a t e (f i r s t - or d er f or m, ba c k g r o u n d k n o w l e d g e); K r a f t : ab so l u t e a cc u r a cy 10 t o 20 p er ce n t (10 t o 30 in t h e t ab l e), ma t c h e d p ai r s b e tt er t han 0.1 p er ce n t an d 0.02 t o 0.3 p er ce n t (7 t o 11 bi t), a s q u a r e l a y o u t minimi z es t h e p er im e t er - t o - a r e a r a t i o, o x i d e g r a d i e n t s c a l l f or co mm o n - ce n t r o i d l a y o u t, an d v a l u es a r e b u i l t f r o m i d e n t i c a l u ni t c a p a c i t or s; A l l e n : 10 p er ce n t ab so l u t e an d 0.1 p er ce n t r e l a t i v e f or M O S, 20 an d 0.1 p er ce n t f or p o l y - p o l y$ $(co m p u t e d : a 20 μ m s q u a r e pl a t e w i t h a 0.05 μ m e d g e er r or i s o f f b y 1 p er ce n t, w hi c h e q u a l u ni t c a p a c i t or s c an ce l in a r a t i o)$
Bottom-plate parasitic capacitance	$C_{b p} = α_{b p} C, α_{b p} = \frac{C _{b o tt o m \to s u b}}{C}$	$V_{o u t} = V_{in} \frac{C}{C + C _{b p} + C _{L}} (divider error)$	$C_{b p} : p a r a s i t i c c a p a c i t an ce o f t h e b o tt o m pl a t e t o t h e s u b s t r a t e$ $α_{b p} : i t s r a t i o t o t h e main c a p a c i t an ce$ $C : main c a p a c i t an ce$ $C_{L} : l o a d; K r a f t : t h e b o tt o m pl a t e o f a p o l y - d i f f u s i o n c a p a c i t or ha s a p a r a s i t i c d i o d e t o t h e s u b s t r a t e, an d f r in g e an d s t r a y c a p a c i t an ce o f p o l y - p o l y c a p a c i t or s c an b e o f t h e s am e or d er a s C_{0}, so c i r c u i t s m u s t b e in se n s i t i v e t o t h e m; N ik n e j a d an d B oser : p o l y - p o l y c a p a c i t or s ha v e b o tt o m - an d t o p - pl a t e p a r a s i t i cs an d a r e s hi e l d e d, an d p o l y - s u b s t r a t e c a p a c i t an ce i s ab o u t 120 aF/ μ m^{2}; co nn ec t in g t h e b o tt o m pl a t e t o t h e l o w - im p e d an ce n o d e i s t h e u s u a l r e m e d y (ba c k g r o u n d k n o w l e d g e)$ $(co m p u t e d : 120 aF/ μ m^{2} u n d er a 1000 aF/ μ m^{2} p o l y - p o l y c a p a c i t or i s α_{b p} = 12 p er ce n t i f t h e w h o l e pl a t e a r e a co u pl es t o t h e s u b s t r a t e (a ss u m e d))$

MOS Decoupling Capacitors

Name	Formula	Related Formulae	Variables/Constants
Channel resistance and cutoff of a MOS decoupling capacitor	$R_{c h, □} = \frac{1}{μ C _{o x} ( V _{GS} - V _{T H} )}, τ \approx \frac{R _{c h, □} C _{o x} L ^{2}}{12} = \frac{L ^{2}}{12 μ ( V _{GS} - V _{T H} )}$	$f_{c} = \frac{1}{2 π τ}, Q = \frac{1}{ω R _{s} C}$	$R_{c h, □} : s h ee t r es i s t an ce o f t h e in v er s i o n l a y er$ $μ : c hann e l m o bi l i t y$ $C_{o x} : o x i d e c a p a c i t an ce p er a r e a, V_{GS} - V_{T H} : g a t e o v er d r i v e$ $τ : t im e co n s t an t o f a c hann e l o f l e n g t h L co n t a c t e d a t b o t h e n d s (d i s t r ib u t e d R C, ba c k g r o u n d k n o w l e d g e)$ $f_{c} : cor n er f r e q u e n cy ab o v e w hi c h t h e c a p a c i t an ce f a l l s$ $Q : q u a l i t y f a c t or w i t h ser i es r es i s t an ce R_{s}; M e n g e t a l . (90 nm C M O S d ec a p ce l l s) : t hin - o x i d e M O S d e v i ces a r e u se d, e f f ec t i v e c a p a c i t an ce an d r es i s t an ce w er e m o d e l l e d f r o m 0 t o 10 GHz w i t h n o n - q u a s i - s t a t i c m o d e l s, n M O S d ec a p s p er f or m b e tt er a t hi g h f r e q u e n cy t han pM O S, a 5 x 15 μ m d e v i ce r o l l s o f f f a s t er t han s h or t er o n es, an d m or e f in g er s l o w er t h e r es i s t an ce b u t l ose a r e a t o co n t a c t s; N ik n e j a d an d B oser : co n t a c t in g a s t r u c t u r e a t b o t h e n d s l o w er s i t s e f f ec t i v e r es i s t an ce f o u r t im es$ $(co m p u t e d w i t h μ = 400 c m^{2} / (V s) an d 1 V o v er d r i v e (a ss u m e d) : f_{c} = 76, 3.1, 0.76 an d 0.34 GHz f or L = 1, 5, 10 an d 15 μ m, an d R_{c h, □} = 5700 Ω/ □ a t 4.4 fF/ μ m^{2})$
Gate leakage and depletion-mode decoupling	$I_{G} = J_{G} (t_{o x}, V) A$	$V_{D D} < V_{F B} \Rightarrow depletion: I_{G} ↓\approx 100 \times, C ↓\approx 25%$	$I_{G} : g a t e l e ak a g e o f a d eco u pl in g c a p a c i t or$ $J_{G} : t u nn e l l in g c u r r e n t d e n s i t y, w hi c h g r o w s s t ee pl y a s t_{o x} f a l l s$ $A : a r e a$ $V_{D D} : s u ppl y a cr oss t h e c a p a c i t or$ $V_{F B} : f l a t - ban d v o l t a g e; I n t e l : l e ak a g e b eco m es a p r o b l e m b e l o w ab o u t 30 \overset{˚}{A}, a d e pl e t i o n - m o d e c a p a c i t or w i t h V_{D D} b e l o w V_{F B} (ab o u t 1.0 V f or h e a v i l y d o p e d p o l y) r e d u ces l e ak a g e ab o u t 100 t im es f or a 1 V s u ppl y a t ab o u t 25 p er ce n t l ess c a p a c i t an ce, an d so m e n - w e l l s t r u c t u r es ha v e g oo d f r e q u e n cy r es p o n se b u t hi g h ser i es r es i s t an ce; M e n g e t a l . : pM O S g a t e l e ak a g e i s ab o u t t h r ee t im es s ma l l er t han n M O S f or t h e s am e s i z e, an d a cr oss - co u pl e d 1 N - 16 P l a y o u t c u t s l e ak a g e b y 62 p er ce n t a g ain s t a s t an d a r d 3 N - 4 P d ec a p$ $(co m p u t e d : r eco v er in g t h e 25 p er ce n t c a p a c i t an ce l oss n ee d s 33 p er ce n t m or e a r e a)$
ESD series resistance of a decoupling cell	$R_{E S D} \geq 500 Ω$	$V_{o x, E S D} \approx V_{E S D} \frac{Z _{C}}{R _{E S D} + Z _{C}}$	$R_{E S D} : minim u m ser i es r es i s t an ce b e tw ee n t h e s u ppl y r ai l an d t h e t hin g a t e$ $V_{o x, E S D} : o x i d e v o l t a g e d u r in g an E S D e v e n t o f V_{E S D}$ $Z_{C} : im p e d an ce o f t h e c a p a c i t or d u r in g t h e p u l se (d i v i d er f or m, ba c k g r o u n d k n o w l e d g e; E S D m o d e l s o n t h e E l ec t r i c a l S t r ess p a g e); M e n g e t a l . : a t 90 nm t h e d ec a p o x i d e c an b r e ak d o w n d u r in g E S D, so a minim u m o f 500 Ω i s t a r g e t e d, a s t an d a r d 3 N - 4 P d ec a p ha s o n l y ab o u t 30 Ω w hi l e t h e cr oss - co u pl e d v er s i o n ha s ab o u t 3500 Ω, an d t h e cr oss - co u pl e d 1 N - 16 P l a y o u t m ee t s t h e t a r g e t$ $(co m p u t e d : n o n e)$

Important Questions

Ques: What oxide thickness does a gate-oxide capacitance of 4.4 fF per square micrometre imply?

From $t_{o x} = ε_{0} ε_{r} / C_{o x}$ with $ε_{r} = 3.9$ , the GF180MCU values of 4.4 and 2.3 $fF/ μ m^{2}$ for its 3.3 and 6 $V$ gates correspond to about 7.8 and 15.0 $nm$ of SiO2, and the 5300 aF per square micrometre of Niknejad and Boser to 6.5 $nm$ (computed). The same process lists oxide breakdown at about 9 and 16 $V$ , fields of about 11 $MV/cm$ , so the rated voltages are about 37 per cent of breakdown (computed). The density is far above that of field-oxide or metal capacitors: Niknejad and Boser give about 120 aF per square micrometre for poly-substrate and 50 for metal-metal, so a 1 $nF$ capacitor needs about 0.19 $m m^{2}$ of gate oxide but tens of times more area otherwise (computed). Reference: GlobalFoundries GF180MCU PDK documentation, electrical specifications 5.3 ‘Gate oxide capacitance’ and 5.4 ‘Oxide Breakdown Voltage’ (fetch-tool summary); A. M. Niknejad and B. Boser, ‘EECS 240 Lecture 2: CMOS Technology and Passive Devices’, UC Berkeley (2006) (capacitor table partly garbled, fetch-tool summary).

Ques: Is the voltage coefficient of an on-chip oxide capacitor 7, 20 or 50 ppm per volt?

The sources measure different structures. Kraft gives 7 $ppm/V$ for a poly-diffusion capacitor and 10 to 100 $ppm/V$ in his summary, Allen gives $\pm 20$ $ppm/V$ for poly-oxide-semiconductor and $\pm 50$ $ppm/V$ for poly-poly, and Niknejad and Boser about 10 $ppm/V$ for poly-poly. All refer to plates of heavily doped poly or diffusion, where the depletion of either plate is small, and they differ through doping and oxide thickness. For a heavily doped poly-diffusion capacitor the low value of Kraft is the more likely one, and 10 to 50 $ppm/V$ is typical for poly-poly (my reading). A gate capacitor on lightly doped silicon is different: Niknejad and Boser describe its coefficient as huge, because it passes through depletion. Reference: M. Kraft, ‘ELEN0037 Microelectronic IC Design, Lecture 2: Technological Aspects’, University of Liege (year not stated) (fetch-tool summary); P. E. Allen, ‘ECE 6440 Frequency Synthesizers, Lecture 040: Integrated Circuit Technology - II’, Georgia Institute of Technology (2003) (fetch-tool summary); A. M. Niknejad and B. Boser, ‘EECS 240 Lecture 2: CMOS Technology and Passive Devices’, UC Berkeley (2006) (capacitor table partly garbled, fetch-tool summary); MOS Capacitor page of this vault (Basic Semiconductor Equations).

Ques: Why does a large MOS decoupling capacitor lose capacitance at high frequency?

Because the charge must reach the middle of the plate through the resistance of the inversion layer. A channel of length $L$ contacted at both ends behaves as a distributed RC line with a time constant of about $L^{2} / [12 μ (V_{GS} - V_{T H})]$ (background knowledge). With an assumed mobility of 400 $c m^{2} / (V s)$ and 1 $V$ of overdrive, the corner falls from about 76 $GHz$ at 1 $μ m$ to 0.76 $GHz$ at 10 $μ m$ and 0.34 $GHz$ at 15 $μ m$ (computed). Meng et al. found the same trend in 90 $nm$ decap cells: a 5 by 15 $μ m$ device rolled off faster, nMOS decaps worked better than pMOS at high frequency, and more fingers lowered the resistance but lost area to contacts. Short gates in parallel therefore give a better high-frequency decap. Reference: X. Meng, R. Saleh and K. Arabi, ‘Layout of Decoupling Capacitors in IP Blocks for 90-nm CMOS’, IEEE Transactions on VLSI Systems 16(11), 1581-1588 (2008) (fetch-tool summary); MOS Capacitor page of this vault (Basic Semiconductor Equations).

Ques: How can the gate leakage of thin-oxide decoupling capacitors be reduced?

Intel notes that leakage becomes a problem below about 30 $\overset{˚}{A}$ and proposes biasing the capacitor in depletion, with the supply below the flat-band voltage, about 1.0 $V$ for heavily doped poly. This removes most of the carriers that would tunnel through the oxide and reduces leakage by about 100 times for a 1 $V$ supply, at about 25 per cent less capacitance, which a 33 per cent larger area recovers (computed). Meng et al. take a layout route: pMOS decaps leak about three times less than nMOS ones of the same size, and their cross-coupled 1N-16P cell leaks 62 per cent less than a standard 3N-4P cell. Using a thicker I/O oxide is a third option, at a lower capacitance per area (background knowledge). Reference: Intel Corp., ‘Decoupling capacitors for thin gate oxides’, US Patent 6,828,638 B2 (2004) (fetch-tool summary); X. Meng, R. Saleh and K. Arabi, ‘Layout of Decoupling Capacitors in IP Blocks for 90-nm CMOS’, IEEE Transactions on VLSI Systems 16(11), 1581-1588 (2008) (fetch-tool summary).

Ques: Why do decoupling cells need series resistance for ESD?

Because a thin gate oxide connected directly between the supply rails can break down during an electrostatic discharge. Meng et al. state that this is possible at 90 $nm$ and therefore require at least 500 $Ω$ of series resistance in the decap cell, which limits the voltage that reaches the gate during the pulse. A standard 3N-4P decap, with its gate tied directly to the rail, has only about 30 $Ω$ , while their cross-coupled design, in which each transistor’s gate is driven through the channel of the other, has about 3500 $Ω$ , and their 1N-16P layout meets the target while also leaking less. The added resistance must still be low enough for the decoupling to work at the frequencies of interest, which sets a maximum number of fingers in their design. Reference: X. Meng, R. Saleh and K. Arabi, ‘Layout of Decoupling Capacitors in IP Blocks for 90-nm CMOS’, IEEE Transactions on VLSI Systems 16(11), 1581-1588 (2008) (fetch-tool summary); Electrical Stress page of this vault.

Ques: How well do on-chip oxide capacitors match?

Much better in ratio than in absolute value. Kraft gives an absolute accuracy of 10 to 20 per cent but matched pairs better than 0.1 per cent, and 0.02 to 0.3 per cent in his summary, which corresponds to 7 to 11 bits; Allen gives 0.1 per cent relative accuracy for both MOS and poly-poly capacitors. The remaining error comes from oxide thickness gradients and edge errors: a 20 $μ m$ square plate with a 0.05 $μ m$ edge error is about 1 per cent off (computed), but identical unit capacitors share it, so their ratio is preserved. Kraft therefore recommends square units, which minimize the perimeter-to-area ratio, common-centroid placement against thickness gradients, and building every value from the same unit capacitor. Reference: M. Kraft, ‘ELEN0037 Microelectronic IC Design, Lecture 2: Technological Aspects’, University of Liege (year not stated) (fetch-tool summary); P. E. Allen, ‘ECE 6440 Frequency Synthesizers, Lecture 040: Integrated Circuit Technology - II’, Georgia Institute of Technology (2003) (fetch-tool summary).

Quartz 5

Explorer

MOS and Poly-Insulator Capacitors