Deep-Trench Capacitors

1. Theory

• Definition: A deep-trench capacitor is a capacitor formed on the walls of holes or trenches etched several to tens of micrometres into silicon, lined with a thin dielectric and filled with a conducting electrode, so that the dielectric area far exceeds the footprint (Infineon and IBM patent; Bunel and Lengignon).
• Area gain: For pores of width $w$, pitch $p$ and depth $d$ the area grows by about $1+4wd/p^2$, about 61 times for 1 $\mu \mathrm{m}$ pores at 2 $\mu \mathrm{m}$ pitch and 60 $\mu \mathrm{m}$ depth (computed), which gives 250 $nF/m{\mathrm{m}}^2$ in production with an oxide-nitride-oxide dielectric (Bunel and Lengignon; Murata).
• Two forms: Embedded trenches from the eDRAM process serve as on-chip decoupling in SOI processors, and discrete silicon capacitors made on dedicated wafers serve as packaged parts (Jayaraman et al.; US 6,825,545; Murata).
• Stability: Because the dielectric is a thin amorphous oxide-nitride, the capacitance changes only about +60 $ppm/K$ and about 0.1 per cent per volt, unlike ferroelectric ceramic dielectrics (Bunel and Lengignon; Murata).
• Parasitics: The resistance of the long, narrow trench fill and of the substrate plate sets the series resistance, while the short current path gives an ESL of tens of pH in discrete parts (Infineon and IBM patent; Murata).
• Leakage and reliability: A thicker oxide-nitride stack than a gate oxide, made possible by the area gain, keeps leakage at the nA level and failure rates of the order of 1 FIT or below (US 6,825,545; Bunel and Lengignon; Murata).

2. Working Principle

• Folding the plate: The trench sidewalls carry the dielectric into the third dimension, so a fixed footprint holds a dielectric area set by the perimeter and depth of each trench (Infineon and IBM patent; background knowledge for the geometry).
• Electrodes: The heavily doped silicon around the trench, the buried plate, forms one electrode and the doped polysilicon, SiGe or metal fill the other, with doping kept high so neither depletes (Infineon and IBM patent; Jayaraman et al.).
• Distributed resistance: The charge reaches the bottom of each trench through the fill, so each trench is a short distributed RC line; many trenches in parallel lower the total resistance, and the capacitance falls to half at a frequency set by this RC (Jayaraman et al.; background knowledge).
• Linear dielectric: In SiO2 and Si3N4 the polarization is nearly proportional to the field and hardly depends on temperature, so the capacitance follows the small expansion and permittivity drift of the stack rather than a ferroelectric transition (Bunel and Lengignon; background knowledge for the mechanism).

3. Applications

• On-chip decoupling in high-performance processors: Embedded deep-trench decaps in SOI processors with eDRAM, where they give several times the capacitance of gate-oxide decaps at lower leakage (Jayaraman et al.; US 6,825,545).
• DRAM and eDRAM storage: Trench storage capacitors of about 25 $\mathrm{fF}$ per cell; on the DRAM page (Infineon and IBM patent).
• High-temperature and high-stability discrete capacitors: Decoupling and filtering at 200 to 250 ${}^{\circ }\mathrm{C}$ in downhole, automotive and aerospace electronics, where ceramic capacitors lose too much capacitance (Bunel and Lengignon; Murata).
• Thin decoupling in packages: Silicon capacitors of 100 $\mu \mathrm{m}$ thickness or less mounted under processors or inside modules, close to the load, with low ESL (Murata).

Capacitance and Area

Name	Formula	Related Formulae	Variables/Constants
Area gain of a trench array	$G=\frac{A_{eff}}{A_{foot}}=1+\frac{4wd}{p^2}(\text{square pores of width }w,\text{pitch }p,\text{depth }d)$	$\frac{C}{A_{foot}}=G\frac{{\epsilon }_0{\epsilon }_r}{t_d},AR=\frac{d}{w}$	$\begin{array}{r}G:ratioofthedielectricareatothe\\ footprint\end{array}$ $\begin{array}{r}{A}_{eff}:dielectricareaincludingthe\\ sidewalls\end{array}$ $A_{foot}:footprint$ $w:porewidth$ $d:depth$ $\begin{array}{r}p:pitch,C/A_{foot}:capacitanceperfootprint\\ area,{\epsilon }_0{\epsilon }_r/t_d:planarcapacitanceper\\ areaofthedielectric\end{array}$ $\begin{array}{r}AR:aspectratio(geometry,background\\ knowledge;trenchbottomsneglected);\\ BunelandLengignon(IPDiAPICS):\\ reactive-ion-etchedmacroporearraysof\\ typically1\mu \mathrm{m}widthandaspectratiosup\\ to60,anoxide-nitride-oxidedielectric\\ withapolysilicontopelectrode,250\\ nF/m{\mathrm{m}}^{2}inproductionat11\mathrm{V}breakdownand\\ 550nF/m{\mathrm{m}}^{2}demonstratedwithhigher-k\\ layers;Murata:ultra-deeptrenchesgive\\ theactiveareaofabout80ceramiclayers\\ in100\mu \mathrm{m}thickness,anddensitiesfrom\\ 1.55nF/m{\mathrm{m}}^{2}at450\mathrm{V}to250nF/m{\mathrm{m}}^{2}at11\mathrm{V}\end{array}$ $\begin{array}{r}(computed:w=1\mu \mathrm{m},p=2\mu \mathrm{m}andd=60\mu \mathrm{m}\\ (assumedfromAR=60)giveG=61,so250\\ nF/m{\mathrm{m}}^2=250fF/\mu {\mathrm{m}}^{2}offootprintneeds\\ only4.1fF/\mu {\mathrm{m}}^{2}ofplanardielectric,an\\ EOTof8.4\mathrm{nm},orabout11.9\mathrm{nm}ofONO\\ with{\epsilon }_r=5.5(assumed),at11\mathrm{V}afieldof\\ 9.3MV/cm)\end{array}$
Capacitance of one deep trench	$C_{tr}=C_d{P}_{tr}d$	$\frac{C}{A_{cell}}=\frac{C_{tr}}{A_{cell}}$	$C_{tr}:capacitanceofonetrench$ $C_d:dielectriccapacitanceperarea$ $P_{tr}:trenchperimeter$ $d:depth$ $\begin{array}{r}{A}_{cell}:footprintpercell(sidewall\\ approximation,backgroundknowledge;\\ memorycellphysicsontheDRAMpage);\\ InfineonandIBM:DRAMandeDRAMtrenches\\ 4to8\mu \mathrm{m}deep,aspectratiosof10:1to\\ 20:1for256Mbitand40:1to60:1ormore\\ for1Gbitandabove,trenchareapercell\\ ofabout11.3,0.6and0.32\mu {\mathrm{m}}^{2}for4Mbit,\\ 256Mbitand1Gbit,andastored\\ capacitanceoftheorderof25\mathrm{fF}\end{array}$ $$\begin{gathered} \begin{array}{r}(computed:25\mathrm{fF}in0.6and0.32\mu {\mathrm{m}}^{2}ofcell\\ footprintis42and78fF/\mu {\mathrm{m}}^2;atrenchof\\ 0.15\mu \mathrm{m}diameterand8\mu \mathrm{m}depth(assumed)\\ has3.8\mu {\mathrm{m}}^{2}ofsidewallandneeds6.6fF/\mu \\ {\mathrm{m}}^2,anEOTof5.2\mathrm{nm})\end{array} \end{gathered}$$
Planar gate-oxide decoupling compared with trench decoupling	$\frac{J_G(t_{ox}-1\text{A˚})}{J_G(t_{ox})}\approx 2.5\text{to}3$	$A_{planar}=\frac{C_{tot}}{C_{ox}}$	$J_G:gatetunnellingcurrentdensity$ $t_{ox}:oxidethickness$ $\begin{array}{r}{A}_{planar}:areaneededbyaplanardecapof\\ total{C}_{tot}\end{array}$ $\begin{array}{r}{C}_{ox}:itscapacitanceperarea;US\\ 6,825,545:gateleakagerisesby2.5to3\\ timesperangstromofoxidescaling,\\ planargate-oxidedecapswith10to22\mathring{\mathrm{A}}\\ oxidesprovideonly0.6to0.8\mu \mathrm{F}perchip,\\ 1\mu \mathrm{F}needs0.54\mathrm{c}{\mathrm{m}}^2,andtrenchdecapswith\\ a4\mathrm{nm}oxidereach1.3\mu \mathrm{F}andabove1.5\mu \mathrm{F}\\ withdeepertrenchesinaconsiderably\\ smalleractivearea,withanexample\\ trenchof0.7\mu \mathrm{m}depthand0.28\mu \mathrm{m}width;\\ Jayaramanetal.:deep-trenchdecapshave\\ asignificantareaadvantageoverMOSand\\ MIMdecapsinsystem-levelsimulation;MOS\\ decapsontheMOSandPoly-Insulator\\ Capacitorspage\end{array}$ $\begin{array}{r}(computed:1\mu \mathrm{F}in0.54\mathrm{c}{\mathrm{m}}^{2}is18.5fF/\mu {\mathrm{m}}^2;\\ thinningby5\mathring{\mathrm{A}}raisestheleakage98to\\ 243times)\end{array}$

Series Resistance and Frequency

Name	Formula	Related Formulae	Variables/Constants
Series resistance and half-capacitance frequency	$R_{tr}=\frac{{\rho }_{fill}d}{A_{tr}},R_{eff}\approx \frac{R_{tr}}{3}$	$\tau \approx R_{eff}{C}_{tr},f_{C/2}\propto \frac{1}{R_{eff}C}$	$\begin{array}{r}{R}_{tr}:end-to-endresistanceofthetrench\\ fill\end{array}$ ${\rho }_{fill}:fillresistivity$ $d:depth$ $A_{tr}:cross-sectionofthefill$ $\begin{array}{r}{R}_{eff}:effectiveseriesresistanceofa\\ distributedtrench(factor1/3,background\\ knowledge)\end{array}$ $\tau :timeconstant$ $\begin{array}{r}{f}_{C/2}:frequencyatwhichtheeffective\\ capacitancehasfallentohalf;Infineon\\ andIBM:fillresistivitybelowabout5000\\ \mu \Omega \mathrm{cm}targeted,withdopedSiorSiGe\\ layersbelow50\mathrm{nm}(preferablyabout15\\ \mathrm{nm})forhigh-aspect-ratiotrenches;\\ Jayaramanetal.:high-k/metalgateanda\\ newplatedopinglowertheequivalent\\ seriesresistanceandimprovethe\\ half-capacitancefrequency3.5timesat32\\ \mathrm{nm},withfurthergainsat22\mathrm{nm};Buneland\\ Lengignon:discretetrenchcapacitorswith\\ ESRbelow150\mathrm{m\Omega }andESLbelow250\mathrm{pH};\\ Murata:ESLofabout6to100\mathrm{pH}andESR\\ ofabout14to300\mathrm{m\Omega }byfamily\end{array}$ $\begin{array}{r}(computed:5000\mu \Omega \mathrm{cm}over8\mu \mathrm{m}ina0.15\\ \mu \mathrm{m}diameterfillgives{R}_{tr}=22.6\mathrm{k\Omega }and{R}_{eff}=\\ 7.5\mathrm{k\Omega },sowith25\mathrm{fF}thetimeconstantis\\ 0.19\mathrm{ns}foronetrench;manytrenchesin\\ parallellowerRbytheirnumber)\end{array}$

Stability and Reliability

Name	Formula	Related Formulae	Variables/Constants
Temperature and voltage stability	$\frac{\Delta C}{C}=TCC\Delta T+VCCV$	$\frac{\Delta C}{C}/1000\mathrm{h}(\text{aging})$	$\Delta C/C:relativecapacitancechange$ $TCC:temperaturecoefficient$ $\Delta T:temperaturechange$ $VCC:voltagecoefficient$ $\begin{array}{r}V:appliedvoltage;BunelandLengignon:\\ +62ppm/K,linear,achangeof1.8per\\ centfromroomtemperatureto300{}^{\circ }Cfora\\ 100\mathrm{nF}0805part,againstmorethan60per\\ centforMLCC,andanearlyflatDC-bias\\ response;Murata:+60ppm/K(+80ppm/K\\ automotive),0.1percentpervolt(0.02\\ percentpervoltforsomefamilies)from\\ 0\mathrm{V}totheratedvoltage,andagingbelow\\ 0.001percentper1000\mathrm{h}\end{array}$ $\begin{array}{r}(computed:+62ppm/Kover275\mathrm{K}is1.7per\\ cent,consistentwiththemeasured1.8per\\ cent;at0.1percentpervoltan11\mathrm{V}\\ partchangesby1.1percentatfull\\ voltage)\end{array}$
Leakage, insulation resistance and failure rate	$R_{ins}=\frac{V_{rated}}{I_{leak}},{\tau }_{self}=R_{ins}C$	$\lambda [\mathrm{FIT}]=10^9\frac{\text{failures}}{\text{device hours}}$	$R_{ins}:insulationresistance$ $V_{rated}:ratedvoltage$ $I_{leak}:leakagecurrent$ ${\tau }_{self}:self-dischargetimeconstant$ $C:capacitance$ $\begin{array}{r}\lambda :failurerateinFIT;Buneland\\ Lengignon:below1\mathrm{nA}atworkingvoltage,\\ below2\mathrm{nA}at300{}^{\circ }C(3\mathrm{V}after120\mathrm{s}),\\ and1FITat225{}^{\circ }Cat60percent\\ confidence;Murata:about100\mathrm{G\Omega }atrated\\ voltagefor100\mathrm{nF}parts(10\mathrm{G\Omega }for10\mathrm{nF}\\ wire-bondparts),leakagedownto100\mathrm{pA},\\ FITbelow0.017,lifetimecharacterizedby\\ TDDBandtemperaturecycling,and\\ operationto150,200or250{}^{\circ }Cbyfamily\end{array}$ $\begin{array}{r}(computed:100\mathrm{G\Omega }with100\mathrm{nF}gives{\tau }_{self}=\\ 1\times 10^4\mathrm{s},about2.8\mathrm{h})\end{array}$

Important Questions

Ques: How does a deep trench reach 250 nF per square millimetre with an ordinary dielectric?

By multiplying the area. For a square array of pores of width $w$ at pitch $p$ and depth $d$, the sidewalls add $4wd$ per unit cell of area $p^2$, so the area gain is $1+4wd/p^2$. With the 1 $\mu \mathrm{m}$ pores and aspect ratio of 60 reported by Bunel and Lengignon, and an assumed 2 $\mu \mathrm{m}$ pitch, the gain is 61, so 250 $nF/m{\mathrm{m}}^2$ needs only 4.1 $fF/\mu {\mathrm{m}}^2$ of planar dielectric, an EOT of 8.4 $\mathrm{nm}$ or about 11.9 $\mathrm{nm}$ of oxide-nitride-oxide with an assumed permittivity of 5.5 (computed). That is about four times the EOT of an assumed 2 $\mathrm{nm}$ thin gate oxide, which explains the low leakage. Murata expresses the same gain as the active area of about 80 ceramic layers in 100 $\mu \mathrm{m}$ of silicon. Reference: C. Bunel and L. Lengignon (IPDiA), ‘Silicon Capacitors with extremely high stability and reliability ideal for high temperature applications’, IMAPS HiTEC 2012, Albuquerque, 273-277 (fetch-tool summary); Murata Manufacturing, ‘Silicon Capacitors’ product catalog CATSICAP1.5 (specifications as of March 2014) (fetch-tool summary).

Ques: Why are deep-trench decaps preferred over gate-oxide decaps in SOI processors?

Because thin gate oxides leak too much for the capacitance they give. US 6,825,545 notes that gate leakage rises 2.5 to 3 times per angstrom of oxide scaling, so thinning by 5 $\mathring{\mathrm{A}}$ raises it 98 to 243 times (computed), and that planar decaps with 10 to 22 $\mathring{\mathrm{A}}$ oxides give only 0.6 to 0.8 $\mu \mathrm{F}$ per chip, with 1 $\mu \mathrm{F}$ needing 0.54 $\mathrm{c}{\mathrm{m}}^2$, about 18.5 $fF/\mu {\mathrm{m}}^2$ (computed). Trench decaps with a 4 $\mathrm{nm}$ oxide gave 1.3 $\mu \mathrm{F}$, and above 1.5 $\mu \mathrm{F}$ with deeper trenches, in a smaller area. Jayaraman et al. confirm a significant area advantage over MOS and MIM decaps in system simulation and note that the trenches come from the eDRAM process at no extra cost. Reference: ‘On chip decap trench capacitor (DTC) for ultra high performance silicon on insulator (SOI) systems microprocessors’, US Patent 6,825,545 (assignee and year not in the text read) (fetch-tool summary); B. Jayaraman, S. Gupta, Y. Zhang, P. Goyal, H. Ho et al. (IBM), ‘Performance analysis and modeling of deep trench decoupling capacitor for 32 nm high-performance SOI processors and beyond’, IEEE ICICDT 2012, doi:10.1109/ICICDT.2012.6232872 (abstract only); MOS and Poly-Insulator Capacitors page of this vault.

Ques: Is the temperature coefficient of a trench silicon capacitor 60, 62 or 80 ppm per kelvin?

All three appear. Bunel and Lengignon give +62 $ppm/K$ for IPDiA’s PICS parts, measured as a 1.8 per cent rise from room temperature to 300 ${}^{\circ }\mathrm{C}$ on a 100 $\mathrm{nF}$ 0805 capacitor, and Murata’s later catalog of the same technology gives +60 $ppm/K$ for standard families and +80 $ppm/K$ for its automotive ATSC range. The 62 $ppm/K$ value over 275 $\mathrm{K}$ predicts 1.7 per cent (computed), consistent with the measurement, so it is the more likely value for the standard oxide-nitride stack, with 60 $ppm/K$ a rounded catalog figure (my reading). The higher automotive value probably reflects a different dielectric or electrode stack for the higher voltage rating (my reading). Either way the change is about 33 times smaller (computed) than the more than 60 per cent of a ceramic MLCC over the same range. Reference: C. Bunel and L. Lengignon (IPDiA), ‘Silicon Capacitors with extremely high stability and reliability ideal for high temperature applications’, IMAPS HiTEC 2012, Albuquerque, 273-277 (fetch-tool summary); Murata Manufacturing, ‘Silicon Capacitors’ product catalog CATSICAP1.5 (specifications as of March 2014) (fetch-tool summary).

Ques: What limits the high-frequency performance of an embedded deep-trench decap?

The series resistance of the long, narrow fill and of the buried plate. The Infineon and IBM patent targets a fill resistivity below about 5000 $\mu \Omega \mathrm{cm}$ for trenches 4 to 8 $\mu \mathrm{m}$ deep. A fill of 0.15 $\mu \mathrm{m}$ diameter and 8 $\mu \mathrm{m}$ length at that limit has 22.6 $\mathrm{k\Omega }$ end to end, about 7.5 $\mathrm{k\Omega }$ effective for a distributed line, so one 25 $\mathrm{fF}$ trench has a time constant of about 0.19 $\mathrm{ns}$ (computed, with the one-third factor as background knowledge). A decap array divides the resistance among thousands of trenches in parallel, but the per-trench RC still sets the frequency at which the capacitance falls to half. Jayaraman et al. report that high-k/metal gate and a new plate doping lowered the ESR and raised this frequency 3.5 times at 32 $\mathrm{nm}$, with further gains at 22 $\mathrm{nm}$. Reference: Infineon Technologies and IBM, ‘Low resistivity deep trench fill for DRAM and eDRAM applications’, US Patent 6,620,724 B1 (2003) (fetch-tool summary); B. Jayaraman, S. Gupta, Y. Zhang, P. Goyal, H. Ho et al. (IBM), ‘Performance analysis and modeling of deep trench decoupling capacitor for 32 nm high-performance SOI processors and beyond’, IEEE ICICDT 2012, doi:10.1109/ICICDT.2012.6232872 (abstract only).

Ques: Is the failure rate of a trench silicon capacitor 1 FIT or below 0.017 FIT?

The two values describe different conditions. Bunel and Lengignon quote 1 FIT at 225 ${}^{\circ }\mathrm{C}$ at 60 per cent confidence for IPDiA parts, a high-temperature figure from life tests in which few or no failures occurred, so it is an upper bound set mainly by the test hours. Murata gives below 0.017 FIT in its catalog, most likely at ordinary operating conditions and derived with acceleration from TDDB and temperature-cycling tests (my reading). Since the TDDB lifetime of the dielectric falls steeply with temperature and voltage, a value about 60 times lower (computed) at normal use is plausible (my reading). The 0.017 FIT value is therefore the more likely one for room-temperature use and 1 FIT for 225 ${}^{\circ }\mathrm{C}$. Both are far below typical ceramic capacitor figures (background knowledge). Reference: C. Bunel and L. Lengignon (IPDiA), ‘Silicon Capacitors with extremely high stability and reliability ideal for high temperature applications’, IMAPS HiTEC 2012, Albuquerque, 273-277 (fetch-tool summary); Murata Manufacturing, ‘Silicon Capacitors’ product catalog CATSICAP1.5 (specifications as of March 2014) (fetch-tool summary).

Ques: How much capacitance per footprint does a DRAM trench cell reach?

The Infineon and IBM patent gives a stored capacitance of the order of 25 $\mathrm{fF}$ and a trench area per cell of about 11.3, 0.6 and 0.32 $\mu {\mathrm{m}}^2$ for 4 Mbit, 256 Mbit and 1 Gbit DRAMs, so the footprint density is about 42 $fF/\mu {\mathrm{m}}^2$ at 256 Mbit and 78 $fF/\mu {\mathrm{m}}^2$ at 1 Gbit (computed), ten to twenty times a planar gate oxide. To keep 25 $\mathrm{fF}$ as the footprint shrinks, the trench must get deeper relative to its width, from aspect ratios of 10:1 to 20:1 at 256 Mbit to 40:1 to 60:1 at 1 Gbit. A trench of 0.15 $\mu \mathrm{m}$ diameter and 8 $\mu \mathrm{m}$ depth, both assumed, has 3.8 $\mu {\mathrm{m}}^2$ of sidewall and needs 6.6 $fF/\mu {\mathrm{m}}^2$, an EOT of 5.2 $\mathrm{nm}$ (computed). The narrow fill then limits the read speed, which is why low-resistivity fills were developed. Reference: Infineon Technologies and IBM, ‘Low resistivity deep trench fill for DRAM and eDRAM applications’, US Patent 6,620,724 B1 (2003) (fetch-tool summary); Dynamic Random Access Memory (DRAM) page of this vault.

Related pages in this vault: MOS and Poly-Insulator Capacitors, MIM and MOM Capacitors, Dynamic Random Access Memory (DRAM), Static and Dynamic Random Access Memory (SRAM and DRAM), Power Delivery Networks, Silicon on Insulator (SOI) MOSFET, MOS Varactors, Wire Capacitance and Low-k Dielectrics.