1. Theory
- Definition: RF compact modelling adds to the core MOSFET model the elements that matter at GHz frequencies: the distributed gate resistance, the substrate resistance network, extrinsic capacitances, and non-quasi-static (NQS) delay of the channel charge (Cheng; Shin et al.).
- Gate resistance: The gate’s sheet resistance, distributed along each finger, appears as an effective series resistance of about one third or one twelfth of the finger resistance, which limits and adds noise (Cheng; background knowledge for the noise).
- Substrate network: The drain and source junctions couple to the resistive substrate, which changes the output admittance by 20 per cent or more at RF (Cheng).
- Non-quasi-static effects: The channel charge cannot follow the terminal voltages instantly; when signals change on the scale of the transit time , the quasi-static assumption fails (Cheng).
- Validity: Quasi-static models with gate resistance are accurate to about half of , while models with NQS and distributed elements match measured Y-parameters up to and above (Cheng; Shin et al.).
2. Working Principle
- Distributed RC along the finger: The gate signal travels along each finger through the gate resistance while charging the gate capacitance, so the input looks like a lossy line whose real part is a fraction of the finger resistance (Cheng; background knowledge for the line picture).
- Channel resistance at the input: The gate charge reaches the channel through the channel resistance, adding a bias-dependent intrinsic input resistance, which BSIM4 includes with its gate resistance (Cheng; BSIM4.3.0 manual).
- Charge deficit: In the NQS model the channel charge relaxes toward its quasi-static value with a time constant set by drift and diffusion, which delays the response and adds phase shift to the transadmittance (BSIM4.3.0 manual; background knowledge for the relaxation form).
- Substrate coupling: High-frequency current through the junction capacitances returns through the substrate resistance, adding a real part to the output and input admittances (Cheng; Shin et al.).
3. Applications
- RF CMOS design kits: Subcircuit or built-in RF models with gate resistance, substrate network and NQS for LNAs, mixers, VCOs and PAs (Cheng; Shin et al.).
- Layout optimization: Finger width, number of fingers and double-sided gate contacts to reduce gate resistance and raise (Cheng; computed).
- Millimetre-wave design: Models verified to 80 to 110 for 60 and higher circuits (Shin et al.).
- Noise modelling: Gate resistance and substrate resistance as additional thermal-noise sources alongside channel noise (MOSFET Noise Models page; background knowledge).
Gate Resistance and Figures of Merit
| Name | Formula | Related Formulae | Variables/Constants |
|---|---|---|---|
| Distributed gate resistance | |||
| Transition and maximum oscillation frequencies |
Non-Quasi-Static Effects
| Name | Formula | Related Formulae | Variables/Constants |
|---|---|---|---|
| Channel transit time and non-quasi-static delay | |||
| Charge-deficit NQS model |
Substrate Network
| Name | Formula | Related Formulae | Variables/Constants |
|---|---|---|---|
| Substrate resistance network |
Important Questions
Ques: How much does the gate contact arrangement change the gate resistance?
By a factor of four. Cheng states that the distributed gate resistance is the gate sheet resistance times a factor of 1/3 or 1/12, depending on the gate connection: 1/3 when each finger is contacted at one end and 1/12 when it is contacted at both ends (background knowledge for the assignment). For an assumed 10 gate on Shin et al.’s layout of 16 fingers of 1.8 by 0.13 , one-sided contacts give 46 per finger and 2.9 in total, while double-sided contacts give 11.5 and 0.72 (computed). Narrow fingers matter as much: the resistance per finger scales with its width, which is why Cheng recommends multi-finger layouts. The intrinsic input resistance of the channel, about in long channels (background knowledge), is 6.9 at 28.8 (computed), comparable to the electrode part. Reference: Y. Cheng (Skyworks Solutions), ‘Advanced MOSFET Modeling for RF IC Design’, NSTI-Nanotech 2004, Vol. 2 (fetch-tool summary); H. Shin, I. M. Kang, J. W. Jeon and J. Gil, ‘Active and Passive RF Device Compact Modeling in CMOS Technologies’, SISPAD 2006, 17-22 (fetch-tool summary).
Ques: How does gate resistance limit the maximum oscillation frequency?
Through (background knowledge). For the 16-finger, 0.13 layout with an assumed 1 per micrometre of width and 1.2 of gate capacitance, is about 133 (computed). With and 0.4 of , is about 350 with 2.9 of gate resistance and about 700 with 0.72 (computed), since it scales as . Real devices also have source resistance, gate-electrode contact resistance and the intrinsic input resistance, so measured values are lower (my reading). The calculation shows why RF layouts use double-sided gate contacts and short fingers, and why models must include the gate resistance to predict power gain. Reference: Y. Cheng (Skyworks Solutions), ‘Advanced MOSFET Modeling for RF IC Design’, NSTI-Nanotech 2004, Vol. 2 (fetch-tool summary); H. Shin, I. M. Kang, J. W. Jeon and J. Gil, ‘Active and Passive RF Device Compact Modeling in CMOS Technologies’, SISPAD 2006, 17-22 (fetch-tool summary).
Ques: Are RF MOSFET models valid only to half of fT, or up to and above fT?
It depends on the model. Cheng reports that the simple gate-resistance model is accurate to about half of , and validates his BSIM3v3-based subcircuit, with a substrate network, to 10 , about half of the roughly 30 of his 0.25 process. Shin et al.’s model, which adds distributed channel resistances, a transport-delay element and a DIBL-related source-drain capacitance to a BSIM4 core, matched measured Y-parameters up to and above through 110 , and its S-parameters to about 80 . The two claims are consistent: quasi-static models with lumped gate resistance work to about half of , and NQS or distributed elements are needed beyond that (my reading). Reference: Y. Cheng (Skyworks Solutions), ‘Advanced MOSFET Modeling for RF IC Design’, NSTI-Nanotech 2004, Vol. 2 (fetch-tool summary); H. Shin, I. M. Kang, J. W. Jeon and J. Gil, ‘Active and Passive RF Device Compact Modeling in CMOS Technologies’, SISPAD 2006, 17-22 (fetch-tool summary).
Ques: When do non-quasi-static effects become important?
When signals change on the time scale of the channel transit time. Cheng notes that quasi-static models ignore the carrier charging time and that NQS effects matter when rise and fall times approach the transit time, which scales roughly as . With , an assumed 0.13 channel with 300 and 0.5 overdrive gives 1.13 , a corner near 141 , while the intrinsic long-channel of is about 212 (computed, background knowledge for the forms). NQS effects therefore appear near , and much earlier in long channels or at low overdrive, as in analog RF bias points. Cheng lists four ways to include them: a bias-dependent gate resistance, an input resistance, a transadmittance source, or the core model. Reference: Y. Cheng (Skyworks Solutions), ‘Advanced MOSFET Modeling for RF IC Design’, NSTI-Nanotech 2004, Vol. 2 (fetch-tool summary).
Ques: Why must the substrate network be modelled at RF?
Because it changes the output admittance and isolation. Cheng reports that substrate resistance can contribute 20 per cent or more of the total output admittance at RF, through resistances between source, drain and bulk and the junction capacitances, with analytical values depending on substrate doping, isolation spacing and depth and layout, accurate to 10 . Shin et al. extract a pi-type substrate network by a three-port measurement from the Y-parameters, and their BSIM4-based macro-model matches S-parameters to about 80 at 25 and to about 70 at 125 . At low frequency the junction capacitances isolate the substrate, but above about the substrate resistance appears in the output, lowering the output resistance and adding noise (background knowledge). BSIM4 includes a flexible built-in substrate network for this. Reference: Y. Cheng (Skyworks Solutions), ‘Advanced MOSFET Modeling for RF IC Design’, NSTI-Nanotech 2004, Vol. 2 (fetch-tool summary); H. Shin, I. M. Kang, J. W. Jeon and J. Gil, ‘Active and Passive RF Device Compact Modeling in CMOS Technologies’, SISPAD 2006, 17-22 (fetch-tool summary); BSIM4.3.0 MOSFET Model User’s Manual, University of California, Berkeley (2003) (Chapter 8 headings only in the excerpt) (fetch-tool summary).
Ques: Is a substrate-resistance temperature coefficient of 3760 ppm per kelvin plausible?
Yes. Shin et al. report a substrate-resistance temperature coefficient of 3760 , a value the extract flags as possibly mistyped. Silicon resistivity in moderately to lightly doped substrates rises with temperature because phonon scattering lowers the mobility, roughly as to near room temperature, which gives about 0.5 to 0.8 per cent per kelvin at 300 (background knowledge). A coefficient of 0.376 per cent per kelvin is somewhat below this range but plausible for a more heavily doped substrate, where ionized-impurity scattering weakens the temperature dependence (my reading). Over 100 it would raise the substrate resistance by about 38 per cent (computed), which matters for RF models used at 125 , as in Shin et al.’s model, which still tracked S-parameters to about 70 . Reference: H. Shin, I. M. Kang, J. W. Jeon and J. Gil, ‘Active and Passive RF Device Compact Modeling in CMOS Technologies’, SISPAD 2006, 17-22 (fetch-tool summary).
Related pages in this vault: MOSFET Noise Models, BSIM3 and BSIM4, Charge-Based Models (EKV), Charge and Capacitance Modelling, Multi-Gate Models (BSIM-CMG and BSIM-IMG), ASM-HEMT Model, MVSG Model, MOS Varactors, Vector Network Analyzer (VNA).