This page covers the degradation of AlGaN/GaN high electron mobility transistors, both the normally-off power devices with a p-GaN or MIS gate and the RF devices with a Schottky gate. The general breakdown and overstress models are on the Electrical Stress page and the solder fatigue of chip-scale packages on the Mechanical and Package Stress page; this page covers trapping, the field-driven damage of the barrier and the gate stack, and the limits that come from them.
1. Why It Happens
- Trigger: A high drain voltage in the off state and during hard switching, which puts electrons into traps of the surface, the passivation and the carbon-doped buffer (Jin and del Alamo; Yang et al.; EPC Phase 12); a high vertical field at the drain-side gate edge in RF devices (Joh); a forward gate voltage on a p-GaN gate (EPC Phase 12; Zhou et al.).
- Mechanism, dynamic on-resistance: Electrons captured in the gate-drain access region deplete the two-dimensional electron gas, so the on-resistance right after switching is higher than in DC and recovers slowly; under hard switching, hot electrons scatter into surface traps and the rise grows as the logarithm of time (EPC Phase 12; Jin and del Alamo).
- Mechanism, inverse piezoelectric damage: The vertical field adds tensile strain to the strained AlGaN barrier, and when the elastic energy exceeds a critical value, crystal defects form at the gate edge, which trap electrons and conduct gate current (Joh).
- Mechanism, gate failure: In a p-GaN gate, impact ionisation creates holes that are trapped in the nitride at the gate corners until it ruptures (EPC Phase 12), and the Schottky junction on the p-GaN breaks down in time (Zhou et al.); in MIS gates, traps accumulate into a percolation path (Yang and Yuan).
- What sets the rate: The drain voltage and the switching conditions, the buffer and passivation chemistry, and the temperature, which speeds the emission of trapped charge (Yang et al.; EPC Phase 12); the gate-edge field and any applied strain for barrier damage (Joh); the gate voltage, the switching frequency and the temperature for the gate (EPC Phase 12; Wang et al.).
- Failure criterion: A 20 per cent rise of the on-resistance (EPC Phase 12); a 5 per cent drop of defines the critical voltage in step-stress tests (Joh); a sudden rise of the gate leakage, or 1 in MIS gates (Zhou et al.; Yang and Yuan).
2. Where to Look
- Location: The gate-drain access region and the field-plate edges for trapping (Yang et al.); the drain-side edge of the gate for barrier damage (Joh); the corners of the p-GaN gate (EPC Phase 12); the carbon-doped buffer under the drift region (Yang et al.).
- Signature: An on-resistance that is tens of per cent higher within microseconds of turn-on and relaxes over seconds to thousands of seconds (Jin and del Alamo; Yang et al.); a reverse gate current that rises by about three orders of magnitude at the critical voltage (Joh); a rising forward gate leakage before gate failure, which does not recover even after a bake (Wang et al.); SWIR emission at high-field spots under drain stress (EPC Phase 12).
- Confirm with: Pulsed I-V from 200 and drain-current transient spectroscopy over many decades of time and several temperatures (Jin and del Alamo); step-stress at increasing drain-gate voltage (Joh); gate step-stress and circuit-based switching stress of the gate (Wang et al.); electroluminescence and sense-node potential measurements (Yang et al.).
- Look-alikes: Self-heating also raises the on-resistance; Yang et al. checked that their stress currents were the same before blaming trapping. A dynamic on-resistance that recovers is trapping, not permanent damage, while a gate leakage increase that survives a bake is permanent (Wang et al.).
3. Prevention
- Design: Field plates and a longer gate-drain spacing spread the field at the gate edge (Yang et al.; Joh); keep the gate overshoot of a p-GaN device below the rated value, using the circuit method of Wang et al. to measure it, since 0.75 less voltage gives about a thousand times longer life (EPC Phase 12).
- Material and process: Si-rich passivation suppresses both surface and buffer trapping (Yang et al.); an undoped GaN cap on the p-GaN raises the 10 year gate voltage from 6.2 to 10.6 (Zhou et al.); a buffer design whose channel is leaky enough to stop the back-gating of the carbon-doped layer (Yang et al.).
- Operation: Keep the channel temperature low for RF devices, since the life falls by orders of magnitude over 100 (Joh); for power devices the dynamic on-resistance slope falls with temperature, so cold hard switching is the worst case (EPC Phase 12).
- Screening and test: Dynamic on-resistance tests under the application’s hard-switching conditions with long-term projection (EPC Phase 12); gate tests under switching rather than DC (Wang et al.); underfill for chip-scale devices, which raised the cycling life by more than 100 times (EPC Phase 12).
Trapping and Dynamic On-Resistance
| Name | Formula | Related Formulae | Variables/Constants |
|---|---|---|---|
| Emission time of a trap and its temperature dependence | |||
| Dynamic on-resistance and its lifetime criterion |
Barrier Damage and Thermal Wear-Out
| Name | Formula | Related Formulae | Variables/Constants |
|---|---|---|---|
| Elastic energy from the inverse piezoelectric effect | |||
| Thermally activated wear-out of RF GaN HEMTs |
Gate Reliability
| Name | Formula | Related Formulae | Variables/Constants |
|---|---|---|---|
| Gate lifetime of a p-GaN gate under forward bias | |||
| Weibull slope and percolation in a GaN MIS gate |
Drain Stress and Short Circuit
| Name | Formula | Related Formulae | Variables/Constants |
|---|---|---|---|
| Hot-electron trapping under drain bias and the short-circuit limit |
Important Questions
Ques: How large is the dynamic on-resistance increase of a GaN HEMT?
It depends on the stress and the passivation. Jin and del Alamo measure 73 and 52 per cent above DC at 200 after a 40 off-state stress on two wafers. Yang et al. find less than 10 per cent after off-state stress at 40 but about 60 per cent after on-state stress at 40 and 0.18 , where hot electrons are involved, on stoichiometric passivation, and much less with Si-rich passivation. EPC defines its lifetime as a 20 per cent rise and models the growth as the logarithm of time. The values are therefore not one number: the on-state or hard-switching value is the more relevant for power converters, and the off-state value alone underestimates it (my reading). Reference: D. Jin and J. A. del Alamo, ‘Mechanisms responsible for dynamic ON-resistance in GaN high-voltage HEMTs’, Proc. ISPSD 2012, Bruges (MIT copy, fetch-tool summary); F. Yang, M. J. Uren, M. Gajda, S. Dalcanale, J. W. Pomeroy and M. Kuball, ‘Suppression of charge trapping in ON-state operation of AlGaN/GaN HEMTs by Si-rich passivation’, Semiconductor Science and Technology 36(9), 095024 (2021) (Bristol repository copy, fetch-tool summary); EPC, ‘eGaN Device Reliability Testing: Phase 12’, 2021 (fetch-tool summary; several equations garbled).
Ques: What activation energy does the trapping in GaN buffers have: 0.45 or 0.8 electronvolts?
Both are reported. The carbon acceptor of the buffer is usually quoted at 0.8 to 0.9 above the valence band, and Jin and del Alamo find dominant traps at 0.76 to 0.82 on one wafer. Yang et al. measure 0.44 to 0.48 and note that many reports give 0.5 to 0.6 . They explain the low values by hopping through a carbon defect band at densities near , so the measured energy is a transport barrier, not a level. The 0.8 value is therefore more likely to be the level of the acceptor, and the lower values describe the rate of the redistribution in heavily doped buffers. The choice matters: from 25 to 150 emission speeds up 356 times for 0.45 and times for 0.8 (computed). Reference: F. Yang, M. J. Uren, M. Gajda, S. Dalcanale, J. W. Pomeroy and M. Kuball, ‘Suppression of charge trapping in ON-state operation of AlGaN/GaN HEMTs by Si-rich passivation’, Semiconductor Science and Technology 36(9), 095024 (2021) (Bristol repository copy, fetch-tool summary); D. Jin and J. A. del Alamo, ‘Mechanisms responsible for dynamic ON-resistance in GaN high-voltage HEMTs’, Proc. ISPSD 2012, Bruges (MIT copy, fetch-tool summary).
Ques: Is hot-electron damage or the field the cause of the degradation of RF GaN HEMTs?
Joh concludes that it is the field. Above a critical drain-gate voltage the drain resistance rises, the maximum current falls and the reverse gate current rises by nearly three orders of magnitude, and this happens even at a stress current below 1 , so hot electrons are not the direct cause in his devices. The critical voltage falls by about 2 when 0.065 to 0.076 per cent tensile strain is applied, which supports the inverse piezoelectric picture: the vertical field adds strain to the barrier until the elastic energy is large enough to form defects. EPC, in contrast, attributes the drain-bias failures and the dynamic on-resistance of its power devices to hot-electron trapping. Both can be right, since the RF devices are stressed off-state at high field and the power devices under switching (my reading). Reference: J. Joh, ‘Physics of electrical degradation in GaN high electron mobility transistors’, PhD thesis, MIT, 2009 (DSpace copy, fetch-tool summary of the first 100,000 characters; chapter 4 model not read); EPC, ‘eGaN Device Reliability Testing: Phase 12’, 2021 (fetch-tool summary; several equations garbled).
Ques: Why is the projected life of an RF GaN HEMT so uncertain?
Because the activation energy is not agreed. Joh quotes about 150 at a 300 junction with activation energies between 1.05 and 2 in industry reports, and one report even gave -0.15 . Extrapolated to a 150 channel, 1.05 gives and 2 gives , three orders of magnitude apart (computed). The high test temperature can also switch on mechanisms that do not occur at use, which is one reason for the spread. A projection should therefore be made at several stress temperatures close to use, and the channel temperature must include self-heating: GaN conducts only 107 at 400 against 160 at room temperature (computed). The lower energy is the safer value for design (my reading). Reference: J. Joh, ‘Physics of electrical degradation in GaN high electron mobility transistors’, PhD thesis, MIT, 2009 (DSpace copy, fetch-tool summary of the first 100,000 characters; chapter 4 model not read); F. Yang, M. J. Uren, M. Gajda, S. Dalcanale, J. W. Pomeroy and M. Kuball, ‘Suppression of charge trapping in ON-state operation of AlGaN/GaN HEMTs by Si-rich passivation’, Semiconductor Science and Technology 36(9), 095024 (2021) (Bristol repository copy, fetch-tool summary).
Ques: What is the safe gate voltage of a p-GaN HEMT for ten years: 6, 7 or 10 volts?
The sources measure different things. Zhou et al. find 6.2 at 1 per cent for a standard p-GaN gate and 10.6 with a u-GaN cap, from DC stress at room temperature. Wang et al. stress the gate in switching and find that the life is set by the number of cycles: at 125 and 100 kHz the 10 year limit is 5.7 at 0.1 per cent and 7.6 at 63 per cent, and about 5 higher in hard switching. EPC gives below 1 ppm at 5.25 and 10 to 100 ppm at 6 . For a hard-switched design the switching values of Wang et al. are the more likely to apply, while the DC values of Zhou et al. compare gate structures. All three agree that about 6 is the safe range for a standard gate. Reference: G. Zhou, F. Zeng, R. Gao, Q. Wang, K. Cheng, G. Xia and H. Yu, ‘Improved Gate Reliability of p-GaN Gate HEMTs by Gate Doping Engineering’, arXiv:2106.01495 (venue and year not stated) (fetch-tool summary); B. Wang, R. Zhang, Q. Song, H. Wang, Q. He, Q. Li, F. Udrea and Y. Zhang, ‘Gate Robustness and Reliability of P-Gate GaN HEMT Evaluated by a Circuit Method’, IEEE Transactions on Power Electronics (year not stated, references to 2023; NSF PAR copy) (fetch-tool summary); EPC, ‘eGaN Device Reliability Testing: Phase 12’, 2021 (fetch-tool summary; several equations garbled).
Ques: Do the Weibull slopes of p-GaN and MIS gates show wear-out or random failure?
The sources disagree for p-GaN gates. Zhou et al. report shape factors of 0.74 to 0.87 under DC stress, below 1, which means a falling failure rate, while Wang et al. report slopes above 1, wear-out, in all their switching tests. Yang and Yuan find about 1.91 for MIS gates, which falls below 1 when a large negative substrate bias makes the failures extrinsic. A slope below 1 in a DC test points to defect-related early failures or to a test at too high a field, so the switching data with a slope above 1 are more likely to describe the intrinsic gate (my reading). The difference matters: the 1 per cent time is 0.090 of the scale time for a slope of 1.91 and 0.0032 for 0.8 (computed). Reference: G. Zhou, F. Zeng, R. Gao, Q. Wang, K. Cheng, G. Xia and H. Yu, ‘Improved Gate Reliability of p-GaN Gate HEMTs by Gate Doping Engineering’, arXiv:2106.01495 (venue and year not stated) (fetch-tool summary); B. Wang, R. Zhang, Q. Song, H. Wang, Q. He, Q. Li, F. Udrea and Y. Zhang, ‘Gate Robustness and Reliability of P-Gate GaN HEMT Evaluated by a Circuit Method’, IEEE Transactions on Power Electronics (year not stated, references to 2023; NSF PAR copy) (fetch-tool summary); W. Yang and J.-S. Yuan, ‘Substrate Bias Enhanced Trap Effects on Time-Dependent Dielectric Breakdown of GaN MIS-HEMTs’, IEEE Transactions on Electron Devices 68(5), 2233-2239 (2021) (NSF PAR copy, fetch-tool summary).
Ques: How sensitive is the projected life to the slope of the dynamic on-resistance?
Extremely, because the rise grows as the logarithm of time. With and an assumed , a slope of 0.01 per log unit reaches the 20 per cent end of life after 15 years, 0.02 after 6 and 0.03 after 13 min (computed). This simplified form stands for the EPC model, whose equation was garbled in the text read, but EPC uses the same log-time growth and the same 20 per cent criterion, and its 1150 h test predicted 15 years within 10 per cent. The slope falls with temperature in their data, so the lowest operating temperature and the highest drain voltage of the mission set the life. Reference: EPC, ‘eGaN Device Reliability Testing: Phase 12’, 2021 (fetch-tool summary; several equations garbled).
Ques: Why does a chip-scale GaN transistor need underfill?
Because its solder joints carry the full thermomechanical stress. EPC reports that EPC2001C without underfill had 2 of 32 failures after 1250 cycles from -40 to 125 and 26 of 32 after 2450 cycles, and that board bending to 6 raises the peak tensile stress in the solder to about N/m2, about twice the N/m2 yield of SAC305. With a suitable underfill, intermittent operation of EPC2206 between 40 and 150 reached 53,000 cycles with no failure, more than 100 times longer. EPC asks for an underfill with a CTE of 16 to 32 ppm per K, against about 24 for the solder, a modulus of 6 to 13 and a glass transition well above the maximum temperature. The solder models themselves are on the Mechanical and Package Stress page. Reference: EPC, ‘eGaN Device Reliability Testing: Phase 12’, 2021 (fetch-tool summary; several equations garbled); Mechanical and Package Stress page of this vault.
References
- D. Jin and J. A. del Alamo, ‘Mechanisms responsible for dynamic ON-resistance in GaN high-voltage HEMTs’, Proc. ISPSD 2012, Bruges (MIT copy, fetch-tool summary).
- F. Yang, M. J. Uren, M. Gajda, S. Dalcanale, J. W. Pomeroy and M. Kuball, ‘Suppression of charge trapping in ON-state operation of AlGaN/GaN HEMTs by Si-rich passivation’, Semiconductor Science and Technology 36(9), 095024 (2021) (Bristol repository copy, fetch-tool summary).
- EPC, ‘eGaN Device Reliability Testing: Phase 12’, 2021 (fetch-tool summary; several equations garbled).
- J. Joh, ‘Physics of electrical degradation in GaN high electron mobility transistors’, PhD thesis, MIT, 2009 (DSpace copy, fetch-tool summary of the first 100,000 characters; chapter 4 model not read).
- G. Zhou, F. Zeng, R. Gao, Q. Wang, K. Cheng, G. Xia and H. Yu, ‘Improved Gate Reliability of p-GaN Gate HEMTs by Gate Doping Engineering’, arXiv:2106.01495 (venue and year not stated) (fetch-tool summary).
- B. Wang, R. Zhang, Q. Song, H. Wang, Q. He, Q. Li, F. Udrea and Y. Zhang, ‘Gate Robustness and Reliability of P-Gate GaN HEMT Evaluated by a Circuit Method’, IEEE Transactions on Power Electronics (year not stated, references to 2023; NSF PAR copy) (fetch-tool summary).
- W. Yang and J.-S. Yuan, ‘Substrate Bias Enhanced Trap Effects on Time-Dependent Dielectric Breakdown of GaN MIS-HEMTs’, IEEE Transactions on Electron Devices 68(5), 2233-2239 (2021) (NSF PAR copy, fetch-tool summary).
- Mechanical and Package Stress page of this vault.
- J. Joh and J. A. del Alamo, ‘Critical Voltage for Electrical Degradation of GaN High-Electron Mobility Transistors’, IEEE Electron Device Letters 29(4), 287-289 (2008), doi:10.1109/LED.2008.917815. Available: https://dspace.mit.edu/handle/1721.1/59403.
- Temperature Acceleration Models (Arrhenius and Eyring) page of this vault.
Related pages in this vault: Electrical Stress, SiC and Ga2O3 Power Devices, Mechanical and Package Stress, GaAs and InP HEMT, MESFET and HBT, GaN HEMT, CMOS Logic Transistors, Silicon Power MOSFET, IGBT and Thyristors, Bipolar Transistors (BJT and SiGe HBT), GaAs InP High Electron Mobility Transistor (HEMT).