This page covers the wear-out of the transistors of CMOS logic: planar bulk and SOI MOSFETs with a high-k metal gate, FinFETs and gate-all-around nanosheets. The physics of the general mechanisms (oxide breakdown models, the hot-carrier lucky-electron model, the BTI power law and its recovery) is on the Electrical Stress page, and the thermal models on the Thermal Stress page; this page covers what changes when the gate stack is high-k on a thin interfacial layer, the channel is a few nanometres wide and the device holds only a few defects.

1. Why It Happens

Trigger: A gate bias at operating temperature, which charges defects in the oxide (BTI), a drain bias that heats the channel carriers (hot-carrier degradation), and a gate field held for years (dielectric breakdown) (Kaczer et al. 2018; Tyaginov et al.; Tao et al.). In fins and nanosheets the device heats itself, which raises the temperature of all three (Chhabria and Sapatnekar).
Mechanism, BTI in a high-k stack: Holes from the channel are captured by defects in the gate oxide in a pFET (NBTI), and electrons by traps in the high-k layer in an nFET (PBTI), whose levels can be moved away from the channel carriers by Dy in the high-k or by a SiGe or Ge channel (Kaczer et al. 2018). Each captured charge shifts the threshold by a random step with an exponential distribution and a mean $η$ that grows as the device shrinks (Kaczer et al. 2010).
Mechanism, hot carriers in short channels: Si-H bonds at the interface break either by one hot carrier (single-carrier process) or by several colder carriers that climb the vibrational ladder of the bond (multiple vibrational excitation, MVE); electron-electron scattering fills the high-energy tail in channels below about 100 $nm$ (Tyaginov et al.).
Mechanism, breakdown of the high-k stack: Traps generated in the stack link up into a percolation path; in thin HfO2 stacks the high-k layer dominates the breakdown, which runs from soft through progressive to hard breakdown (Tao et al.; O’Connor et al.).
Mechanism, self-heating: The fin and the nanosheet conduct heat about 10 and 25 times worse than bulk silicon and are wrapped in oxide, so the channel runs hotter than the substrate, most at the drain edge (Chhabria and Sapatnekar; Hsieh et al. 2018).
What sets the rate: The gate overdrive and the oxide field through the voltage exponent, the temperature including the self-heating rise, the energy offset between the channel carriers and the defect band (Kaczer et al. 2018), the stress current and drain voltage for hot carriers (Bury et al.; Zhang et al.), and the gate area through the number of defects and the Weibull slope (Kaczer et al. 2010; O’Connor et al.).
Failure criterion: A tolerated threshold shift, 50 $mV$ at 125 $^{\circ} C$ in one nanosheet projection (Bury et al.); a drop of 10 per cent of the peak transconductance or of the saturation current for hot carriers (Zhang et al.; Bury et al.); breakdown at a soft-breakdown current, 10 $μ A$ in one study (O’Connor et al.); or a slower circuit, seen as a ring-oscillator frequency drift (Lu and Jenkins).

2. Where to Look

Location: The interfacial layer and the high-k next to the channel for BTI and breakdown (Kaczer et al. 2018; Tao et al.); the drain end of the channel for hot carriers and for the self-heating peak (Hsieh et al. 2018); the channel corners of a nanosheet, where the field crowds (Lim et al. 2023); the pull-down network of a stacked cell, which runs hottest (Chhabria and Sapatnekar).
Signature: Discrete threshold steps and a wide device-to-device spread in small devices, against a smooth log-like recovery in large ones (Kaczer et al. 2018); a power-law drift with an exponent near 0.16 for BTI (Deora et al.; Lu and Jenkins); a degradation that is stronger in linear than in saturation current and a falling transconductance for hot carriers (Bury et al.); a stress-induced leakage current that rises before breakdown (O’Connor et al.).
Confirm with: Measure-stress-measure sequences with a delay of a microsecond or less, since relaxation starts within 1 $μ s$ (Kaczer et al. 2018); maps of the degradation over the gate and drain bias plane for hot carriers (Bury et al.); random telegraph noise of single traps as a local thermometer for self-heating (Hsieh et al. 2018); constant-voltage breakdown tests on many devices with Weibull statistics (O’Connor et al.).
Look-alikes: Self-heating lowers the drive current by about 10 per cent (n) and 14 per cent (p) during a DC measurement and recovers at once, so it can be mistaken for degradation (Hsieh et al. 2018). A high series contact resistance on one sheet looks like extra hot-carrier damage until the width is corrected (Bury et al.). Random telegraph noise looks like BTI steps but switches both ways without stress (Stampfer).

3. Prevention

Design: Keep the overdrive low, since the life depends on the voltage to a high power (see the lifetime row), and guardband the timing for the threshold drift and its spread in small devices (Kaczer et al. 2010). Place contacts to cut the self-heating of stacked cells: a third contact lowered the rise of one cell from 18.1 to 13.8 $K$ (Chhabria and Sapatnekar). Optimise the nanosheet corner rounding for the breakdown field (Lim et al. 2023).
Material and process: Move the defect levels away from the carriers: rare earths such as Dy in the high-k for PBTI, a SiGe or Ge channel with a thin Si cap for NBTI (Kaczer et al. 2018; Deora et al.); keep the deuterium or hydrogen passivation of the interface and the interface trap density low for hot carriers (Tyaginov et al.).
Operation: Lower the supply in standby and keep the junction cool, since every few kelvins of self-heating add to the rate (Chhabria and Sapatnekar); dynamic operation lets BTI recover in part, so the DC projection is pessimistic (Sangani et al.).
Screening and test: Measure BTI with ultra-fast or extended measure-stress-measure sequences (Kaczer et al. 2018; Bury et al.), stress hot carriers over a bias map and in the MVE regime that matches the low supply (Bury et al.), and monitor the field drift with built-in ring oscillators against a reference ring (Lu and Jenkins).

Single Defects and Variability

Name	Formula	Related Formulae	Variables/Constants
Threshold step of a single trapped charge (defect-centric model)	$f_{1} (Δ V_{t h}) = \frac{1}{η} e^{- Δ V_{t h} / η}$	$η_{s h ee t} = \frac{q}{C _{o x} A _{G}}, C_{o x} = \frac{ε _{0} 3.9}{E O T}$	$f_{1} : p r o babi l i t y d e n s i t y o f t h e t h r es h o l d s hi f t c a u se d b y o n e t r a pp e d c ha r g e$ $Δ V_{t h} : t h r es h o l d s hi f t$ $η : m e an s hi f t p er c ha r g e, w hi c h g r o w s a s t h e d e v i ce s h r ink s$ $η_{s h ee t} : c ha r g e - s h ee t es t ima t e o f η$ $q : e l e m e n t a r y c ha r g e 1.602 \times 1 0^{- 19} C$ $C_{o x} : g a t e c a p a c i t an ce p er u ni t a r e a$ $A_{G} : g a t e a r e a W L f or a pl ana r d e v i ce (t h e m u l t i g a t e a r e a i s in t h e n e x t r o w)$ $ε_{0} : v a c uu m p er mi tt i v i t y 8.854 \times 1 0^{- 12} F/m$ $E O T : e q u i v a l e n t o x i d e t hi c k n ess, w i t h C_{o x} = 3.9 ε_{0} / E O T a s in t h e B S I M - C M G man u a l (sec t i o n 3.7.3); K a cz er e t a l . (2010) : e x p o n e n t ia l s t e p s, W e ib u l l w i t h s l o p e 1, m e a s u r e d η = 4.75 mV w i t h so m e s t e p s ab o v e 30 mV f or L = 35 nm, W = 90 nm an d E O T = 0.8 nm, an d t h e c ha r g e - s h ee t es t ima t e i s b e l o w 2 mV an d t oo s ma l l; S t am p f er : ab o u t 63 p er ce n t o f t h e d e f ec t s g i v e s t e p s b e l o w η$ $(co m p u t e d f or t h e K a cz er d e v i ce : C_{o x} = 0.0432 F/ m^{2}, η_{s h ee t} = 1.18 mV, so t h e m e a s u r e d m e an i s 4.0 t im es t h e c ha r g e - s h ee t v a l u e; m y r e a d in g i s t ha t t h e c u r r e n t f l o w s t h r o ug h a p er co l a t i o n p a t h, w hi c h a c ha r g e ab o v e i t b l oc k s m or e s t r o n g l y)$
Number of charges and the spread of the shift	$⟨ Δ V_{t h} ⟩ = N η, σ_{Δ V_{t h}}^{2} = 2 N η^{2} = 2 η ⟨ Δ V_{t h} ⟩$	$P_{N} (n) = \frac{N ^{n} e ^{- N}}{n !}, N = W L N_{o t}$ $f_{N} (Δ V_{t h}) = \sum_{n = 1}^{\infty} P_{N} (n) \frac{Δ V _{t h}^{n - 1} e ^{- Δ V_{t h} / η}}{( n - 1 )! η ^{n}}$	$⟨ Δ V_{t h} ⟩ : m e an s hi f t o v er man y d e v i ces$ $N : m e an n u mb er o f t r a pp e d c ha r g es p er d e v i ce$ $σ : s t an d a r d d e v ia t i o n o f t h e s hi f t, P_{N} (n) : P o i sso n p r o babi l i t y o f n c ha r g es$ $N_{o t} : a r e a l d e n s i t y o f c ha r g e d d e f ec t s$ $f_{N} : d i s t r ib u t i o n o f t h e s hi f t (g amma t er m s w e i g h t e d b y t h e P o i sso n n u mb er s, S t am p f er), K a cz er e t a l . (2010) : N r ose f r o m 2.6 t o 6.9 d u r in g s t r ess an d f e l l t o 3.4 a f t er 10 s o f r eco v er y, w hi c h t h ey g i v e a s ab o u t 1 \times 1 0^{11} t o 2 \times 1 0^{11} c m^{- 2}, an d t h e m o m e n t s g a v e η o f 7 t o 9 mV a g ain s t 4.75 mV f r o m t h e s t e p hi s t o g r am s$ $(co m p u t e d f or η = 4.75 mV : N = 2.6, 6.9 an d 3.4 g i v e m e an s o f 12.4, 32.8 an d 16.2 mV an d σ o f 10.8, 17.6 an d 12.4 mV; N_{o t} = 8.3 \times 1 0^{10}, 2.19 \times 1 0^{11} an d 1.08 \times 1 0^{11} c m^{- 2} f or W L = 3.15 \times 1 0^{- 11} c m^{2})$
Gate area of a multigate device and its step size	$A_{G, f in} = N_{f in} (2 H_{f in} + W_{f in}) L_{G}$	$A_{G, N S} = N_{s h} \cdot 2 (W_{s h} + T_{s h}) L_{G}$ $η_{s h ee t} = \frac{q}{C _{o x} A _{G}}$	$A_{G, f in} : g a t e a r e a o f a F in F E T$ $N_{f in} : n u mb er o f f in s$ $H_{f in} an d W_{f in} : f in h e i g h t an d w i d t h$ $L_{G} : g a t e l e n g t h$ $A_{G, N S} : g a t e a r e a o f a nan os h ee t d e v i ce$ $N_{s h} : n u mb er o f s h ee t s$ $W_{s h} an d T_{s h} : s h ee t w i d t h an d t hi c k n ess (t h e g a t e s u r r o u n d s e a c h s h ee t), t h e f or m s a r e t h e g a t e d p er im e t er s o f t h e F in F E T an d G AA F E T p a g es o f t hi s v a u l t t im es L_{G} an d i g n or e cor n er r o u n d in g; K a cz er e t a l . (2018) : r e l a x a t i o n s h o w s d i scr e t e s t e p s in d e v i ces b e l o w ab o u t 1 \times 1 0^{4} n m^{2} an d i s s m oo t h an d l o g - l ik e in l a r g e o n es$ $(co m p u t e d w i t h a ss u m e d d im e n s i o n s : 2 f in s o f 42 b y 8 nm w i t h L_{G} = 20 nm g i v e 3680 n m^{2} an d η_{s h ee t} = 1.13 mV f or E O T = 0.9 nm, ab o u t 4.5 mV i f t h e f a c t or o f 4.0 o f t h e f i r s t r o w h o l d s; 3 s h ee t s o f 30 b y 5 nm w i t h L_{G} = 14 nm g i v e 2940 n m^{2} an d 1.42 mV; b o t h a r e b e l o w 1 \times 1 0^{4} n m^{2}, so s in g l e c ha r g es a r e v i s ib l e)$

Bias Temperature Instability in High-k Stacks

Name	Formula	Related Formulae	Variables/Constants
Lifetime and operating voltage from a power-law BTI shift	$t_{f} = t_{1} (\frac{Δ V _{cr i t}}{Δ V _{1}})^{1/ n}$	$\frac{t _{f} ( V _{1} )}{t _{f} ( V _{2} )} = (\frac{V _{2}}{V _{1}})^{Γ/ n}$ $Δ V_{t h} = B V_{G}^{Γ} e^{- E_{a} / (k_{B} T)} t^{n}$	$t_{f} : t im e t o r e a c h t h e t o l er a t e d s hi f t$ $t_{1} : s t r ess t im e a t w hi c h t h e s hi f t Δ V_{1} w a s m e a s u r e d$ $Δ V_{cr i t} : t o l er a t e d s hi f t$ $n : t im e e x p o n e n t$ $V_{1}, V_{2} : g a t e s t r ess v o l t a g es$ $Γ : v o l t a g e e x p o n e n t$ $B : co n s t an t$ $E_{a} : a c t i v a t i o n e n er g y$ $k_{B} : B o l t z mann co n s t an t 8.617 \times 1 0^{- 5} eV/K$ $T : ab so l u t e t e m p er a t u r e (t h e l a s t f or m i s t h e p o w er l a w o f t h e E l ec t r i c a l S t r ess p a g e); B u r y e t a l . : 50 mV a t 125^{\circ} C i s t h e t o l er a t e d s hi f t o f t h e i r nan os h ee t l i f e t im e p r o j ec t i o n, w i t h V_{D D} = 0.75 V; D eor a e t a l . : n = 0.155 t o 0.16 f or S i an d S i G e pF E T s, in d e p e n d e n t o f t h e s t r ess v o l t a g e; Lu an d J e nk in s : n = 0.174 f i tt e d t o f i e l d d a t a a g ain s t 0.16 p r e d i c t e d$ $(co m p u t e d : a s hi f t o f 20 mV a f t er 1000 s r e a c h es 50 mV a f t er 3.1 \times 1 0^{5} s (3.6 d a y s) f or n = 0.16, 9.8 \times 1 0^{4} s f or 0.20 an d 3.9 \times 1 0^{4} s f or 0.25; l o w er in g t h e s t r ess f r o m 1.2 t o 0.9 V l e n g t h e n s t h e l i f e b y 220 f or an a ss u m e d Γ = 3 an d 1330 f or Γ = 4 w i t h n = 0.16, so t h e p r o j ec t i o n d e p e n d s s t r o n g l y o n n an d Γ)$
Emission time of an oxide defect (energy alignment with the channel carriers)	$τ_{e} = τ_{e 0} e^{E_{A} / (k_{B} T)}$	$\frac{τ _{e} ( T _{1} )}{τ _{e} ( T _{2} )} = exp [\frac{E _{A}}{k _{B}} (\frac{1}{T _{1}} - \frac{1}{T _{2}})]$	$τ_{e} : e mi ss i o n (r eco v er y) t im e o f a d e f ec t$ $τ_{e 0} : p r e f a c t or$ $E_{A} : a c t i v a t i o n e n er g y o f t h e e mi ss i o n$ $k_{B} : B o l t z mann co n s t an t 8.617 \times 1 0^{- 5} eV/K$ $T, T_{1}, T_{2} : ab so l u t e t e m p er a t u r es$ $K a cz er e t a l . (2018) : P B T I f a l l s w h e n D y p a ss i v a t es hi g h - k t r a p s b y m o v in g t h e i r l e v e l s t o w a r d t h e o x i d e co n d u c t i o n ban d, N B T I f a l l s w i t h a S i - c a pp e d G e or a t hi c k er S i G e w e l l an d, u n e x p ec t e d l y, w i t h a t hinn er S i c a p (1.4 t o 0.65 nm), a m o d e l l e d s hi f t o f 0.5 eV o f t h e m e an d e f ec t l e v e l a w a y f r o m t h e c hann e l c a r r i er s g i v es an e x p o n e n t ia l r e d u c t i o n o f t r a pp in g, an d t h e e mi ss i o n t im e in a 28 nm hi g h - k t ec hn o l o g y ha s E_{A} = 1.2 eV$ $(co m p u t e d : w i t h E_{A} = 1.2 eV an e mi ss i o n t im e i s 1.2 \times 1 0^{5} t im es s h or t er a t 125^{\circ} C t han a t 25^{\circ} C, so r eco v er y d u r in g a d e l a y e d m e a s u r e m e n t i s m u c h f a s t er w h e n t h e p a r t i s h o t)$

Hot-Carrier Degradation in Short Channels

Name	Formula	Related Formulae	Variables/Constants
Bond-breaking rate of hot carriers (acceleration integral)	$I_{x} = \int f (E) g (E) v (E) σ_{x} (E) d E$	$σ_{A B} (E) = σ_{A B, 0} (E - E_{a} + E_{i} + d F_{o x})^{p_{A B}}$ $σ_{M V E} (E) = σ_{M V E, 0} (E - ℏ ω)^{p_{M V E}}$	$I_{x} : r a t e a t w hi c h c a r r i er s in t er a c t w i t h a S i - H b o n d b y t h e p r ocess x$ $f g : c a r r i er d i s t r ib u t i o n t im es d e n s i t y o f s t a t es$ $v : c a r r i er v e l oc i t y$ $σ_{x} : r e a c t i o n cr oss sec t i o n$ $E : c a r r i er e n er g y$ $σ_{A B} : cr oss sec t i o n o f t h e s in g l e - c a r r i er p r ocess t ha t e x c i t es a b o n d in g e l ec t r o n t o an an t ib o n d in g s t a t e$ $E_{a} : b o n d - b r e ak in g e n er g y$ $E_{i} : e n er g y o f t h e v ib r a t i o na l l e v e l a l r e a d y r e a c h e d$ $d F_{o x} : l o w er in g o f t h e ba r r i er b y t h e d i p o l e m o m e n t d in t h e o x i d e f i e l d F_{o x}$ $σ_{M V E} : cr oss sec t i o n o f m u l t i pl e v ib r a t i o na l e x c i t a t i o n b y se v er a l co l d er c a r r i er s$ $ℏ ω : s p a c in g o f t h e v ib r a t i o na l l e v e l s$ $p : e x p o n e n t s; T y a g in o v e t a l . : b e n d in g m o d e ℏ ω = 0.075 eV w i t h E_{a} = 1.5 eV (e a r l i er m o d e l) an d s t r e t c hin g m o d e 0.25 eV w i t h 2.5 eV (n e w), σ_{M V E, 0} = 5 \times 1 0^{- 19} an d σ_{A B, 0} = 5 \times 1 0^{- 18} in t h e u ni t s p r in t e d (c m^{- 2} in t h e s u mma r y, w hi c h i s p r es u mab l y c m^{2}), an d e l ec t r o n - e l ec t r o n sc a tt er in g f i l l s t h e hi g h - e n er g y t ai l in c hann e l s s h or t er t han ab o u t 100 nm$ $(n o n e w n u mb er s; t h e p r e - e x c i t a t i o n o f t h e b o n d b y M V E l o w er s t h e e n er g y t ha t a s in g l e h o t c a r r i er n ee d s, w hi c h i s w h y t h e tw o p r ocesses a c t t o g e t h er)$
Vibrational ladder of the Si-H bond	$P_{u} = \frac{1}{τ _{e}} e^{- ℏ ω / (k_{B} T)} + I_{M V E}, P_{d} = \frac{1}{τ _{e}} + I_{M V E}$	$\frac{n _{i + 1}}{n _{i}} \approx \frac{P _{u}}{P _{d}}$	$P_{u}, P_{d} : r a t es o f e x c i t a t i o n an d d e - e x c i t a t i o n b e tw ee n n e i g hb o u r in g v ib r a t i o na l l e v e l s$ $τ_{e} : v ib r a t i o na l l i f e t im e o f t h e b o n d$ $ℏ ω : l e v e l s p a c in g$ $k_{B} : B o l t z mann co n s t an t 8.617 \times 1 0^{- 5} eV/K$ $T : ab so l u t e t e m p er a t u r e$ $I_{M V E} : M V E a cce l er a t i o n in t e g r a l o f t h e p r e v i o u s r o w$ $n_{i} : occ u p a t i o n o f l e v e l i (t h e r a t i o f or m f o l l o w s f r o m t h e tw o r a t es b y d e t ai l e d ba l an ce b e tw ee n n e i g hb o u r in g l e v e l s, d er i v e d); T y a g in o v e t a l . : τ_{e} = 1.5 ns a t 25^{\circ} C an d 1.3 ns a t 75^{\circ} C, an d u s in g 1.5 ns a t 75^{\circ} C o v er es t ima t es t h e d e g r a d a t i o n$ $(co m p u t e d : f or t h e b e n d in g m o d e e^{- 0.075/ (k_{B} T)} i s 0.054 a t 25^{\circ} C an d 0.082 a t 75^{\circ} C, so h e a t in g h e l p s t h e l a dd er w hi l e i t s h or t e n s τ_{e})$
Empirical hot-carrier power law and lifetime against drain voltage	$D (t) = α t^{n} e^{β / V_{D S}}$	$τ = A e^{B / V_{D S}}, B = - \frac{β}{n}$	$D : d e g r a d a t i o n o f a p a r am e t er s u c h a s t h e p e ak t r an sco n d u c t an ce, t h e s a t u r a t i o n c u r r e n t or t h e t h r es h o l d, in p er ce n t$ $α : p os i t i v e co n s t an t$ $t : s t r ess t im e$ $n : t im e e x p o n e n t$ $β : n e g a t i v e co n s t an t$ $V_{D S} : d r ain s t r ess v o l t a g e$ $τ : l i f e t im e t o a c h ose n d e g r a d a t i o n$ $A, B : co n s t an t s; Z han g e t a l . : n o f ab o u t 0.5 t o 1 f or in t er f a ce - t r a p d ama g e an d 0.1 t o 0.3 f or c ha r g e inj ec t i o n in t o t h e o x i d e, f i tt e d v a l u es 0.19 t o 0.78, t h e cr i t er i o n i s 10 p er ce n t o f t h e p e ak t r an sco n d u c t an ce, an d t h e f or m m u s t b e u se d w i t h c a r e ab o v e 300 K b ec a u se n c han g es b e f or e 10 p er ce n t; B u r y e t a l . ana l y se nan os h ee t s in t h e M V E r e g im e b y pl o tt in g t h e t im e t o 10 p er ce n t d r o p o f I_{D S A T} t im es t h e s t r ess c u r r e n t a g ain s t t h e s t r ess c u r r e n t$ $(co m p u t e d : f or n = 0.5 a d e g r a d a t i o n o f 1 p er ce n t a t 1 h b eco m es 10 p er ce n t a t 100 h; f or n = 0.2 i t n ee d s 1 \times 1 0^{5} h, so t h e r e g im e t ha t se t s n d ec i d es t h e p r o j ec t i o n)$

Breakdown of High-k and Multigate Stacks

Name	Formula	Related Formulae	Variables/Constants
Percolation and the Weibull slope of a thin high-k stack	$β = m n_{b d}$	$F (t) = 1 - e^{- (t / t_{63})^{β}}$ $\frac{t _{63} ( E _{1} )}{t _{63} ( E _{2} )} = e^{γ (E_{2} - E_{1})}$	$β : W e ib u l l s l o p e o f t h e b r e ak d o w n t im es$ $m : l o g a r i t hmi c t r a p g e n er a t i o n r a t e (e x p o n e n t o f t h e l e ak a g e in cr e a se a g ain s t t im e)$ $n_{b d} : n u mb er o f t r a p s in t h e cr i t i c a l p er co l a t i o n p a t h$ $F : c u m u l a t i v e f r a c t i o n f ai l e d$ $t : s t r ess t im e$ $t_{63} : t im e a t w hi c h 63 p er ce n t ha v e f ai l e d$ $E_{1}, E_{2} : o x i d e f i e l d s$ $γ : f i e l d a cce l er a t i o n o f t h e E m o d e l; O^{'} C o nn or e t a l . : β = 1.54 (S i) an d 1.82 (S i G e s u b s t r a t e) f or 7.8 an d 8.1 an g s t r o m E O T H f O 2, a g ain s t ab o u t 0.8 t o 1 co mm o n l y r e p or t e d, n o S i O 2 - l ik e in t er f a c ia l l a y er w a s see n, an d 10 y e a r v o l t a g es o f 1.24 an d 1.3 V; T a o e t a l . : β = 0.87, m = 0.4 t o 0.5, γ = 1.59, p r in t e d a s s c m / M V in t h e ab s t r a c t an d r e a d h er e a s c m / M V w i t h t h e na t u r a l l o g a r i t hm, a s in t h e E m o d e l o f t h e E l ec t r i c a l S t r ess p a g e, 1.06 V ma x im u m f or 10 y e a r s a t 125^{\circ} C w i t h E O T 0.91 nm, an d t h e hi g h - k l a y er d o mina t es t h e b r e ak d o w n$ $(co m p u t e d : t h r ee t r a p s an d β = 1.82 or 1.54 g i v e m = 0.61 or 0.51; T a o^{'} s β = 0.87 w i t h m = 0.4 t o 0.5 im pl i es ab o u t 1.7 t o 2.2 t r a p s; 0.1 V a cr oss 0.91 nm i s 1.1 MV/cm an d c han g es t_{63} b y 5.7 w i t h γ = 1.59, or b y 56 i f γ w er e in d ec a d es p er MV/cm; 1.06 V o v er 0.91 nm i s 11.6 MV/cm b e f or e t h e f l a t - ban d an d s u r f a ce - p o t e n t ia l cor r ec t i o n s)$
Breakdown life of a multigate stack with self-heating and corners	$\frac{t _{63} ( A _{1} )}{t _{63} ( A _{2} )} = (\frac{A _{2}}{A _{1}})^{1/ β}$	$t_{63} (T_{0} + Δ T) = t_{63} (T_{0}) e^{\frac{E _{a}}{k _{B}} (\frac{1}{T _{0} + Δ T} - \frac{1}{T _{0}})}$	$A_{1}, A_{2} : g a t e a r e a s (t h e m u l t i g a t e a r e a o f t h e d e f ec t sec t i o n)$ $β : W e ib u l l s l o p e$ $T_{0} : ambi e n t or c h u c k t e m p er a t u r e$ $Δ T : se l f - h e a t in g r i se o f t h e c hann e l$ $E_{a} : a c t i v a t i o n e n er g y o f t h e b r e ak d o w n$ $k_{B} : B o l t z mann co n s t an t 8.617 \times 1 0^{- 5} eV/K (b o t h f or m s a r e s t an d a r d, see t h e E l ec t r i c a l S t r ess p a g e); I E E E A ccess (2023, ab s t r a c t) : in s t a c k e d nan os h ee t s a t t h e 3 nm n o d e s t a t i c D C se l f - h e a t in g c an c u t t h e T D D B l i f e b y m or e t han 90 p er ce n t, d y nami c l o g i c o p er a t i o n b y 42.7 t o 51.4 p er ce n t, an d c hann e l cor n er r o u n d in g a c t s t h r o ug h f i e l d cr o w d in g an d t h e e f f ec t i v e w i d t h$ $(co m p u t e d : a c u t o f 90 p er ce n t i s a f a c t or o f 10, an d 42.7 t o 51.4 p er ce n t a r e f a c t or s o f 1.75 t o 2.06; f or an a ss u m e d β = 1.5 a d e v i ce w i t h 10 t im es t h e a r e a ha s a t_{63} 4.6 t im es s h or t er)$

Self-Heating in FinFET and GAA

Name	Formula	Related Formulae	Variables/Constants
Channel temperature from self-heating	$Δ T = R_{t h} P, P = I_{D} V_{D S}$	$C \frac{\partial T}{\partial t} = K \nabla^{2} T + P_{V}$ $G T = P$	$Δ T : r i se o f t h e c hann e l t e m p er a t u r e ab o v e t h e s u b s t r a t e or ambi e n t$ $R_{t h} : t h er ma l r es i s t an ce o f t h e d e v i ce$ $P : d i ss i p a t e d p o w er$ $I_{D} : d r ain c u r r e n t$ $V_{D S} : d r ain v o l t a g e$ $C : v o l u m e t r i c h e a t c a p a c i t y$ $K : t h er ma l co n d u c t i v i t y$ $P_{V} : h e a t g e n er a t e d p er u ni t v o l u m e$ $G : t h er ma l co n d u c t an ce ma t r i x o f a f ini t e - d i f f er e n ce g r i d$ $T, P : n o d e t e m p er a t u r es an d p o w er s (C hhab r ia an d S a p a t n e k a r); co n d u c t i v i t i es in t h e i r m o d e l : S i f in 13, S i nan o w i r e 5, S i s u b s t r a t e 148, b u r i e d o x i d e 0.8, H f O 2 0.27, m e t a l g a t e 48 an d C u 42.4 W/ (m K), i . e . ab o u t 10 an d 25 t im es b e l o w b u l k; t h e H s i e h e t a l . (2018) ab s t r a c t : t h e h o tt es t p o in t i s t h e d r ain e d g e, R_{t h} r i ses s ha r pl y a s L s h r ink s t o 20 nm, pF in F E T s r u n h o tt er, an d t h e d r i v e c u r r e n t f a l l s b y ab o u t 10 p er ce n t (n) an d 14 p er ce n t (p) t h r o ug h se l f - h e a t in g$ $(co m p u t e d : 148/13 = 11.4 an d 148/5 = 29.6, a g ain s t ab o u t 10 an d 25 in t h e t e x t; t h e a v er a g e g a t e t e m p er a t u r e r i ses o f t h e s t u d y a r e ab o u t 5 K f or b u l k F in F E T, 12 K f or S O I F in F E T an d 18 K f or G AA F E T, an d t h e ab s t r a c t s a y s 17 K)$
Acceleration of ageing by the self-heating rise	$A F_{S H} = exp [\frac{E _{a}}{k _{B}} (\frac{1}{T _{0}} - \frac{1}{T _{0} + Δ T})]$	$Δ V_{t h} (T_{0} + Δ T) = Δ V_{t h} (T_{0}) A F_{S H}$	$A F_{S H} : f a c t or b y w hi c h a t h er ma l l y a c t i v a t e d d e g r a d a t i o n r a t e r i ses$ $E_{a} : a c t i v a t i o n e n er g y$ $k_{B} : B o l t z mann co n s t an t 8.617 \times 1 0^{- 5} eV/K$ $T_{0} : t e m p er a t u r e w i t h o u t se l f - h e a t in g$ $Δ T : se l f - h e a t in g r i se o f t h e p r e v i o u s r o w$ $(t h e seco n d f or m h o l d s w h e n t h e a c t i v a t i o n e n er g y s i t s o n t h e p r e f a c t or o f t h e s hi f t, a s in t h e B T I r o w o f t hi s p a g e, so t h e t im e e x p o n e n t d oes n o t e n t er); C hhab r ia an d S a p a t n e k a r w r i t e t h e s hi f t w i t h an A r r h e ni u s f a c t or in T_{S H} an d f in d t ha t se l f - h e a t in g a cce l er a t es B T I an d H C I d e l a y d e g r a d a t i o n b y u p t o 25 p er ce n t (F in F E T) an d 39 p er ce n t (G AA F E T), an d E M l i f e f a l l s b y u p t o 38 p er ce n t (S O I F in F E T) an d 45 p er ce n t (G AA F E T); in a N A N D 4 ce l l t h e p u l l - d o w n n e tw or k r i ses b y 31.4 K w i t h t h e co n t a c t n e x t t o I 1 an d 23.3 K n e x t t o I 4, an d t h e p u l l - u p n e tw or k b y 18.1 K w i t h 2 co n t a c t s an d 13.8 K w i t h 3$ $(co m p u t e d f or T_{0} = 85^{\circ} C : w i t h an a ss u m e d E_{a} = 0.5 eV, r i ses o f 5, 12 an d 18 K g i v e A F_{S H} = 1.25, 1.69 an d 2.17, an d w i t h E_{a} = 0.1 eV 1.05, 1.11 an d 1.17; t h e t hi r d co n t a c t l o w er s t h e r i se b y 24 p er ce n t, t h e co n t a c t p os i t i o n t h e p u l l - d o w n r i se b y 26 p er ce n t)$

Circuit-Level Drift

Name	Formula	Related Formulae	Variables/Constants
Frequency drift of a logic path from the threshold shift	$\frac{Δ f}{f} \approx - \frac{α Δ V _{t h}}{V _{D D} - V _{t h}}$	$t_{d} \propto \frac{C _{L} V _{D D}}{( V _{D D} - V _{t h} ) ^{α}}$ $\frac{Δ f}{f _{0}} = B t^{n}$	$Δ f / f : r e l a t i v e c han g e o f t h e osc i l l a t i o n or c l oc k f r e q u e n cy$ $α : v e l oc i t y - s a t u r a t i o n in d e x o f t h e a l p ha - p o w er l a w (1 t o 2)$ $Δ V_{t h} : m e an t h r es h o l d s hi f t o f t h e s w i t c hin g t r an s i s t or s$ $V_{D D} : s u ppl y v o l t a g e$ $V_{t h} : t h r es h o l d v o l t a g e$ $t_{d} : g a t e d e l a y$ $C_{L} : l o a d c a p a c i t an ce (t h e d e l a y f or m f o l l o w s f r o m t h e a l p ha - p o w er l a w o f S ak u r ai an d N e w t o n (1990), w h ose d e l a y i s p r o p or t i o na l t o C_{L} V_{D D} / I_{D 0} w i t h I_{D 0} \propto (V_{D D} - V_{t h})^{α}, an d t h e f i r s t f or m i s i t s d er i v a t i v e)$ $B, n : f i t co n s t an t s o f t h e p o w er l a w in t im e; Lu an d J e nk in s : ab o u t 1 p er ce n t f r e q u e n cy c han g e p er 10 mV o f s u ppl y, a f e w p er ce n t o v er 5 t o 10 y e a r s e x p ec t e d a t n o mina l co n d i t i o n s, n = 0.174 in t h e f i e l d, an d a hi g h - t h r es h o l d r in g d e g r a d es m or e t han a s t an d a r d o n e b ec a u se o f i t s l o w er o v er d r i v e; S an g ani e t a l . : in a 28 nm r in g t h e s t a t i c s t r ess i s B T I d o mina t e d an d ab o v e ab o u t 1.8 V d y nami c s t r ess a dd s H C I, an d a m o d e l w i t h o u t r eco v er y o v er es t ima t es t h e d r i f t$ $(co m p u t e d w i t h a ss u m e d α = 1.3, V_{D D} = 0.75 V an d V_{t h} = 0.30 V : 10, 30 an d 50 mV g i v e 2.9, 8.7 an d 14.4 p er ce n t, an d 3.7, 11.1 an d 18.6 p er ce n t f or V_{t h} = 0.40 V; w i t h n = 0.174 a d r i f t o f 2 p er ce n t a t 500 d a y s b eco m es 2.8 p er ce n t a t 10 y e a r s)$

Important Questions

Ques: How large is the threshold step of one trapped charge in a small device: 1, 5 or 9 millivolts?

The three numbers come from different estimates. For pFETs of 35 by 90 $nm$ and EOT 0.8 $nm$ , the charge-sheet formula $q / (C_{o x} W L)$ gives 1.18 $mV$ (computed), and Kaczer et al. say it is below 2 $mV$ and too small. The step histograms gave $η = 4.75$ $mV$ , with single steps above 30 $mV$ . The moments of the distribution, $⟨ Δ V_{t h} ⟩ = N η$ and $σ^{2} = 2 N η^{2}$ , gave 7 to 9 $mV$ . The histogram value is more likely, since it counts the steps directly, while the moments also take up device-to-device variation that is not from the trapped charges (my reading). The factor of about 4 over the charge sheet comes from the current flowing through percolation paths, which one charge can block. Reference: B. Kaczer, Ph. J. Roussel, T. Grasser and G. Groeseneken, ‘Statistics of Multiple Trapped Charges in the Gate Oxide of Deeply Scaled MOSFET Devices - Application to NBTI’, IEEE Electron Device Letters 31(5), 411-413 (2010) (author copy at TU Wien, fetch-tool summary); B. Stampfer, ‘Advanced Electrical Characterization of Charge Trapping in MOS Transistors’, PhD thesis, TU Wien, section 3.3 ‘The Defect Centric Model’ (year not stated) (fetch-tool summary).

Ques: Does a SiGe channel reduce NBTI by 40 per cent or by a factor of four?

The same paper gives both. Deora et al. write a reduction of about 40 per cent of the NBTI degradation in the abstract, while the body says that the threshold shift is about 4 times lower in SiGe than in Si after 1000 $s$ at 125 $^{\circ} C$ (their Fig. 2b), with the same time exponent of 0.155 to 0.16 and the same field acceleration, so the mechanism is unchanged. A factor of four means a 75 per cent reduction. The body value is more likely to describe their devices, since it is the measured figure; the abstract may compare a different condition (my reading). The reason they give is a higher hole barrier, by 0.156 $eV$ , which lowers the hole tunnelling to the oxide traps. Kaczer et al. (2018) explain the same gain by the misalignment of the channel holes and the defect band. Reference: S. Deora, A. Paul, R. Bijesh, J. Huang, G. Klimeck, G. Bersuker, P. D. Kirsch and R. Jammy, ‘Intrinsic Reliability Improvement in Biaxially Strained SiGe p-MOSFETs’, IEEE Electron Device Letters 32(3) (2011), arXiv:1012.1579 (fetch-tool summary); B. Kaczer, J. Franco, P. Weckx, Ph. J. Roussel, V. Putcha, E. Bury, M. Simicic, A. Chasin, D. Linten, B. Parvais, F. Catthoor, G. Rzepa, M. Waltl and T. Grasser, ‘A brief overview of gate oxide defect properties and their relation to MOSFET instabilities and device and circuit time-dependent variability’, Microelectronics Reliability 81, 186-194 (2018) (author copy at TU Wien, fetch-tool summary).

Ques: Why does the threshold spread grow faster than the mean shift as transistors shrink?

In the defect-centric model the mean shift is $N η$ and the variance is $2 N η^{2}$ , so the relative spread is $2/ N$ . A small device holds few defects, so N is small and the spread is large: with $η = 4.75$ $mV$ and N = 6.9 the mean is 32.8 $mV$ and the standard deviation 17.6 $mV$ , more than half the mean (computed). Since $η$ grows as the gate area falls, a nanosheet of 2940 $n m^{2}$ has a charge-sheet step of 1.42 $mV$ against 1.18 $mV$ for the planar device (computed), and both are below the area of about $1 \times 1 0^{4}$ $n m^{2}$ where single steps appear. The worst device of a large array then sets the guardband, not the mean, which is why the distribution, not one number, must be projected. Reference: B. Kaczer, Ph. J. Roussel, T. Grasser and G. Groeseneken, ‘Statistics of Multiple Trapped Charges in the Gate Oxide of Deeply Scaled MOSFET Devices - Application to NBTI’, IEEE Electron Device Letters 31(5), 411-413 (2010) (author copy at TU Wien, fetch-tool summary); B. Kaczer, J. Franco, P. Weckx, Ph. J. Roussel, V. Putcha, E. Bury, M. Simicic, A. Chasin, D. Linten, B. Parvais, F. Catthoor, G. Rzepa, M. Waltl and T. Grasser, ‘A brief overview of gate oxide defect properties and their relation to MOSFET instabilities and device and circuit time-dependent variability’, Microelectronics Reliability 81, 186-194 (2018) (author copy at TU Wien, fetch-tool summary); B. Stampfer, ‘Advanced Electrical Characterization of Charge Trapping in MOS Transistors’, PhD thesis, TU Wien, section 3.3 ‘The Defect Centric Model’ (year not stated) (fetch-tool summary).

Ques: At which bias is hot-carrier damage worst, at maximum substrate current or at equal gate and drain voltage?

It depends on the channel length and the supply. Zhang et al. find the nMOS worst case at maximum substrate current, $V_{G} \approx V_{D} /2$ , with stress at 2.4 to 3.0 $V$ on a 1.8 $V$ process, and the pMOS worst case at $V_{G} = V_{D}$ . Tyaginov et al. stress 44 $nm$ nMOSFETs at $V_{G} = V_{D}$ , and Bury et al. use $V_{G} = V_{D} = 1.6$ $V$ as their severe condition for nanosheets. At a low supply the carriers rarely reach the bond energy alone, and multiple vibrational excitation, which needs many carriers, dominates; this favours the high current of $V_{G} = V_{D}$ . For nanoscale logic, equal gate and drain voltage is therefore the more likely worst case, and the substrate-current maximum applies to longer channels at higher voltages (my reading). Reference: Y. Zhang, J. Xu, T. Lu, Y. Zhang, C. Luo and G. Guo, ‘Hot Carrier Degradation in MOSFETs at Cryogenic Temperatures Down to 4.2 K’, IEEE Transactions on Device and Materials Reliability (2021), arXiv:2104.12165 (fetch-tool summary); S. Tyaginov, M. Jech, P. Sharma, J. Franco, B. Kaczer and T. Grasser, ‘On the Temperature Behavior of Hot-Carrier Degradation’, IIRW 2015 Final Report (author copy at TU Wien, fetch-tool summary); E. Bury, A. Chasin, B. Kaczer, M. Vandemaele, S. Tyaginov, J. Franco, R. Ritzenthaler, H. Mertens, P. Weckx, N. Horiguchi and D. Linten, ‘Evaluating Forksheet FET Reliability Concerns by Experimental Comparison with Co-integrated Nanosheets’, IEEE IRPS 2022, 5A.2 (KU Leuven Lirias copy) (fetch-tool summary).

Ques: Is hot-carrier degradation worse at high or low temperature?

Both are reported, and the temperature acts in two ways. Tyaginov et al. find a larger linear-current drop at 25 $^{\circ} C$ than at 75 $^{\circ} C$ for 1.8 and 2.0 $V$ stress on 44 $nm$ devices, and the gap closes at 2.2 $V$ . Heat shortens the vibrational lifetime of the bond, from 1.5 to 1.3 $ns$ , which slows the climbing of the ladder, but it also fills the high-energy tail through electron-electron scattering, which helps the single-carrier process at high voltage. Zhang et al. find hot-carrier damage more severe at cryogenic temperatures, since the mobility and the carrier energy rise. A rising temperature therefore reduces the damage at low voltage and changes it little at high voltage, so the worst case of a room-temperature part is a cold, high-current stress (my reading). Reference: S. Tyaginov, M. Jech, P. Sharma, J. Franco, B. Kaczer and T. Grasser, ‘On the Temperature Behavior of Hot-Carrier Degradation’, IIRW 2015 Final Report (author copy at TU Wien, fetch-tool summary); Y. Zhang, J. Xu, T. Lu, Y. Zhang, C. Luo and G. Guo, ‘Hot Carrier Degradation in MOSFETs at Cryogenic Temperatures Down to 4.2 K’, IEEE Transactions on Device and Materials Reliability (2021), arXiv:2104.12165 (fetch-tool summary).

Ques: Is the Weibull slope of an ultrathin high-k stack below 1 or near 2?

The sources disagree. Tao et al. report $β = 0.87$ for a SiO2/HfO2 stack of 0.91 $nm$ EOT with a 0.3 $nm$ interfacial layer, close to the 0.8 to 1 that O’Connor et al. call commonly reported. O’Connor et al. find 1.54 on Si and 1.82 on SiGe for 7.8 and 8.1 angstrom EOT HfO2 with no visible interfacial layer. With $β = m n_{b d}$ , three traps and the measured trap generation rate explain their values (m = 0.51 and 0.61, computed), and Tao’s 0.87 with m = 0.4 to 0.5 implies about two traps (computed). Both can hold for different stacks. For a projection, the lower slope is the safer choice, since it gives a shorter life for the low percentiles and a large area, until the slope of the actual stack is measured (my reading). Reference: F. Tao, H. Yang, B. Tang, Z. Tang, Y. Xu, J. Xu, Q. Wang and J. Yan, ‘TDDB characteristic and breakdown mechanism of ultra-thin SiO2/HfO2 bilayer gate dielectrics’, Journal of Semiconductors 35(6), 064003 (2014) (fetch-tool summary); R. O’Connor, G. Hughes, T. Kauerauf and L.-A. Ragnarsson, ‘Time Dependent Dielectric Breakdown and Stress Induced Leakage Current Characteristics of 8 angstrom EOT HfO2 N-MOSFETs’, IEEE IRPS 2010, BD.5.1-BD.5.5 (DCU repository copy, fetch-tool summary).

Ques: How much does self-heating shorten the life of FinFET and nanosheet logic?

The numbers depend on the load. Chhabria and Sapatnekar find an average gate temperature rise of about 5 $K$ for bulk FinFET, 12 $K$ for SOI FinFET and 18 $K$ for GAAFET (17 $K$ in their abstract), and up to 25 and 39 per cent faster BTI and HCI delay degradation. For an assumed activation energy of 0.5 $eV$ at 85 $^{\circ} C$ these rises speed up a thermally activated rate by 1.25, 1.69 and 2.17 (computed). For breakdown in stacked nanosheets, static DC self-heating can cut the life by more than 90 per cent, a factor above 10, but dynamic logic only by 42.7 to 51.4 per cent, a factor of 1.75 to 2.06 (computed). The DC value is the worst case and the dynamic value is more likely for real logic. Reference: V. A. Chhabria and S. S. Sapatnekar, ‘Impact of Self-heating on Performance and Reliability in FinFET and GAAFET Designs’, ISQED 2019 (NSF PAR copy) (fetch-tool summary); J. W. Lim, C. Yoo, K. Park and J. Jeon, ‘Self-Heating and Corner Rounding Effects on Time Dependent Dielectric Breakdown of Stacked Multi-Nanosheet FETs’, IEEE Access 11, 82208-82215 (2023) (abstract only).

Ques: Why must BTI be measured within microseconds of the end of stress?

Because the shift starts to recover at once. Kaczer et al. (2018) say that the relaxation of large devices begins within 1 $μ s$ or less after the stress is removed and continues for up to many days, as a smooth log-like curve, and in small devices as discrete steps. A delay of milliseconds therefore reads a smaller shift than the circuit sees and makes the projection optimistic. The recovery is itself thermally activated: with the emission activation energy of 1.2 $eV$ they report for a 28 $nm$ high-k technology, a defect empties $1.2 \times 1 0^{5}$ times faster at 125 $^{\circ} C$ than at 25 $^{\circ} C$ (computed). The reported shift is therefore only meaningful together with the measurement delay and the temperature, and ultra-fast or extended measure-stress-measure sequences are used. Reference: B. Kaczer, J. Franco, P. Weckx, Ph. J. Roussel, V. Putcha, E. Bury, M. Simicic, A. Chasin, D. Linten, B. Parvais, F. Catthoor, G. Rzepa, M. Waltl and T. Grasser, ‘A brief overview of gate oxide defect properties and their relation to MOSFET instabilities and device and circuit time-dependent variability’, Microelectronics Reliability 81, 186-194 (2018) (author copy at TU Wien, fetch-tool summary); E. Bury, A. Chasin, B. Kaczer, M. Vandemaele, S. Tyaginov, J. Franco, R. Ritzenthaler, H. Mertens, P. Weckx, N. Horiguchi and D. Linten, ‘Evaluating Forksheet FET Reliability Concerns by Experimental Comparison with Co-integrated Nanosheets’, IEEE IRPS 2022, 5A.2 (KU Leuven Lirias copy) (fetch-tool summary).

Ques: Why does a high-threshold ring oscillator slow down more than a standard one under the same stress?

Because the gate delay depends on the overdrive. In the alpha-power law the delay goes as $V_{D D} / (V_{D D} - V_{t h})^{α}$ , so the relative frequency change is about $α Δ V_{t h} / (V_{D D} - V_{t h})$ . For 30 $mV$ , $α = 1.3$ and a 0.75 $V$ supply this is 8.7 per cent with a 0.30 $V$ threshold and 11.1 per cent with 0.40 $V$ (computed, assumed values). Lu and Jenkins see exactly this trend in IBM processors, where the high-threshold ring degrades more, attributed to its lower overdrive. Their field data follow $Δ f / f_{0} = B t^{n}$ with n = 0.174, so a 2 per cent drift at 500 days grows to only 2.8 per cent at 10 years (computed), consistent with their expected few per cent over 5 to 10 years. Reference: P.-F. Lu and K. A. Jenkins, ‘A Built-In BTI Monitor for Long-Term Data Collection in IBM Microprocessors’, IBM Research Report RC25328, 5 November 2012 (fetch-tool summary; equations partly garbled); D. Sangani, J. Diaz-Fortuny, E. Bury, J. Franco, B. Kaczer and G. Gielen, ‘Modeling Analysis of BTI-driven degradation of a Ring Oscillator Designed in a 28-nm CMOS Technology’, IEEE Transactions on Device and Materials Reliability (2023), DOI 10.1109/TDMR.2023.3288380 (accepted version, fetch-tool summary).

Ques: How much does a power-law fit of a short BTI test change the projected life?

A great deal, because the exponent sits in the denominator of the extrapolation. With $t_{f} = t_{1} (Δ V_{cr i t} /Δ V_{1})^{1/ n}$ , a shift of 20 $mV$ after 1000 $s$ reaches 50 $mV$ after 3.6 days for n = 0.16, 1.1 days for 0.20 and 0.45 days for 0.25 (computed). Deora et al. find n = 0.155 to 0.16 for Si and SiGe pFETs, and Lu and Jenkins fit 0.174 to field data against 0.16 predicted. The voltage exponent matters as much: lowering the stress from 1.2 to 0.9 $V$ lengthens the life by 220 times for an assumed $Γ = 3$ and by 1330 for $Γ = 4$ (computed). A projection should therefore state n, $Γ$ , the measurement delay and the tolerated shift, such as the 50 $mV$ at 125 $^{\circ} C$ of Bury et al. Reference: S. Deora, A. Paul, R. Bijesh, J. Huang, G. Klimeck, G. Bersuker, P. D. Kirsch and R. Jammy, ‘Intrinsic Reliability Improvement in Biaxially Strained SiGe p-MOSFETs’, IEEE Electron Device Letters 32(3) (2011), arXiv:1012.1579 (fetch-tool summary); P.-F. Lu and K. A. Jenkins, ‘A Built-In BTI Monitor for Long-Term Data Collection in IBM Microprocessors’, IBM Research Report RC25328, 5 November 2012 (fetch-tool summary; equations partly garbled); E. Bury, A. Chasin, B. Kaczer, M. Vandemaele, S. Tyaginov, J. Franco, R. Ritzenthaler, H. Mertens, P. Weckx, N. Horiguchi and D. Linten, ‘Evaluating Forksheet FET Reliability Concerns by Experimental Comparison with Co-integrated Nanosheets’, IEEE IRPS 2022, 5A.2 (KU Leuven Lirias copy) (fetch-tool summary).

References

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B. Stampfer, “Advanced Electrical Characterization of Charge Trapping in MOS Transistors,” PhD thesis, TU Wien, section 3.3, “The Defect Centric Model.”
B. Kaczer, J. Franco, P. Weckx, Ph. J. Roussel, V. Putcha, E. Bury, M. Simicic, A. Chasin, D. Linten, B. Parvais, F. Catthoor, G. Rzepa, M. Waltl and T. Grasser, “A brief overview of gate oxide defect properties and their relation to MOSFET instabilities and device and circuit time-dependent variability,” Microelectronics Reliability, vol. 81, pp. 186-194, 2018 (author copy at TU Wien).
S. Deora, A. Paul, R. Bijesh, J. Huang, G. Klimeck, G. Bersuker, P. D. Kirsch and R. Jammy, “Intrinsic Reliability Improvement in Biaxially Strained SiGe p-MOSFETs,” IEEE Electron Device Letters, vol. 32, no. 3, 2011, doi:10.1109/LED.2010.2099101. Available: https://arxiv.org/abs/1012.1579
S. Tyaginov, M. Jech, P. Sharma, J. Franco, B. Kaczer and T. Grasser, “On the Temperature Behavior of Hot-Carrier Degradation,” IIRW 2015 Final Report (author copy at TU Wien).
E. Bury, A. Chasin, B. Kaczer, M. Vandemaele, S. Tyaginov, J. Franco, R. Ritzenthaler, H. Mertens, P. Weckx, N. Horiguchi and D. Linten, “Evaluating Forksheet FET Reliability Concerns by Experimental Comparison with Co-integrated Nanosheets,” 2022 IEEE International Reliability Physics Symposium, pp. 5A.2-1 to 5A.2-7, doi:10.1109/IRPS48227.2022.9764526. Available: https://lirias.kuleuven.be/retrieve/713053
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D. Sangani, J. Diaz-Fortuny, E. Bury, J. Franco, B. Kaczer and G. Gielen, “Modeling Analysis of BTI-driven degradation of a Ring Oscillator Designed in a 28-nm CMOS Technology,” IEEE Transactions on Device and Materials Reliability, 2023, doi:10.1109/TDMR.2023.3288380.
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Electrical Stress, Fin Field Effect Transistor (FinFET) and Gate All Around Field Effect Transistor (GAAFET) pages of this vault.

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