This page covers the instabilities of thin-film transistors used in displays and flexible electronics: hydrogenated amorphous silicon (a-Si:H), low-temperature polysilicon (LTPS), amorphous oxide semiconductors such as In-Ga-Zn-O (IGZO), and organic semiconductors. Their main failure is a slow drift of the threshold voltage under gate bias, with light and humidity as added stresses, rather than a sudden failure. The trapping physics of crystalline MOSFETs is on the CMOS Logic Transistors page and moisture transport on the Environmental and Chemical page.
1. Why It Happens
- Trigger: A gate bias held for a long time, as in the driving transistor of an OLED pixel, at a raised panel temperature (Hekmatshoar et al.; Niang et al.); light on an oxide TFT under negative bias (Ryu et al.); water from the air or the dielectric surface for organic TFTs (Sharma et al.); a high drain and gate voltage in LTPS (Liu et al.).
- Mechanism, a-Si:H: At low field, new defects are created in the channel, with a power-law shift; at high field, charge is trapped in the gate nitride with a logarithmic shift (Hekmatshoar et al.).
- Mechanism, IGZO under positive bias: Existing states redistribute with a narrow distribution of barriers near 0.75 , which is charge trapping rather than defect creation (Niang et al.; Yoon et al.).
- Mechanism, IGZO under light and negative bias: Light makes holes, which drift to the insulator and are captured by oxygen vacancies; the vacancies become doubly charged and can diffuse, which shifts the threshold negative by up to about 18 (Ryu et al.).
- Mechanism, organic TFTs: Holes in the channel oxidise adsorbed water to protons, which move into the SiO2 and screen the gate, so the threshold follows the gate voltage (Sharma et al.).
- Mechanism, LTPS: Hot carriers at the drain junction and self-heating on the glass create traps at the interface and in the poly-Si, and the on-current can first rise and then fall (Liu et al.).
- What sets the rate: The gate overdrive and the temperature through a stretched exponential with an activation energy near 0.6 to 0.75 (Sharma et al.; Niang et al.); the photon energy and intensity for NBIS (Ryu et al.); the water content and the HOMO level for organics (Sharma et al.); the drain voltage for LTPS (Liu et al.).
- Failure criterion: A threshold shift that the pixel circuit can no longer compensate, or a drive-current half-life, more than ten years in one a-Si:H process against an OLED half-life of about 65,000 (Hekmatshoar et al.).
2. Where to Look
- Location: The channel and the channel-insulator interface for all types; the gate nitride of a-Si:H at high field (Hekmatshoar et al.); the back channel and the insulator of IGZO under light (Ryu et al.); the SiO2 surface under an organic channel (Sharma et al.); the drain junction of LTPS (Liu et al.).
- Signature: A parallel shift of the transfer curve with unchanged mobility and swing for charge trapping (Yoon et al.); a shift that grows as a power of time for defect creation (Hekmatshoar et al.); a negative shift under light that persists in the dark until annealed (Ryu et al.); a turn-around of the LTPS on-current with time (Liu et al.).
- Confirm with: DC bias stress at several temperatures, analysed by stretched-exponential fitting and thermalization energy, or AC methods that avoid interrupting the stress (Niang et al.; Zhang); NBIS with monochromatic light of known photon energy; stress in vacuum and in humid air for organics (Sharma et al.).
- Look-alikes: Taking the transfer curve interrupts the stress and lets it recover, a systematic error that grows with the measurement time (Zhang). A negative shift under positive bias in some IGZO stacks comes from holes injected from the gate, not from the channel (Yoon et al.).
3. Prevention
- Design: Pixel circuits that compensate the threshold of the driving TFT; keep the overdrive low, since the shift scales with (Sharma et al.); shield oxide TFTs from light under negative bias (Ryu et al.); use LDD in LTPS to suppress hot carriers (Liu et al.).
- Material and process: Hydrogen-diluted a-Si:H with a 260 anneal, which halved from 0.44 to 0.21 (Hekmatshoar et al.); few oxygen vacancies in IGZO and a dense, stable insulator (Ryu et al.; Yoon et al.); dielectrics that hold no water for organic TFTs, since water is the root of their drift (Sharma et al.).
- Operation: Lower panel temperature, since the time constant is thermally activated; for organics, encapsulation against moisture (Sharma et al.).
- Screening and test: Bias-temperature stress at 60 to 105 with extraction of and (Niang et al.; Zhang); NBIS tests with display-relevant wavelengths (Ryu et al.).
Bias-Stress Kinetics
| Name | Formula | Related Formulae | Variables/Constants |
|---|---|---|---|
| Stretched-exponential threshold shift under gate bias | |||
| Thermalization energy of the bias-stress states | |||
| Defect creation in a-Si:H TFTs |
Light, Water and Hot Carriers
| Name | Formula | Related Formulae | Variables/Constants |
|---|---|---|---|
| Oxygen vacancies and negative bias illumination stress in IGZO | |||
| Water and protons in organic transistors | |||
| Hot carriers and self-heating in LTPS TFTs |
Important Questions
Ques: Is IGZO bias-stress instability defect creation or charge trapping?
The sources agree that it is mostly trapping or redistribution of existing states, unlike a-Si:H. Niang et al. find a narrow distribution of barriers peaked at 0.75 with a width of about 0.1 and , and conclude that the shift is not a defect-creation process as in a-Si:H but a redistribution of existing states. Yoon et al. attribute the PBTS shift of their ALD IGZO to charge trapping, since the mobility and the swing do not change. Hekmatshoar et al. show the contrast for a-Si:H, where low-field stress creates defects with a power law of exponent 0.21 to 0.44. Under light and negative bias, oxygen vacancies add a separate mechanism (Ryu et al.). The positive-bias drift of IGZO is therefore more likely trapping, which is also why it can recover. Reference: K. M. Niang, P. M. C. Barquinha, R. F. P. Martins, B. Cobb, M. J. Powell and A. J. Flewitt, ‘A thermalization energy analysis of the threshold voltage shift in amorphous indium gallium zinc oxide thin film transistors under positive gate bias stress’, Applied Physics Letters (2016, from the file name; journal and year not stated in the text read; Cambridge repository copy) (fetch-tool summary); S.-J. Yoon, N.-J. Seong, K. Choi, W.-C. Shin and S.-M. Yoon, ‘Investigations on the bias temperature stabilities of oxide thin film transistors using In-Ga-Zn-O channels prepared by atomic layer deposition’, RSC Advances (2018) (fetch-tool summary; journal inferred from the article ID); B. Hekmatshoar, K. H. Cherenack, A. Z. Kattamis, K. Long, S. Wagner and J. C. Sturm, ‘Highly stable amorphous-silicon thin-film transistors on clear plastic’, Applied Physics Letters 93, 032103 (2008) (Princeton copy, fetch-tool summary).
Ques: What is the activation energy of IGZO bias stress: 0.75 or nearly 3 electronvolts?
The numbers come from different quantities. Niang et al. find a barrier distribution peaked at 0.75 by thermalization energy analysis, and Yoon et al. report a maximum activation energy of 0.76 for a 10 channel and 1.31 for 6 from subthreshold conduction. Taking Yoon’s stretched-exponential times at 60 and 80 as Arrhenius points gives about 2.8 and 2.9 (computed), but their also changes between the temperatures, from 0.36 to 0.46, so the time constants are not directly comparable. The thermalization value of about 0.75 is therefore the more likely energy of the process, and the high value is an artefact of fitting and separately at two temperatures (my reading). Reference: K. M. Niang, P. M. C. Barquinha, R. F. P. Martins, B. Cobb, M. J. Powell and A. J. Flewitt, ‘A thermalization energy analysis of the threshold voltage shift in amorphous indium gallium zinc oxide thin film transistors under positive gate bias stress’, Applied Physics Letters (2016, from the file name; journal and year not stated in the text read; Cambridge repository copy) (fetch-tool summary); S.-J. Yoon, N.-J. Seong, K. Choi, W.-C. Shin and S.-M. Yoon, ‘Investigations on the bias temperature stabilities of oxide thin film transistors using In-Ga-Zn-O channels prepared by atomic layer deposition’, RSC Advances (2018) (fetch-tool summary; journal inferred from the article ID).
Ques: Why does light make the threshold of an IGZO TFT shift negative?
Because light frees holes that are captured by oxygen vacancies. Ryu et al. calculate that neutral vacancies have levels on average 0.81 to 1.10 above the valence band, and that the +2/0 level lies 2.85 above it when scaled to the 3.1 gap. Under negative gate bias, photo-generated holes drift to the insulator, since the valence-band offset is small, and are trapped at vacancies, which become doubly charged and positive; some ionised vacancies also diffuse to the interface. The positive charge shifts the threshold negative, by up to 18 at -20 in the experiments they cite, and persists after the light is off. With their levels, photons above about 2.0 to 2.3 , green and blue light, are enough (computed). Reference: B. Ryu, H.-K. Noh, E.-A. Choi and K. J. Chang, ‘O-vacancy as the origin of negative bias illumination stress instability in amorphous In-Ga-Zn-O thin film transistors’, arXiv:1006.4913 (journal and year not stated in the text read) (fetch-tool summary).
Ques: How large will the threshold shift of an a-Si:H TFT be after ten years?
It depends strongly on the exponent of the power law. Hekmatshoar et al. find for standard devices and 0.21 for hydrogen-diluted a-Si:H with a 260 anneal, which extrapolates to only 1.2 after ten years at a field of . With that value means 0.47 after 1000 , and the shift grows only 2.6 times from 1000 to ten years, against 7.2 times for 0.44 (computed). The authors call the extrapolation conservative, since the power law ignores the saturation of the defect density that the full stretched exponential includes. They also give a current half-life of more than ten years, about 80,000 , above the OLED half-life of about 65,000 , so the TFT no longer limits the pixel. Reference: B. Hekmatshoar, K. H. Cherenack, A. Z. Kattamis, K. Long, S. Wagner and J. C. Sturm, ‘Highly stable amorphous-silicon thin-film transistors on clear plastic’, Applied Physics Letters 93, 032103 (2008) (Princeton copy, fetch-tool summary).
Ques: Why are organic transistors unstable under gate bias even in vacuum?
Because a monolayer of water stays adsorbed on the SiO2. Sharma et al. explain the drift by holes that oxidise this water to protons, which then diffuse into the oxide; the proton diffusion, with 0.5 , is the rate-limiting step. Their model predicts , so halving the water doubles the time constant, and a HOMO 0.2 deeper raises it by 49 times at 25 (computed). All semiconductors they compare have about the same 0.6 activation energy, and the prefactor sets the large differences in stability, from for pentacene crystals to for P3HT. They conclude that the drift can only be removed by removing the water, since a much deeper HOMO makes the semiconductor itself unstable. Reference: A. Sharma, S. G. J. Mathijssen, P. A. Bobbert and D. M. de Leeuw, ‘Influence of the semiconductor oxidation potential on the operational stability of organic field-effect transistors’, Applied Physics Letters 99, 103302 (2011) (Augsburg repository copy, fetch-tool summary).
Ques: Why does the on-current of an LTPS TFT first rise and then fall under stress?
Liu et al. observe this turn-around in n-channel LDD TFTs stressed at a gate voltage of 18 : it appears after about 20 at a drain voltage of 10.5 and after 4000 at 6 , and it disappears above about 12 , where the trap density rises fast from the start. The threshold rises monotonically, so the turn-around comes from the transconductance, which increases at low drain stress, read as a higher field-effect mobility. Their C-V data at 9 drain show neither the hot-carrier signature nor the self-heating signature, so they place the turn-around outside both regimes. A short test at low drain voltage can therefore look like an improvement, and the end of life must be taken after the turn-around (my reading). Reference: H.-W. Liu, S.-M. Chiou and F.-H. Wang, ‘Turn-Around Phenomenon in the Degradation Trend of n-Type Low-Temperature Polycrystalline Silicon Thin-Film Transistors under DC Bias Stress’, Japanese Journal of Applied Physics 49, 074103 (2010) (author copy, fetch-tool summary).
References
- K. M. Niang, P. M. C. Barquinha, R. F. P. Martins, B. Cobb, M. J. Powell and A. J. Flewitt, ‘A thermalization energy analysis of the threshold voltage shift in amorphous indium gallium zinc oxide thin film transistors under positive gate bias stress’, Applied Physics Letters (2016, from the file name; journal and year not stated in the text read; Cambridge repository copy) (fetch-tool summary).
- S.-J. Yoon, N.-J. Seong, K. Choi, W.-C. Shin and S.-M. Yoon, ‘Investigations on the bias temperature stabilities of oxide thin film transistors using In-Ga-Zn-O channels prepared by atomic layer deposition’, RSC Advances (2018) (fetch-tool summary; journal inferred from the article ID).
- B. Hekmatshoar, K. H. Cherenack, A. Z. Kattamis, K. Long, S. Wagner and J. C. Sturm, ‘Highly stable amorphous-silicon thin-film transistors on clear plastic’, Applied Physics Letters 93, 032103 (2008) (Princeton copy, fetch-tool summary).
- B. Ryu, H.-K. Noh, E.-A. Choi and K. J. Chang, ‘O-vacancy as the origin of negative bias illumination stress instability in amorphous In-Ga-Zn-O thin film transistors’, arXiv:1006.4913 (journal and year not stated in the text read) (fetch-tool summary).
- A. Sharma, S. G. J. Mathijssen, P. A. Bobbert and D. M. de Leeuw, ‘Influence of the semiconductor oxidation potential on the operational stability of organic field-effect transistors’, Applied Physics Letters 99, 103302 (2011) (Augsburg repository copy, fetch-tool summary).
- H.-W. Liu, S.-M. Chiou and F.-H. Wang, ‘Turn-Around Phenomenon in the Degradation Trend of n-Type Low-Temperature Polycrystalline Silicon Thin-Film Transistors under DC Bias Stress’, Japanese Journal of Applied Physics 49, 074103 (2010) (author copy, fetch-tool summary).
- Thermal Stress page of this vault.
Related pages in this vault: Thin-Film Transistors (a-Si, LTPS, IGZO, Organic), CMOS Logic Transistors, SiC and Ga2O3 Power Devices, Environmental and Chemical, Organic Light Emitting Diode (OLED), Bipolar Transistors (BJT and SiGe HBT), Silicon Power MOSFET, IGBT and Thyristors, Ferroelectric Random Access Memory (FeRAM, PZT and HfO2).