Gain Cell (2T and 3T eDRAM)

1. Theory

Definition: A gain cell is a 2-transistor (2T) or 3-transistor (3T) dynamic memory cell in which a write transistor places charge on a storage node and a read transistor, whose gate is that node, senses it.
Built-in gain: The read transistor converts the stored voltage into a bitline current, so the charge is never shared with the bitline.
No special capacitor: The storage node is just the read transistor’s gate plus parasitic capacitances, so the cell can be made in a standard logic process (embedded DRAM).
2T vs 3T: The 3T cell adds a read-select transistor that cuts off unselected cells from the read bitline.
2T0C oxide cell: Using a wide-bandgap oxide semiconductor (e.g. IGZO) write transistor gives extremely low off-current, so no separate capacitor is needed.

2. Working Principle

Write: The write wordline turns on the write transistor and the write bitline sets the storage node voltage.
Read: The read transistor conducts a current set by the stored voltage, $(V_{S N} - V_{T H, R})^{2}$ , onto the read bitline; the read is non-destructive.
Coupling: Write-wordline feedthrough and read-line coupling shift the stored level and reduce margin.
Retention: The small storage capacitance is drained by write-transistor subthreshold and GIDL leakage and read-transistor gate leakage, so refresh is still needed.
Retention boosters: Negative write-wordline hold voltage, high-threshold write transistors, thicker read-gate oxide, or oxide-semiconductor write transistors.
Two-sided window loss: A stored 1 decays downward while a stored 0 can drift upward through the off write transistor.

3. Applications

Current status: Mostly research and niche designs rather than mainstream products.
Logic-compatible embedded memory: Dense, low-power on-die caches and buffers without a DRAM capacitor process.
Stacked 3D DRAM (research): IGZO 2T0C cells built in back-end layers above logic as a path to capacitorless, high-density DRAM.

Name	Formula	Related Formulae	Variables/Constants
Storage node capacitance	$C_{S N} = C_{o x} W_{R} L_{R} + 2 C_{o v, R} W_{R} + C_{o v, W} W_{W} + C_{j, W}$	$C_{o x} = \frac{ε _{o x}}{t _{o x}}$	$C_{S N} : t o t a l c a p a c i t an ce o f t h e s t or a g e n o d e, w hi c h i s m os tl y t h e g a t e o f t h e r e a d t r an s i s t or$ $C_{o x} : g a t e o x i d e c a p a c i t an ce p er u ni t a r e a o f t h e r e a d t r an s i s t or$ $W_{R}, L_{R} : w i d t h an d l e n g t h o f t h e r e a d t r an s i s t or$ $C_{o v, R}, C_{o v, W} : g a t e o v er l a p c a p a c i t an ces p er u ni t w i d t h o f t h e r e a d an d w r i t e t r an s i s t or s$ $W_{W} : w i d t h o f t h e w r i t e t r an s i s t or$ $C_{j, W} : j u n c t i o n c a p a c i t an ce o f t h e w r i t e t r an s i s t or a t t h e s t or a g e n o d e$ $(a se p a r a t e M O S or M I M c a p a c i t or c an b e a dd e d in p a r a l l e l t o in cr e a se C_{S N})$ $(C_{o x} W_{R} L_{R} i s t h e f u l l g a t e c a p a c i t an ce o n l y w hi l e t h e r e a d c hann e l i s in v er t e d; w i t h t h e r e a d t r an s i s t or o f f (a s t or e d 0) i t f a l l s t o t h e m u c h s ma l l er d e pl e t i o n v a l u e, so C_{S N} d e p e n d s o n t h e s t or e d l e v e l)$
Written storage node levels	$V_{S N, 1} = min [V_{D D}, V_{W W L} - V_{T H, W} (V_{S B})]$ $V_{S N, 0} \approx 0$	$V_{T H, W} (V_{S B}) = V_{T H 0} + γ (2 ϕ_{F} + V_{S B} - 2 ϕ_{F})$	$V_{S N, 1}, V_{S N, 0} : s t or a g e n o d e v o l t a g e a f t er w r i t in g a 1 an d a 0$ $V_{W W L} : w r i t e w or d l in e v o l t a g e in t h e o n s t a t e, r ai se d ab o v e V_{D D} t o p a ss a f u l l 1$ $V_{T H, W} (V_{S B}) : t h r es h o l d v o l t a g e o f t h e w r i t e t r an s i s t or in c l u d in g b o d y e f f ec t$ $V_{T H 0}, γ, ϕ_{F} : z er o - bia s t h r es h o l d v o l t a g e, b o d y e f f ec t coe f f i c i e n t an d F er mi p o t e n t ia l (a s in t h e D R A M p a g e)$
Write feedthrough and read coupling	$Δ V_{S N} = - \frac{C _{o v, W} W _{W}}{C _{S N}} Δ V_{W W L}$	$Δ V_{S N} = \frac{C _{g d, R}}{C _{S N}} Δ V_{R B L}$	$Δ V_{S N} : s hi f t o f t h e s t or a g e n o d e v o l t a g e b y c a p a c i t i v e co u pl in g$ $Δ V_{W W L} : c han g e o f t h e w r i t e w or d l in e v o l t a g e w h e n t h e w r i t e t r an s i s t or t u r n s o f f (n e g a t i v e f or a f a l l in g e d g e, w hi c h l o w er s V_{S N})$ $C_{g d, R} : g a t e - d r ain (s t or a g e n o d e t o r e a d bi tl in e) c a p a c i t an ce o f t h e r e a d t r an s i s t or$ $Δ V_{R B L} : s w in g o f t h e r e a d bi tl in e, w hi c h co u pl es ba c k in t o t h e s t or a g e n o d e d u r in g a r e a d$
Read current	$I_{r e a d} = \frac{μ _{n} C _{o x} W _{R}}{2 L _{R}} (V_{S N} - V_{T H, R})^{2}$	$Δ I_{r e a d} = I_{r e a d} (V_{S N, 1}) - I_{r e a d} (V_{S N, 0})$	$I_{r e a d} : s a t u r a t i o n c u r r e n t o f an N M O S r e a d t r an s i s t or, co n t r o l l e d b y t h e s t or a g e n o d e v o l t a g e$ $V_{S N} : s t or a g e n o d e v o l t a g e a t t h e g a t e o f t h e r e a d t r an s i s t or$ $V_{T H, R} : t h r es h o l d v o l t a g e o f t h e r e a d t r an s i s t or$ $μ_{n} : e l ec t r o n m o bi l i t y o f t h e r e a d t r an s i s t or$ $Δ I_{r e a d} : d i f f er e n ce b e tw ee n t h e r e a d c u r r e n t s o f a s t or e d 1 an d 0 (t h e r e a d w in d o w)$ $(t h e r e a d i s n o n - d es t r u c t i v e b ec a u se i t se n ses t h e g a t e o f t h e r e a d t r an s i s t or, n o t t h e s t or e d c ha r g e)$
Read time	$t_{r e a d} = \frac{C _{R B L} Δ V _{se n se}}{I _{r e a d}}$	$t_{r e a d} \propto \frac{1}{( V _{S N} - V _{T H, R} ) ^{2}}$	$t_{r e a d} : t im e f or t h e se l ec t e d ce l l t o d i sc ha r g e t h e r e a d bi tl in e b y t h e se n se v o l t a g e$ $C_{R B L} : r e a d bi tl in e c a p a c i t an ce$ $Δ V_{se n se} : bi tl in e v o l t a g e c han g e t ha t t h e se n s in g c i r c u i t c an d e t ec t$ $(a d e g r a d e d V_{S N} a t t h e e n d o f t h e r e t e n t i o n p er i o d l e n g t h e n s t h e r e a d t im e)$
Retention time	$t_{r e t} = \frac{C _{S N} Δ V _{ma x}}{I _{o f f, W} + I _{G, R} + I _{J}}$	$Δ V_{ma x} = V_{S N, 1} - V_{S N, min}$	$t_{r e t} : t im e f or t h e s t or e d 1 l e v e l t o d ec a y u n t i l t h e r e a d w in d o w i s n o l o n g er d e t ec t ab l e$ $Δ V_{ma x} : t o l er ab l e l oss o f t h e s t or a g e n o d e v o l t a g e$ $V_{S N, min} : l o w es t s t or a g e n o d e v o l t a g e t ha t s t i l l g i v es a d e t ec t ab l e r e a d c u r r e n t$ $I_{o f f, W} : o f f - s t a t e c u r r e n t o f t h e w r i t e t r an s i s t or$ $I_{G, R} : g a t e l e ak a g e o f t h e r e a d t r an s i s t or in t o t h e s t or a g e n o d e$ $I_{J} : j u n c t i o n l e ak a g e o f t h e s t or a g e n o d e$ $(t r e a t in g t h e l e ak a g e a s co n s t an t o v er t h e d ec a y)$
Write transistor off-current with word line underdrive	$I_{o f f, W} (V_{W W L, h o l d}) = I_{o f f, W} (0) \cdot 1 0^{- Δ V / S}$	$S = n \frac{k _{B} T}{q} ln 10$ $Δ V = - V_{W W L, h o l d}$	$I_{o f f, W} (0) : w r i t e t r an s i s t or o f f - c u r r e n t w i t h t h e w r i t e w or d l in e a t 0 V$ $V_{W W L, h o l d} : n e g a t i v e w r i t e w or d l in e v o l t a g e a ppl i e d d u r in g h o l d$ $Δ V : u n d er d r i v e b e l o w t h e so u r ce p o t e n t ia l$ $S : s u b t h r es h o l d s w in g in v o l t s p er d ec a d e$ $n : s u b t h r es h o l d s l o p e f a c t or$ $(t h e g ain i s l imi t e d a t l a r g e n e g a t i v e bia s b y G I D L a t t h e s t or a g e n o d e j u n c t i o n)$ $k_{B} : B o l t z mann co n s t an t$
Intrinsic carrier concentration and wide-bandgap write transistors	$n_{i} = N_{C} N_{V} e^{- E_{g} /2 k_{B} T}$	$\frac{n _{i, 2}}{n _{i, 1}} \approx e^{- (E_{g 2} - E_{g 1}) /2 k_{B} T}$ $I_{g e n} \propto n_{i}$	$n_{i} : in t r in s i c c a r r i er co n ce n t r a t i o n o f t h e c hann e l ma t er ia l$ $N_{C}, N_{V} : e f f ec t i v e d e n s i t i es o f s t a t es o f t h e co n d u c t i o n an d v a l e n ce ban d s$ $E_{g} : ban d g a p o f t h e c hann e l ma t er ia l$ $n_{i, 2} / n_{i, 1} : r a t i o o f in t r in s i c c a r r i er co n ce n t r a t i o n s o f tw o ma t er ia l s, ab o u t 1 0^{- 17} f or a 3.1 e V o x i d e se mi co n d u c t or a g ain s t s i l i co n a t 300 K (E_{g} = 1.12 e V)$ $I_{g e n} : t h er ma l g e n er a t i o n l e ak a g e, t h e p a r t o f t h e o f f - c u r r e n t t ha t sc a l es w i t h n_{i}$ $(t h e w i d e g a p r e m o v es g e n er a t i o n, G I D L an d ban d - t o - ban d l e ak a g e, w hi c h n ee d h o l es; t h e o f f - c u r r e n t t ha t r e main s in an n - t y p e o x i d e t r an s i s t or i s e l ec t r o n e mi ss i o n o v er t h e g a t e - co n t r o l l e d so u r ce ba r r i er an d t r a p - a ss i s t e d p a t h s, so i t i s se t b y t h e t h r es h o l d v o l t a g e an d s w in g, n o t b y n_{i}; t h e r a t i o a l so i g n or es t h e d i f f er e n t N_{C}, N_{V} o f t h e tw o ma t er ia l s)$ $k_{B} : B o l t z mann co n s t an t$

Important Questions

Ques: What is a gain cell, and how does it differ from the 1T1C cell?

A gain cell stores its bit as charge on the gate of a read transistor, so the stored charge is not shared with the bitline during a read. The read transistor converts the storage node voltage into a bitline current $I_{r e a d}$ , which gives the cell its gain. Compared with the 1T1C cell, the read is non-destructive, the signal does not depend on the ratio $C_{s} / C_{B L}$ , and the cell needs no tall special capacitor, so it can be made in a standard logic process (embedded DRAM). The cell is larger than a 1T1C cell, because it has two or three transistors and separate read and write lines, and the charge is still lost by leakage, so it needs refresh. Reference: K.C. Chun, P. Jain, J.H. Lee and C.H. Kim, “A 3T gain cell embedded DRAM utilizing preferential boosting for high density and low power on-die caches,” IEEE J. Solid-State Circuits 46, 1495 (2011).

Ques: Why are there 2T and 3T versions, and which transistor type is used for reading?

The 2T cell has a write transistor and a read transistor, with the read transistor connected between the read bitline and a read wordline. The 3T cell adds a read-select transistor in series with the read transistor, so that unselected cells on the same read bitline are cut off and cannot leak onto it. Either an NMOS or a PMOS read transistor can be used. An NMOS gives a higher read current and a shorter read time for the same area, while a PMOS device has lower gate tunnelling leakage in thin-oxide processes, because holes face a higher tunnelling barrier than electrons, and this helps retention. In the 3T cell the read current is that of the series stack of the two transistors. Reference: K.C. Chun, P. Jain, J.H. Lee and C.H. Kim, IEEE J. Solid-State Circuits 46, 1495 (2011); W.-C. Lee and C. Hu, “Modeling CMOS tunneling currents through ultrathin gate oxide due to conduction- and valence-band electron and hole tunneling,” IEEE Trans. Electron Devices 48, 1366 (2001).

Ques: What limits the retention time of the gain cell?

Retention is $t_{r e t} = C_{S N} Δ V_{ma x} / (I_{o f f, W} + I_{G, R} + I_{J})$ . The storage capacitance $C_{S N}$ is small because it is only the gate of the read transistor, so the same leakage drains it faster than the 1T1C capacitor. Leakage through the write transistor dominates (subthreshold and GIDL), followed by gate tunnelling through the read transistor. Retention is extended by a negative hold voltage on the write wordline, by a high-threshold write transistor, and by a thicker gate oxide on the read transistor, each of which costs speed or area. Capacitive coupling from the write wordline and the read bitline also shifts the stored level, which reduces the margin. Reference: K.C. Chun, P. Jain, J.H. Lee and C.H. Kim, IEEE J. Solid-State Circuits 46, 1495 (2011).

Ques: Why are oxide-semiconductor transistors used as the write transistor in a 2T0C cell?

Amorphous oxide semiconductors such as In-Ga-Zn-O have a bandgap of about 3 eV, so the intrinsic carrier concentration and the off-current are many orders of magnitude lower than in silicon ( $n_{i} \propto e^{- E_{g} /2 k_{B} T}$ ). The storage node then holds its charge for much longer, so the cell needs no separate capacitor (2T0C, with only the read transistor gate as storage) and can be refreshed far less often. In addition, oxide transistors can be fabricated at low temperature, so they can be stacked above the silicon logic or in a back-end layer. Strictly, the wide gap removes the hole-related leakage (generation, GIDL, band-to-band tunnelling); what remains is electron emission over the source barrier, which a high threshold keeps extremely small. Their drawbacks are the n-type-only operation (no good p-channel device) and a lower mobility than silicon. Reference: T. Kamiya, K. Nomura and H. Hosono, “Present status of amorphous In-Ga-Zn-O thin-film transistors,” Sci. Technol. Adv. Mater. 11, 044305 (2010) (material properties); A. Belmonte et al., “Capacitor-less, long-retention (>400 s) DRAM cell paving the way towards low-power and high-density monolithic 3D DRAM,” IEDM Tech. Dig. (2020) (2T0C cell).

Ques: How do the storage node levels change during hold, and why is a 0 not safe?

A stored 1 decays downward through the write transistor, the junction and the gate leakage of the read transistor, but a stored 0 can drift upward when the write bitline is held high by other cells in the column, since the write transistor is off but not perfect. The read window $Δ I_{r e a d}$ therefore shrinks from both sides. The retention time is set by whichever level first crosses the sensing limit, which depends on the bitline bias used during hold. Reference: P. Meinerzhagen, A. Teman, R. Giterman, N. Edri, A. Burg and A. Fish, Gain-Cell Embedded DRAMs for Low-Power VLSI Systems-on-Chip, Springer, 2018.

Quartz 5

Explorer